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On May 21, 2:13=A0pm, "Andrew Holme" <a...@nospam.co.uk> wrote: > "austin" <aus...@xilinx.com> wrote in message > > news:a193c66c-bf74-4f77-ba75-a18ba5957165@w35g2000prg.googlegroups.com... > > > > > Syms, > > > The DCM never attenuates jitter. =A0It can not be accidentally 'correct= ' > > all the time (zig for every zag...). =A0It is a delay line. =A0What goe= s > > in, is guaranteed to come out. > > > The DCM only changes one tap at a time (based on the FACTORY_JF > > setting, it is that number times 6 or 36 -- depending on family -- > > input clocks for one tap change). =A0The FACTORY_JF is completely miss- > > leading, as the intent was to allow the DCM to tolerate input jitter, > > but correcting often, or not so often, does nothing to tolerate input > > jitter. =A0And since it only updates one tap, the FACTORY_JF also does > > nothing to increase or decrease the output jitter. =A0The only time we > > recommended changing the FACTORY_JF setting was for the Vccaux dV/dt ' > > issue' on Virtex II (subsequently fixed in all later devices). > > > I suspect that if the output is a PWM signal, that jitter is no issue > > whatsoever, as the PWM signal is a signal that has potentially 100% > > "jitter" just to do what it is supposed to be doing. =A0I am not sure > > what the poster really is concerned about. > > Hi Austin, > > I'm building fractional-N synthesizers like this using the Spartan 3: > > http://www.holmea.demon.co.uk/Frac3/Main.htm > > > There is a hidden setting to freeze the DCM updates of the taps, but > > it really isn't of any use, other than for testing (does the added tap > > switch jitter break the design? =A0If so, you are so close to your > > timing margin -- no slack -- that you really need to find and > > constrain the paths where the device has insufficient slack). > > > Austin > > What is the hidden setting? > > I'm designing a new synthesizer with two PLLs. =A0One PLL is the same as = in my > design =A0above. =A0The other will lock the VCXO reference to an external > standard. =A0The standard is a very clean =A0and stable 5 MHz which I wou= ld like > to divide down to 1 MHz or 500 KHz. =A0Unfortunately, in the first spin o= f the > PCB, the 5 MHz enters on an LVDS pair in a corner close to one of the DCM= s, > and I was wondering if I could use the DCM to do the division. =A0Next ti= me, I > will probably use a global clock pair as I do for the VCO and XCO clocks. If your final output is a PWM signal synchronous to the 5 MHz input clock, wouldn't it make sense to re-clock it with an external part (picoGate or similar flip-flop) using the clean 5 MHz? Then your FPGA jitter just needs to stay within the portion of a cycle time to guarantee setup and hold to the external flip-flop. You could also make sure the external flop has a clean Vcc for a stable analog PWM voltage. Regards, GaborArticle: 140701
"austin" <austin@xilinx.com> wrote in message news:a193c66c-bf74-4f77-ba75-a18ba5957165@w35g2000prg.googlegroups.com... > Syms, > > The DCM never attenuates jitter. It can not be accidentally 'correct' > all the time (zig for every zag...). It is a delay line. What goes > in, is guaranteed to come out. > Hi Austin, But it is _possible_ for a DLL to attenuate jitter. I wonder why the DCM doesn't? Googling :- dll jitter attenuator gives plenty of hits. What about clock synthesis mode? I.e. using the CLKFX output. Clearly it's not just a delay line in this mode. I assume the DCM measures the incoming period and servos the delay line length to match the required output. It's not beyond the wit of man to see how this _could_ be used to attenuate jitter. Cheers, Syms.Article: 140702
It is weird that these newsgroups are getting swamped with SPAM recently!? I wonder if Google or whoever takes care of these newsgroups can do a better job of filtering or deleting them? -- AmalArticle: 140703
On May 21, 9:44=A0am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Thu, 21 May 2009 08:56:15 -0700 (PDT), Weng Tianxiang wrote: > >If M5 Xilinx implementation were carried out for M3 or M4, you > >couldn't tell there was a transaction on X, > >because it didn't generate a transaction information except it really > >happend internally. > >It may violate the true spirit of coding, but it doesn't hurt anybody > >and always gives the correct result. > > Yes, I completely agree. =A0They are the same for synthesis, > in every tool I have tried. > > >M9: process (X, Y1) > >begin > > =A0 =A0if X =3D '1' then > > =A0 =A0 =A0 =A0Y <=3D Y1; > > =A0 =A0end if; > >end process; > > >Does it mean: > >X is connected to the latch enable terminal and Y1 to data input > >terminal and Y is configured as a transparent latch? > > Yes, exactly. =A0It is a good description both for simulation > and for synthesis. =A0The problem, of course, is that many > FPGAs do not have good latch primitives (except, maybe, on > their I/O pads) and so you can get very strange hardware > implementations that will cause trouble with static > timing analysis. > > Regards > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. Hi Jonathan, Thank you for your answer. Have you received my email? WengArticle: 140704
On Fri, 22 May 2009 06:52:40 -0700 (PDT), Weng Tianxiang wrote: >Have you received my email? no, not yet. Just put the six-letter name of my company in place of MYCOMPANY in the email address. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 140705
> I have tried this new system, but still we have not. ???? > I have place a FIR interpolator x2 before to enter in the fifo: > > In Burst Mode = IFFT (at 64MHz / 2) ---> FIR Interpolator x2 (64MHz) > ---> FIFO > > In Timing Mode = FIFO (at 64MHz / 3.5 --- Nominal sample time 64MHz / > 7 after interpolation x2 new sample time is 64MHz / 3.5) > > How interpolate "New sample time is 64MHz / 3.5" of 3.5 to achieve > clock Rate of 64MHz ? Sorry, I don't understand what you are trying to say... Are you using an online translator? /MikhailArticle: 140706
I have installed ISE 10.1 on a 64-bit box running RHEL 5.3, but am
having problems with a number of the tools (including fpga_editor which
dies, and edif2ngc which segfaults).
My latest problem shows up when I invoke xdl in -ncd2xdl mode:
> [xxxx@xxxx test]$ xdl -ncd2xdl uart.ncd
> Release 10.1 - xdl K.39 (lin64)
> Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
>
> /usr/local/Xilinx/10.1/ISE/bin/lin64/unwrapped/xdl: symbol lookup
> error: /usr/local/Xilinx/10.1/ISE/bin/lin64/unwrapped/xdl: undefined
> symbol: _ZNK3Xdl7Pds2Xdl7Options8ForceCfgEv
The results are the same when I invoke the non-64-bit version of the
utility.
My LD_LIBRARY_PATH is built upon what the ISE installer suggests:
> [xxxx@xxxx ~]$ echo $LD_LIBRARY_PATH
> /usr/local/lib64:/usr/local/Xilinx/10.1/ChipScope/lib/lin64:
> /usr/local/Xilinx/10.1/ChipScope/xilinx/lib/lin64:
> /usr/local/Xilinx/10.1/EDK/lib/lin64:
> /usr/local/Xilinx/10.1/ISE/lib/lin64:/usr/X11R6/lib:
> ...
When I explicitly go looking for the symbol, I find it referenced in the
xdl utility, but never anywhere else:
> [xxxx@xxxx test]$ find . -exec grep -nH ForceCfg {} \;
> Binary file ./bin/lin/unwrapped/xdl matches
> Binary file ./bin/lin64/unwrapped/xdl matches
Does anyone know the proper incantation to use, or am I correctly
concluding that my installation is missing something?
Article: 140707On Fri, 22 May 2009 11:57:36 +0100, Martin Thompson wrote: >I noticed whilst delving with FPGA editor into Xilinx devices that >there is a latch option within the flipflop block - have you ever used >them? Will synth tools map to them do you know? I've always steered clear of latches in FPGAs, for all the standard reasons. You're right, the slice FFs can be configured as latches, and ISE uses them correctly - at least, it did with the simple testcases I tried. And ISE's static timing analysis seems to handle them correctly, though I confess I haven't done a really detailed examination of how all that works. I'm still reluctant to use latches for mainstream design, but I guess that just shows I'm boring and unadventurous :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 140708
As is it's fully device independent VHDL. UFM code not written correctly yet. > once you start a video logical next steps are > 2) release RECORD button > 3) upload to youtube [optional] I will when I get that far. > are you still recording? > or what it is what you started? > if you started thinkig about adding video to nibz then why not stop > thinking and go on doing? I was asking for commentary. I will be doing it quite soon. I was wondering if suit a video mode would be the most logical. > if something feels good to you then go ahead and and do it. > why do you need someone to tell you that? > > FYI most people are used to count memory capacity in > bits or bytes, you are using "jacko cell's as measurement > unit this is not so well known, at least now > > if you want comment on the new nibz: > > 1) MAX II is WAY too expensive for considering to be used for soft > processor, so it is totally nonsense targetting MAX II > 2) a soft core optimized for MAX II makes little to none sense on any > other FPGA than MAX II > > based on [1] and [2] you should get some decent FPGA board and make > some real processor that has real use also. > if you need some board, I would be happy to donate some. When I run out of space on the 1270 I may take you up on that. > sorry that i say what i think, some people do not appreciate it, but > it is what i think really > i tried to make soft core useable on MAX II - 240, but never fully > finished it, it may have been useful, as 240 is still cheap > but core that is useable in 1270 or 2220 makes no sense as the price > is not comparable any more. About 40 dollars. It is getting higher. > I am doing something that is optimized for one FPGA as well, but i'd > say that makes sense in my case > the design AP32ACT is optimized for A3P060 and > 1) is fully tested on target board > 2) utilizes nearly 100% of _any_ type of resources available in that > FPGA > 3) is supported by high level language compiler > 4) has proven tested uart bootloader > 5) has proven tested SD card bootloader > 6) has several demos, interrupt handler, character LCD hello,.. Cool. > funnily, I am thinking adding video too :) Cool. > but, I am not considering the AP32ACT to be used in any other FPGA > then the one it was originally targetted for, > because any other FPGA (i dont call MAX II FPGA, they are CPLDs') has > more resources useable and can use > more featured soft core Yes it is a CPLD, but the nibz is device independent so may be useful for some FPGAs too. Especially if a large hardware thing needs a little controller for some IO level management on the FPGA. cheers jackoArticle: 140709
On May 22, 3:26=A0pm, Neil Steiner <neil.stei...@east.isi.edu> wrote:
> I have installed ISE 10.1 on a 64-bit box running RHEL 5.3, but am
> having problems with a number of the tools (including fpga_editor which
> dies, and edif2ngc which segfaults).
>
> My latest problem shows up when I invoke xdl in -ncd2xdl mode:
>
> =A0> [xxxx@xxxx test]$ xdl -ncd2xdl uart.ncd
> =A0> Release 10.1 - xdl K.39 (lin64)
> =A0> Copyright (c) 1995-2008 Xilinx, Inc. =A0All rights reserved.
> =A0>
> =A0> /usr/local/Xilinx/10.1/ISE/bin/lin64/unwrapped/xdl: symbol lookup
> =A0> error: /usr/local/Xilinx/10.1/ISE/bin/lin64/unwrapped/xdl: undefined
> =A0> symbol: _ZNK3Xdl7Pds2Xdl7Options8ForceCfgEv
>
> The results are the same when I invoke the non-64-bit version of the
> utility.
>
> My LD_LIBRARY_PATH is built upon what the ISE installer suggests:
>
> =A0> [xxxx@xxxx ~]$ echo $LD_LIBRARY_PATH
> =A0> /usr/local/lib64:/usr/local/Xilinx/10.1/ChipScope/lib/lin64:
> =A0> /usr/local/Xilinx/10.1/ChipScope/xilinx/lib/lin64:
> =A0> /usr/local/Xilinx/10.1/EDK/lib/lin64:
> =A0> /usr/local/Xilinx/10.1/ISE/lib/lin64:/usr/X11R6/lib:
> =A0> ...
>
> When I explicitly go looking for the symbol, I find it referenced in the
> xdl utility, but never anywhere else:
>
> =A0> [xxxx@xxxx test]$ find . -exec grep -nH ForceCfg {} \;
> =A0> Binary file ./bin/lin/unwrapped/xdl matches
> =A0> Binary file ./bin/lin64/unwrapped/xdl matches
>
> Does anyone know the proper incantation to use, or am I correctly
> concluding that my installation is missing something?
You should run the set up script which comes with ISE (and the
corresponding one for EDK).
> . /usr/local/Xilinx/10.1/ISE/settings64.sh
I've had no problems with ise/edif2ndc/xdl when the ISE environment is
set up this way (I have a function in .bashrc to set this up when I
need it as these settings stop other things from working properly).
fpga_editor is a bit harder - first you want "openmotif22" installed.
> yum install openmotif22
Next there's some Xilinx weirdness which may require you to;
> export DISPLAY=3D:0
Then it seems to run ok.
(NOTE: running centos 5.3 not RHEL, but pretty much the same thing)
Cheers,
Andy.
Article: 140710On Fri, 22 May 2009 06:47:03 -0700 (PDT) Amal <akhailtash@gmail.com> wrote: > It is weird that these newsgroups are getting swamped with SPAM > recently!? I wonder if Google or whoever takes care of these > newsgroups can do a better job of filtering or deleting them? > > -- Amal The real problem at the moment seems to coming through usenetmonster. I tried using their X-Complaints-To, but they seem to not give a damn. So instead I now killfile anything coming through on their Message-ID. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 140711
On May 22, 6:47 am, Amal <akhailt...@gmail.com> wrote: > It is weird that these newsgroups are getting swamped with SPAM > recently!? I wonder if Google or whoever takes care of these > newsgroups can do a better job of filtering or deleting them? > > -- Amal We will have peace in the Middle East before Google does anything about SPAM. There were a number of people that were manually shutting it off (by changing the subject line to minimize its annoyance), but the format fascists complained too much, and Google turned off their ability to shut it down. So long as we're all bottom-posting, all is good, right?Article: 140712
On May 20, 10:53 pm, David Antliff <david.antl...@gmail.com> wrote: > On May 21, 3:37 pm, Matthew Hicks <mdhic...@uiuc.edu> wrote: > > > Are you sure that the settings you are using are identical. I was under > > the impression that ISE was just a GUI wrapper that sent commands to a common > > set of implementation programs. > > Hi Matthew, > > I'm working with Andrew on this project. > > The settings are not identical because ngdbuild.exe invoked by ISE has > an '-ise project.ise' and '-intstyle ise' options. We want to avoid > the use of the .ise project file entirely. > > Also it seems that the GUI calls a different set of executables in the > "unwrapped" subdirectory of "ISE/bin/nt". It also passes the ISE > project file as a parameter and there's evidence that some settings > (such as the UCF file) are drawn from this. As I mention later, > running the same executable as the ISE generates a strange fatal > exception. > > Let me try and describe the issue fully. > > - we are using Xilinx 10.1 service pack 3 on Windows XP, and a recent > installation of Cygwin. > - we are trying to incorporate Xilinx into our automated build system > - so we are running the Xilinx command-line applications from a GNU > Makefile invoked from a Cygwin bash shell. > - we want to avoid the project .ise file completely as this seems to > change every time anyone opens it - this makes build tracking > difficult and therefore the .ise file is unsuitable as an input to our > automated build process. > - we first synthesize an EDIF file with Synplify 9.6.2 - this is > called FPGA_DAC16V2.edf in the examples below > - the Xilinx Project Navigator ISE file contains just two sources: > FPGA_DAC16V2.edf > Constraints/FPGA_DAC16V2.ucf > > Once we have our EDIF, we wanted to see how to drive the Xilinx > Translate process (ngdbuild.exe) from the command line: > > - the <project>.cmd_log file that Project Navigator creates during > Translate shows ngdbuild executing as follows: > > ngdbuild -ise "D:/DAC_16v2/FPGA_DAC16V2/PAR/FPGA_DAC16V2/ > FPGA_DAC16V2.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc3s1000- > ft256-4 "D:/DAC_16v2/FPGA_DAC16V2/Synthesis/FPGA_DAC16V2/rev_1/ > FPGA_DAC16V2.edf" FPGA_DAC16V2.ngd > > - hmm, there are two 'ngdbuild.exe' programs under .../ISE/bin/nt - > which one is being run? We think it's 'bin/nt/unwrapped/ngdbuild.exe'. > - anyway, we note the '-i' option means 'ignore the User Constraints > File', although the log output shows: > ... > Reading in constraint information from 'Constraints/ > FPGA_DAC16v2.ucf'... > > ... > > - we believe ngdbuild is picking up the presence of this UCF file > from the referenced .ise file, but perhaps not actually applying the > constraints due to -i option. > - now, because we want to remove the .ise file from our process, we > manually converted this into the following command using "xflow" > integration: > > D:/Xilinx/10.1/ISE/bin/nt/ngdbuild.exe -intstyle xflow -dd _ngo -nt > timestamp -i -p xc3s1000-ft256-4 > "D:/DAC_16v2/FPGA_DAC16V2/Synthesis/FPGA_DAC16V2/rev_1/ > FPGA_DAC16V2.edf" FPGA_DAC16V2.ngd > > However the log output from this shows that this time, the constraint > information is not read, presumably because ngdbuild does not know > about the UCF file. This also results in a file about 100kb smaller > than the ISE generated .ngd file - certainly a different output. If > the entire process is run to generate a .bit file, a binary diff shows > these two .bit files as *significantly* different. > > - so we determine that the UCF is probably required, changing the > command line to (replacing -i with -uc <file>): > > D:/Xilinx/10.1/ISE/bin/nt/ngdbuild.exe -intstyle xflow -dd _ngo -nt > timestamp -uc Constraints/FPGA_DAC16V2.ucf -p xc3s1000-ft256-4 "D:/ > DAC_16v2/FPGA_DAC16V2/Synthesis/FPGA_DAC16V2/rev_1/FPGA_DAC16V2.edf" > FPGA_DAC16V2.ngd > > HOWEVER > > Instead of "Reading in constraint information from 'Constraints/ > FPGA_DAC16v2.ucf'..." we see this instead: > > ... > Applying constraints in "d:/DAC_16v2/FPGA_DAC16V2/PAR/FPGA_DAC16V2/ > Constraints/FPGA_DAC16V2.ucf" to the design... > ... > > This is not what the ISE flow said it was doing. It read the UCF file > but it certainly didn't say it was applying the constraints! > > Not only this, but the resulting .ngd file is still different - in > this case, the ISE generated .ngd file is 5333871 bytes and the one > generated by the commandline is only 5333798 bytes, or 73 bytes > smaller. A binary diff shows the files are almost entirely different. > This results in all other files beyond ngdbuild (such as map, par, > etc) to be different too. And the problem is, we don't know what is > actually different! > > Interestingly, although all the resulting intermediate files that > follow on from this are different between the two processes, the > final .bit file is thankfully identical except for a few bytes that > look like a timestamp near the top of the file. This is a huge relief! > However we would still like to know what is going on because if we > can't generate identical ngd files, or at least be sure that they > differ only by a timestamp, then building confidence in our build > system will be difficult. Who is to say that future builds will > deviate in unknown ways? > > We would like the output from ISE to exactly match the output from the > commandline, and if this is not possible then we'd like to know why > the two output files differ. > > This raises a few questions: > > 1. is the .ngd output file encrypted or perhaps compressed? This would > explain the massive difference in the two files, especially if there's > a timestamp embedded in them. > > 2. how can we get the output .ngd files to be the same without > referencing the .ise file - what are we missing on the command line? > > 3. why does the ISE flow appear to not apply the UCF constraints, yet > if we don't do this with our command-line build, the resulting .bit > file is completely different. > > 4. why does the .ise Project file continually change? Even running > 'ngdbuild -ise FPGA_DAC16V2.ise -h' to display the program's HELP text > causes the .ise file to change! Why? This makes it very difficult to > manage in a Source Control tool because it's continually changing > without a clear reason. > > 5. what is the difference between the file .../ISE/bin/nt/ngdbuild.exe > and .../ISE/bin/nt/unwrapped/ngdbuild.exe? The 'unwrapped' version of > ngdbuild.exe is used by ISE but when used in the example command-lines > above it frequently fails to find the UCF file and aborts: > > ERROR:ProjectMgmt:356 - Problem loading constraints. > ... > FATAL_ERROR:NgdBuild:Portability/export/Port_Main.h:143:1.6 - This > application > has discovered an exceptional condition from which it cannot > recover. > Process will terminate. For technical support on this issue, please > open a > WebCase with this project attached athttp://www.xilinx.com/support. > > I assume from this that we are not supposed to be calling the > 'unwrapped' version of the exe file? Perhaps this is for internal ISE > use only? > > So it appears it is not possible to run a). the same ngdbuild > executable, or b). the same command line options if you want to > completely avoid referencing the ISE project file with a command-line > invocation of ngdbuild. > > -- David Antliff I have been successful converting a project from GUI to command line with identical bit files. Take a very close look at the log files left behind by the GUI build. There are options that you will probably not recognize - the GUI knows better than you what you want it to do :) You can get rid of the -intstyle ISE flag. I use a .prj file format and that works just fine for me. Most options can be set in a number of places. I'm not 100% sure which location for the option has priority; I had some weird results which went away when I made them all match. The XST user guide was (actually) helpful in this process. Reasonably hard to read, it looks like a disgruntled synopsys employee modeled it after the dc_shell documentation. But with a little patience and perseverance, it can be made to work. Another thing to look out for: The GUI scatters work directories all over the place. Weirdness in these directories can cause run to run inconsistencies; audit the location and cleanup of these directories carefully. ALArticle: 140713
On May 22, 3:41=A0pm, "Symon" <symon_bre...@hotmail.com> wrote:
>...
> But it is _possible_ for a DLL to attenuate jitter. I wonder why the DCM
> doesn't?
> Googling :-
> dll jitter attenuator
> gives plenty of hits.
> ...
Symon,
bizarre theorem: google give hits =3D> it can be done ;-)
anyway... if you trust such bizzarre theoreme (?!?) then try to
google: "dll jitter attenuator"
WITH quotes you obtain nothing but
some suggestion to not use quotes...
Instead if you
google "pll jitter attenuator"
some usefull result appears ;-)
Regards
Sandro
Article: 140714On 22 May, 17:53, MadHatt...@myself.com wrote: > On May 22, 6:47 am, Amal <akhailt...@gmail.com> wrote: > > > It is weird that these newsgroups are getting swamped with SPAM > > recently!? I wonder if Google or whoever takes care of these > > newsgroups can do a better job of filtering or deleting them? > > > -- Amal > > We will have peace in the Middle East before Google does anything > about SPAM. Not so. I sent complaints to Google about the spam in alt.os.development and it appears that they have not just removed the sending accounts but also deleted the spam posts sent. Maybe their responsiveness is a per-newsgroup thing. Encouraged by their apparent response I have been reporting spams in other groups to them for the last couple of months. I can't say I've seen any definite response yet but I've not been checking for specific messages and ids. Reporting spam consumes a bit of time but I presume the reason why some groups are heavily hit with spam is that spammers have been allowed to get away with it. They tell their friends and before you know it the spam levels drown out the legitimate posts. The delay was about 6 weeks for alt.os.development. It may be worth many folks reporting spam posts for a while to see if that encourages a faster response. JamesArticle: 140715
Guys, All I want to know if there is a way to specify them inside my RTL. For example there are other directives like "// synthesis full_case". I am just looking for a convenient way to include those directives in to the RTL. In my case the MCP is applied to data that travels from one clock domain to another and is properly "latched" by synchronized control logic. There are many good and bad uses for MCP ... Thanks, rudiArticle: 140716
On May 19, 1:50=A0pm, Svenn Are Bjerkem <svenn.bjer...@googlemail.com> wrote: > On May 18, 9:48=A0am, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > > > I am starting to think the problem is the use of an enumerated value > > rather than a string constant or a numerical constant. =A0I changed it > > to an integer and it still does not work when using a constant name. > > But if an integer value is used, it works ok. =A0It would seem that the > > generic input function in XST does not work with symbols, only > > values. > > Just in case it hasn't been considered: > In the XST user guide for 10.1 on page 338 to 340 the use of -generics > is mentioned. > > -- > Svenn Thanks, I figured out what was wrong. I was using constant symbols for the value and XST does not seem to recognize any user defined symbols. So I had to use integer values. RickArticle: 140717
On Fri, 22 May 2009 10:58:52 -0700 (PDT), luudee <rudolf.usselmann@gmail.com> wrote: > > >Guys, > >All I want to know if there is a way to specify them inside my >RTL. For example there are other directives like >"// synthesis full_case". > >I am just looking for a convenient way to include those directives >in to the RTL. In all my readings of synthesis tool documentation I have not seen any one of them supporting a pragma/directive like that. It's definitely not in the Verilog RTL synthesis standard either (1364.1) >In my case the MCP is applied to data that travels from one >clock domain to another and is properly "latched" by synchronized >control logic. There are many good and bad uses for MCP ... Another issue to be careful about MCP is how holds are handled. Some STA tools move the holds in a dependent way to setup MCP (Primetime) and some don't (Altera Timequest) and some are programmable (Magma). To get the same effect, you have to add different hold MCPs to different tools which make annotating the RTL extremely difficult. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 140718
Rob Gaddi <rgaddi@technologyhighland.com> wrote: >The real problem at the moment seems to coming through usenetmonster. >I tried using their X-Complaints-To, but they seem to not give a >damn. So instead I now killfile anything coming through on their >Message-ID. Google groups seem to have let a captcha-cracking spam-botnet slip beyond their control for the moment since it hits them from multiple IPs. Also readnews.com is spammer friendly due to rubbish security which allows a forged NNTP-Posting-Host, forged preloaded path, and forged abuse address (it's not really Usenet Monster) -- and their claims to have fixed the problem are demonstrably false for now. -- Dave FarranceArticle: 140719
"Dave Farrance" <DaveFarrance@OMiTTHiSyahooANDTHiS.co.uk> wrote in message news:rtud15pnvkj20ufjps5c03ijqulrte1nas@4ax.com... > Rob Gaddi <rgaddi@technologyhighland.com> wrote: > >>The real problem at the moment seems to coming through usenetmonster. >>I tried using their X-Complaints-To, but they seem to not give a >>damn. So instead I now killfile anything coming through on their >>Message-ID. > > Google groups seem to have let a captcha-cracking spam-botnet slip beyond > their control for the moment since it hits them from multiple IPs. > > Also readnews.com is spammer friendly due to rubbish security which allows > a forged NNTP-Posting-Host, forged preloaded path, and forged abuse > address (it's not really Usenet Monster) -- and their claims to have fixed > the problem are demonstrably false for now. > > -- > Dave Farrance Dave, How did you identify that these posts are really coming from readnews.com? I, too, would love to kill this crap. If readnews is the problem, I will join in the campaign. The squeaky wheel gets the grease... Thanks, Bob -- == All google group posts are automatically deleted due to spam ==Article: 140720
Hi Andy,
I appreciate the suggestions, but I'm afraid they don't seem to be helping.
>> > [xxxx@xxxx test]$ find . -exec grep -nH ForceCfg {} \;
>> > Binary file ./bin/lin/unwrapped/xdl matches
>> > Binary file ./bin/lin64/unwrapped/xdl matches
>>
>> [snipped]
>
> You should run the set up script which comes with ISE (and the
> corresponding one for EDK).
>
>> . /usr/local/Xilinx/10.1/ISE/settings64.sh
I've already defined everything that settings64.sh is defining, but even
when I explicitly source it, my problems remain.
Regardless, if *no* file or library in the $XILINX tree provides the
necessary symbol (refer to find command above), I don't see how any
amount of configuration could solve the problem.
> fpga_editor is a bit harder - first you want "openmotif22" installed.
>
>> yum install openmotif22
Okay, I had openmotif-2.3.1-2.el5.x86_64 installed, but I've now added
openmotif22-2.2.3-18.x86_64. Unfortunately, it makes no difference.
I should point out that I have no problem opening fpga_editor. I just
can't keep it from spontaneously dying when I try to open an NCD file.
> Next there's some Xilinx weirdness which may require you to;
>
>> export DISPLAY=:0
I'm actually using 'ssh -Y' and my DISPLAY variable looks healthy, and
again, there's no problem starting up the fpga_editor GUI.
Neil
Article: 140721
warning message:
INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred for signal
<array_reg>. You may be trying to describe a RAM in a way that is
incompatible with block and distributed RAM resources available on
Xilinx devices, or with a specific template that is not supported.
Please review the Xilinx resources documentation and the XST user
manual for coding guidelines. Taking advantage of RAM resources will
lead to improved device usage and reduced synthesis time..
I believe this is the offending code:
-----------------------------------------
entity fifo is
generic(
B: natural:=8; -- number of bits
W: natural:=4 -- number of address bits
);
port(
clk,
reset : in std_logic;
rd,
wr : in std_logic;
w_data : in std_logic_vector (B-1 downto 0);
empty,
notempty,
full : out std_logic;
r_data : out std_logic_vector (B-1 downto 0)
);
end fifo;
architecture arch of fifo is
type reg_file_type is array (2**W-1 downto 0) of
std_logic_vector(B-1 downto 0);
signal array_reg: reg_file_type;
-----------------------------------------
I'm just trying to figure out if this is something I could/should do
something about. I'm working with a spartan 3e chip and here's the
summary:
+++++++++++++++++++++++++++++++++++++++++++++++
Module Name:
lprj_TOP
Errors:
No Errors
Target Device:
xc3s1500-5fg456
Warnings:
98 Warnings
Product Version:
ISE 10.1.03 - Foundation
Routing Results:
All Signals Completely Routed
Design Goal:
Balanced
Timing Constraints:
All Constraints Met
Design Strategy:
Xilinx Default (unlocked)
Final Timing Score:
0 (Timing Report)
raggedstone_uart10 Partition Summary
[-]
No partition information was found.
Device Utilization Summary
[-]
Logic Utilization
Used
Available
Utilization
Note(s)
Number of Slice Flip Flops
2,126
26,624
7%
Number of 4 input LUTs
3,459
26,624
12%
Logic Distribution
Number of occupied Slices
2,900
13,312
21%
Number of Slices containing only related logic
2,900
2,900
100%
Number of Slices containing unrelated logic
0
2,900
0%
Total Number of 4 input LUTs
3,551
26,624
13%
Number used as logic
3,459
Number used as a route-thru
92
Number of bonded IOBs
Number of bonded
33
333
9%
IOB Flip Flops
1
Number of RAMB16s
2
32
6%
Number of MULT18X18s
4
32
12%
Number of BUFGMUXs
1
8
12%
+++++++++++++++++++++++++++++++++++++++++++++++
everything runs ok, I'm just trying to figure out if there is a better
way to do this, am I mis-using the chips resources, or maybe this
warning is meaningless.
Sincerely,
Jon
Article: 140722Hi Mikhail, Sorry for mya poor english ... I have place a FIR interpolator x2 before to enter in the fifo: In Burst Mode = IFFT (at 64MHz / 2) ---> FIR Interpolator x2 (64MHz) ---> FIFO In Timing Mode = FIFO (at 64MHz / 3.5 --- Nominal sample time 64MHz / after interpolation x2 new sample time is 64MHz / 3.5) How interpolate "New sample time is 64MHz / 3.5" to 3.5 to archive clock Rate of 64MHz ? > Sorry, I don't understand what you are trying to say... Are you using an > online translator? Little traslator ... sorry. Kappa.Article: 140723
On May 22, 5:26 pm, doug <x...@xx.com> wrote:
>
> Only FFs have reset.
>
that doesn't mean anything to me. maybe I inlcuded too much code in
the snippet, the only part of the code
that is causing the issue I believe is this:
-----------------------------------------------------------------------------------
type reg_file_type is array (2**W-1 downto 0) of
std_logic_vector(B-1 downto 0);
signal array_reg: reg_file_type;
-----------------------------------------------------------------------------------
the error message in question has no issue with the reset. its
complaining about <array_reg>
Article: 140724jleslie48 wrote: > warning message: > > INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred for signal > <array_reg>. You may be trying to describe a RAM in a way that is > incompatible with block and distributed RAM resources available on > Xilinx devices, or with a specific template that is not supported. > Please review the Xilinx resources documentation and the XST user > manual for coding guidelines. Taking advantage of RAM resources will > lead to improved device usage and reduced synthesis time.. > > > > I believe this is the offending code: > > ----------------------------------------- > entity fifo is > generic( > B: natural:=8; -- number of bits > W: natural:=4 -- number of address bits > ); > port( > clk, > reset : in std_logic; Only FFs have reset. > rd, > wr : in std_logic; > w_data : in std_logic_vector (B-1 downto 0); > empty, > notempty, > full : out std_logic; > r_data : out std_logic_vector (B-1 downto 0) > ); > end fifo; > > architecture arch of fifo is > type reg_file_type is array (2**W-1 downto 0) of > std_logic_vector(B-1 downto 0); > signal array_reg: reg_file_type; > > > ----------------------------------------- > > > > I'm just trying to figure out if this is something I could/should do > something about. I'm working with a spartan 3e chip and here's the > summary: > > +++++++++++++++++++++++++++++++++++++++++++++++ > Module Name: > lprj_TOP > Errors: > No Errors > Target Device: > xc3s1500-5fg456 > Warnings: > 98 Warnings > Product Version: > ISE 10.1.03 - Foundation > Routing Results: > All Signals Completely Routed > Design Goal: > Balanced > Timing Constraints: > All Constraints Met > Design Strategy: > Xilinx Default (unlocked) > Final Timing Score: > 0 (Timing Report) > > > > raggedstone_uart10 Partition Summary > [-] > No partition information was found. > > > > Device Utilization Summary > [-] > Logic Utilization > Used > Available > Utilization > Note(s) > Number of Slice Flip Flops > 2,126 > 26,624 > 7% > > Number of 4 input LUTs > 3,459 > 26,624 > 12% > > Logic Distribution > > > > > Number of occupied Slices > 2,900 > 13,312 > 21% > > Number of Slices containing only related logic > 2,900 > 2,900 > 100% > > Number of Slices containing unrelated logic > 0 > 2,900 > 0% > > Total Number of 4 input LUTs > 3,551 > 26,624 > 13% > > Number used as logic > 3,459 > > > > Number used as a route-thru > 92 > > > > Number of bonded IOBs > Number of bonded > 33 > 333 > 9% > > IOB Flip Flops > 1 > > > > Number of RAMB16s > 2 > 32 > 6% > > Number of MULT18X18s > 4 > 32 > 12% > > Number of BUFGMUXs > 1 > 8 > 12% > > > +++++++++++++++++++++++++++++++++++++++++++++++ > > > everything runs ok, I'm just trying to figure out if there is a better > way to do this, am I mis-using the chips resources, or maybe this > warning is meaningless. > > Sincerely, > > Jon
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