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On May 21, 12:40=A0am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Wed, 20 May 2009 18:50:56 -0700 (PDT), Weng Tianxiang wrote:
> >I am trying to claim the following things in VHDL in
> >some written materials, and want to know if they are absolute
> >correct practically based on Xilinx FPGA implementations, not
> >theoretically on ModelSim simulations.
>
> That's a very strange way to look at it. =A0The VHDL language
> is defined by its simulation semantics. =A0Synthesis creates
> hardware that conforms to a certain (very useful) subset
> of those behaviours. =A0It makes no sense to say that your
> understanding of VHDL is "absolutely correct... based on
> FPGA implementations".
>
> On the other hand, you CAN reasonably ask "do these two
> pieces of VHDL code imply identical synthesised hardware?".
>
>
>
>
>
> >signal =A0 X =A0: unsigned(63 downto 0);
> >signal =A0 X0 : unsigned(63 downto 0);
> >signal =A0 X1 : unsigned(63 downto 0);
> >signal =A0 X2 : unsigned(63 downto 0);
> >signal =A0 X3 : unsigned(63 downto 0);
> >signal =A0 A1 : std_logic;
> >signal =A0 A2 : std_logic;
> >signal =A0 A3 : std_logic;
>
> >1. The following M1 and M2 process code implementations are the same:
>
> >M1 : process(..)
> >begin
> > =A0 X <=3D X0;
> > =A0 if A1 =3D '1' then
> > =A0 =A0 =A0X <=3D X1;
> > =A0 =A0 =A0if A2 =3D '1' then
> > =A0 =A0 =A0 =A0 X <=3D X2;
> > =A0 =A0 =A0elsif A3 =3D '1' then
> > =A0 =A0 =A0 =A0 X <=3D X3;
> > =A0 =A0 =A0end if;
> > =A0 end if;
> >end process;
>
> >M2 : process(..)
> >begin
> > =A0 if A1 =3D '1' then
> > =A0 =A0 =A0if A2 =3D '1' then
> > =A0 =A0 =A0 =A0 X <=3D X2;
> > =A0 =A0 =A0elsif A3 =3D '1' then
> > =A0 =A0 =A0 =A0 X <=3D X3;
> > =A0 =A0 =A0else
> > =A0 =A0 =A0 =A0 X <=3D X1;
> > =A0 =A0 =A0end if;
> > =A0 else
> > =A0 =A0 =A0X <=3D X0;
> > =A0 end if;
> >end process;
>
> Well... single-stepping through the two pieces of
> code in a simulator will of course show slightly
> different sequences of activity, but I agree that
> the externally-visible results of the two processes
> should be identical. =A0It is impossible to tell the
> difference between
>
> =A0 Y <=3D A;
> =A0 Y <=3D B; -- completely replaces assignment Y<=3DA
>
> and
>
> =A0 Y <=3D B;
>
> (unless the evaluation of expression A has side-effects,
> of course).
>
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
>
>
>
>
> >2. The following M3 to M5 process code implementations are the same:
>
> >M3 : process(A1)
> >begin
> > =A0 if A1 =3D '1' then
> > =A0 =A0 =A0X <=3D X1;
> > =A0 else
> > =A0 =A0 =A0null;
> > =A0 end if;
> >end process;
>
> >M4 : process(A1)
> >begin
> > =A0 if A1 =3D '1' then
> > =A0 =A0 =A0X <=3D X1;
> > =A0 end if;
> >end process;
>
> I agree that these two are identical in every meaningful way.
> "null;" really does nothing.
>
> >M5 : process(A1)
> >begin
> > =A0 if A1 =3D '1' then
> > =A0 =A0 =A0X <=3D X1;
> > =A0 else
> > =A0 =A0 =A0X <=3D X;
> > =A0 end if;
> >end process;
>
> No, this is not the same. =A0In M5 but not in M4, when
> A1 transitions to a value that is not '1', signal X
> is written; there will be no value-change on X as a
> result, for sure, but there *is* a transaction on X
> and that could be detected, outside the process,
> with the 'transaction, 'active or 'quiet attributes.
>
> None of the processes M3 to M5 follow any conventional
> synthesis template. =A0If you had included X1 in the
> sensitivity list, they would all be perfectly good
> descriptions of a transparent latch. =A0If you had
> rewritten the condition as "if rising_edge(A1)" they
> would all be perfectly good descriptions of a register.
>
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
>
>
>
>
> >3. The following M6 to M8 process code implementations are the same:
>
> >M6 : process(CLK)
> >begin
> > =A0 if CLK'event and CLK =3D '1' then
> > =A0 =A0 =A0if A1 =3D '1' then
> > =A0 =A0 =A0 =A0 X <=3D X1;
> > =A0 =A0 =A0else
> > =A0 =A0 =A0 =A0 null;
> > =A0 =A0 =A0end if;
> > =A0 end if;
> >end process;
>
> >M7 : process(CLK)
> >begin
> > =A0 if CLK'event and CLK =3D '1' then
> > =A0 =A0 =A0if A1 =3D '1' then
> > =A0 =A0 =A0 =A0 X <=3D X1;
> > =A0 =A0 =A0end if;
> > =A0 end if;
> >end process;
>
> M6 and M7 are completely identical in behaviour, yes.
>
> >M8 : process(CLK)
> >begin
> > =A0 if CLK'event and CLK =3D '1' then
> > =A0 =A0 =A0if A1 =3D '1' then
> > =A0 =A0 =A0 =A0 X <=3D X1;
> > =A0 =A0 =A0else
> > =A0 =A0 =A0 =A0 X <=3D X;
> > =A0 =A0 =A0end if;
> > =A0 end if;
> >end process;
>
> Same discussion as for M5, above.
>
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.- Hide quote=
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Hi Jonathan,
Once again I get your valuable comments.
1. "On the other hand, you CAN reasonably ask "do these two
pieces of VHDL code imply identical synthesised hardware?". "
Yes, you are right and I accept it.
2. >M5 : process(A1)
>begin
> if A1 =3D '1' then
> X <=3D X1;
> else
> X <=3D X;
> end if;
>end process;
No, this is not the same. In M5 but not in M4, when
A1 transitions to a value that is not '1', signal X
is written; there will be no value-change on X as a
result, for sure, but there *is* a transaction on X
and that could be detected, outside the process,
with the 'transaction, 'active or 'quiet attributes.
If M5 Xilinx implementation were carried out for M3 or M4, you
couldn't tell there was a transaction on X,
because it didn't generate a transaction information except it really
happend internally.
It may violate the true spirit of coding, but it doesn't hurt anybody
and always gives the correct result.
3. I have to frankly admit that I have no hardware transparent latch
in my mind. In all my designs, there are only two data signal types:
register or combinational signal.
Your comments bring me back some ideas about transparent latch:
M9: process (X, Y1)
begin
if X =3D '1' then
Y <=3D Y1;
end if;
end process;
Does it mean:
X is connected to the latch enable terminal and Y1 to data input
terminal and Y is configured as a transparent latch?
Thank you.
Weng
Article: 140676On May 21, 3:57=A0pm, ales.gor...@gmail.com wrote: > On May 21, 10:42=A0am, CMOS <manusha1...@gmail.com> wrote: > > > > > On May 21, 9:35=A0am, "Antti.Luk...@googlemail.com" > > > <Antti.Luk...@googlemail.com> wrote: > > > On May 21, 7:30=A0am, CMOS <manusha1...@gmail.com> wrote: > > > > > On May 21, 12:17=A0am, Tommy Thorn <tommy.th...@gmail.com> wrote: > > > > > > On May 20, 11:05=A0am, CMOS <manusha1...@gmail.com> wrote: > > > > > > > hi all, > > > > > > im planning to implement barcode scanning using a CMOS sensor. = The > > > > > > processing needs to happen inside a FPGA, so im evaluating my o= ptions > > > > > > in choosing a propersoftprocessor for the task. these are my > > > > > > requirements. > > > > > > > 1) open source and need to be able to be used in commercial pro= ducts > > > > > > 2) need to have good documentation and support tools (toolchain= , > > > > > > simulators, emulators) > > > > > > 3) robust and stable > > > > > > 4) need to use in an xilinx spartan 3 device with 400K gates. > > > > > > > i know aboutprocessorsOpenRISC 1000, NIOS 2 and LEON 2, but not= sure > > > > > > how good they are with regard to my requirements, specially the= (2), > > > > > > (3) and (4) above. Please help. > > > > > > > in addition, i like to here about microblaze and its licensing = fees > > > > > > structure > > > > > > A few points: > > > > > - Nios II and MicroBlaze aren't open source, but both are very go= od. > > > > > - Is OpenRISC 1000 ok for commercial products? > > > > > - I doubt LEON 2 (and maybe OpenRISC 1000) can fit in "400K gates= " > > > > > > You could also consider YARI (http://yari.thorn.ws). It's a bit w= eak > > > > > in the documentation department though but has great tools. The > > > > > hardware debugger still work in progress, but YARI has excellent > > > > > simulation support. > > > > > > Regards, > > > > > Tommy > > > > > thanks tommy. > > > > > why do you think OpenRISC 1000 is not suitable for commercial > > > > projects? > > > > > thanks. > > > > it doesnt fir s3-400 as a starter > > > > Antti > > > hi again, > > > i decided to go with LEON 2 processor, but i could not find a download > > location for it. Can some one point me to a link? > > > thanks > > MicroBlaze is nice and easy to use, but with s3-400 you won't have > much space left. Since the processor could not digest data in real > time, you probably need a frame buffer also, so bigger FPGA is > probably inevitable. > You might consider taking this imaging development kit for a start:www.op= tomotive.si > > Cheers, > > Ales Hi Ales, thanks for the info. I will have a look in to your suggesstion as well. btw, i have decided to implement all algorithms in a normal PC first to find out processing power requirements. If requirements are too high and algorithms cannot be run inside s3-400 with required timing constraints, the whole project is kind of become useless. Assuming s3-400 is capable of delivering the throughput, what i need now is a processor (open source LGPL like) that fits inside this device without much of a problem leaving some resources for other stuff like USB core etc. This makes me to remove both OpenRISC and LEON from consideration. What are the potions i have now? I had a look in to YARI, and niktech, but not sure how much software development support (compilers, debuggers, etc) they have. I have also tried MIPS based processor as well. I need your support to chose the best one! thanksArticle: 140677
On May 21, 7:09=A0pm, CMOS <manusha1...@gmail.com> wrote: > On May 21, 3:57=A0pm, ales.gor...@gmail.com wrote: > > > > > On May 21, 10:42=A0am, CMOS <manusha1...@gmail.com> wrote: > > > > On May 21, 9:35=A0am, "Antti.Luk...@googlemail.com" > > > > <Antti.Luk...@googlemail.com> wrote: > > > > On May 21, 7:30=A0am, CMOS <manusha1...@gmail.com> wrote: > > > > > > On May 21, 12:17=A0am, Tommy Thorn <tommy.th...@gmail.com> wrote: > > > > > > > On May 20, 11:05=A0am, CMOS <manusha1...@gmail.com> wrote: > > > > > > > > hi all, > > > > > > > im planning to implement barcode scanning using a CMOS sensor= . The > > > > > > > processing needs to happen inside a FPGA, so im evaluating my= options > > > > > > > in choosing a propersoftprocessor for the task. these are my > > > > > > > requirements. > > > > > > > > 1) open source and need to be able to be used in commercial p= roducts > > > > > > > 2) need to have good documentation and support tools (toolcha= in, > > > > > > > simulators, emulators) > > > > > > > 3) robust and stable > > > > > > > 4) need to use in an xilinx spartan 3 device with 400K gates. > > > > > > > > i know aboutprocessorsOpenRISC 1000, NIOS 2 and LEON 2, but n= ot sure > > > > > > > how good they are with regard to my requirements, specially t= he (2), > > > > > > > (3) and (4) above. Please help. > > > > > > > > in addition, i like to here about microblaze and its licensin= g fees > > > > > > > structure > > > > > > > A few points: > > > > > > - Nios II and MicroBlaze aren't open source, but both are very = good. > > > > > > - Is OpenRISC 1000 ok for commercial products? > > > > > > - I doubt LEON 2 (and maybe OpenRISC 1000) can fit in "400K gat= es" > > > > > > > You could also consider YARI (http://yari.thorn.ws). It's a bit= weak > > > > > > in the documentation department though but has great tools. The > > > > > > hardware debugger still work in progress, but YARI has excellen= t > > > > > > simulation support. > > > > > > > Regards, > > > > > > Tommy > > > > > > thanks tommy. > > > > > > why do you think OpenRISC 1000 is not suitable for commercial > > > > > projects? > > > > > > thanks. > > > > > it doesnt fir s3-400 as a starter > > > > > Antti > > > > hi again, > > > > i decided to go with LEON 2 processor, but i could not find a downloa= d > > > location for it. Can some one point me to a link? > > > > thanks > > > MicroBlaze is nice and easy to use, but with s3-400 you won't have > > much space left. Since the processor could not digest data in real > > time, you probably need a frame buffer also, so bigger FPGA is > > probably inevitable. > > You might consider taking this imaging development kit for a start:www.= optomotive.si > > > Cheers, > > > Ales > > Hi Ales, thanks for the info. I will have a look in to your > suggesstion as well. > > btw, i have decided to implement all algorithms in a normal PC first > to find out processing power requirements. If requirements are too > high and algorithms cannot be run inside s3-400 with required timing > constraints, the whole project is kind of become useless. > > Assuming s3-400 is capable of delivering the throughput, what i need > now is a processor (open source LGPL like) that fits inside this > device without much of a problem leaving some resources for other > stuff like USB core etc. This makes me to remove both OpenRISC and > LEON from consideration. What are the potions i have now? > > I had a look in to YARI, and niktech, but not sure how much software > development support (compilers, debuggers, etc) they have. I have also > tried MIPS based processor as well. I need your support to chose the > best one! > > thanks if you think you use usb soft core you can already forget s3-400 anttiArticle: 140678
On Thu, 21 May 2009 09:09:24 -0700 (PDT) CMOS <manusha1980@gmail.com> wrote: > On May 21, 3:57=A0pm, ales.gor...@gmail.com wrote: > > On May 21, 10:42=A0am, CMOS <manusha1...@gmail.com> wrote: > > > > > > > > > On May 21, 9:35=A0am, "Antti.Luk...@googlemail.com" > > > > > <Antti.Luk...@googlemail.com> wrote: > > > > On May 21, 7:30=A0am, CMOS <manusha1...@gmail.com> wrote: > > > > > > > On May 21, 12:17=A0am, Tommy Thorn <tommy.th...@gmail.com> > > > > > wrote: > > > > > > > > On May 20, 11:05=A0am, CMOS <manusha1...@gmail.com> wrote: > > > > > > > > > hi all, > > > > > > > im planning to implement barcode scanning using a CMOS > > > > > > > sensor. The processing needs to happen inside a FPGA, so > > > > > > > im evaluating my options in choosing a > > > > > > > propersoftprocessor for the task. these are my > > > > > > > requirements. > > > > > > > > > 1) open source and need to be able to be used in > > > > > > > commercial products 2) need to have good documentation > > > > > > > and support tools (toolchain, simulators, emulators) > > > > > > > 3) robust and stable > > > > > > > 4) need to use in an xilinx spartan 3 device with 400K > > > > > > > gates. > > > > > > > > > i know aboutprocessorsOpenRISC 1000, NIOS 2 and LEON 2, > > > > > > > but not sure how good they are with regard to my > > > > > > > requirements, specially the (2), (3) and (4) above. > > > > > > > Please help. > > > > > > > > > in addition, i like to here about microblaze and its > > > > > > > licensing fees structure > > > > > > > > A few points: > > > > > > - Nios II and MicroBlaze aren't open source, but both are > > > > > > very good. > > > > > > - Is OpenRISC 1000 ok for commercial products? > > > > > > - I doubt LEON 2 (and maybe OpenRISC 1000) can fit in "400K > > > > > > gates" > > > > > > > > You could also consider YARI (http://yari.thorn.ws). It's a > > > > > > bit weak in the documentation department though but has > > > > > > great tools. The hardware debugger still work in progress, > > > > > > but YARI has excellent simulation support. > > > > > > > > Regards, > > > > > > Tommy > > > > > > > thanks tommy. > > > > > > > why do you think OpenRISC 1000 is not suitable for commercial > > > > > projects? > > > > > > > thanks. > > > > > > it doesnt fir s3-400 as a starter > > > > > > Antti > > > > > hi again, > > > > > i decided to go with LEON 2 processor, but i could not find a > > > download location for it. Can some one point me to a link? > > > > > thanks > > > > MicroBlaze is nice and easy to use, but with s3-400 you won't have > > much space left. Since the processor could not digest data in real > > time, you probably need a frame buffer also, so bigger FPGA is > > probably inevitable. > > You might consider taking this imaging development kit for a > > start:www.optomotive.si > > > > Cheers, > > > > Ales >=20 > Hi Ales, thanks for the info. I will have a look in to your > suggesstion as well. >=20 > btw, i have decided to implement all algorithms in a normal PC first > to find out processing power requirements. If requirements are too > high and algorithms cannot be run inside s3-400 with required timing > constraints, the whole project is kind of become useless. >=20 > Assuming s3-400 is capable of delivering the throughput, what i need > now is a processor (open source LGPL like) that fits inside this > device without much of a problem leaving some resources for other > stuff like USB core etc. This makes me to remove both OpenRISC and > LEON from consideration. What are the potions i have now? >=20 > I had a look in to YARI, and niktech, but not sure how much software > development support (compilers, debuggers, etc) they have. I have also > tried MIPS based processor as well. I need your support to chose the > best one! >=20 > thanks What are you actually looking for the processor to do? If you're implementing most of your algorithm in hardware (i.e., the point of an FPGA), then you should be able to get by with a fairly minimal softcore like a Picoblaze. The tool support is, well at least they're there. It's rock stable, free for practically any use in a Xilinx chip, and coding in assembly builds character. More to the point, you could put several of them in an S3-400 with room to spare. --=20 Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 140679
On May 21, 9:18=A0pm, Rob Gaddi <rga...@technologyhighland.com> wrote: > On Thu, 21 May 2009 09:09:24 -0700 (PDT) > > > > CMOS <manusha1...@gmail.com> wrote: > > On May 21, 3:57=A0pm, ales.gor...@gmail.com wrote: > > > On May 21, 10:42=A0am, CMOS <manusha1...@gmail.com> wrote: > > > > > On May 21, 9:35=A0am, "Antti.Luk...@googlemail.com" > > > > > <Antti.Luk...@googlemail.com> wrote: > > > > > On May 21, 7:30=A0am, CMOS <manusha1...@gmail.com> wrote: > > > > > > > On May 21, 12:17=A0am, Tommy Thorn <tommy.th...@gmail.com> > > > > > > wrote: > > > > > > > > On May 20, 11:05=A0am, CMOS <manusha1...@gmail.com> wrote: > > > > > > > > > hi all, > > > > > > > > im planning to implement barcode scanning using a CMOS > > > > > > > > sensor. The processing needs to happen inside a FPGA, so > > > > > > > > im evaluating my options in choosing a > > > > > > > > propersoftprocessor for the task. these are my > > > > > > > > requirements. > > > > > > > > > 1) open source and need to be able to be used in > > > > > > > > commercial products 2) need to have good documentation > > > > > > > > and support tools (toolchain, simulators, emulators) > > > > > > > > 3) robust and stable > > > > > > > > 4) need to use in an xilinx spartan 3 device with 400K > > > > > > > > gates. > > > > > > > > > i know aboutprocessorsOpenRISC 1000, NIOS 2 and LEON 2, > > > > > > > > but not sure how good they are with regard to my > > > > > > > > requirements, specially the (2), (3) and (4) above. > > > > > > > > Please help. > > > > > > > > > in addition, i like to here about microblaze and its > > > > > > > > licensing fees structure > > > > > > > > A few points: > > > > > > > - Nios II and MicroBlaze aren't open source, but both are > > > > > > > very good. > > > > > > > - Is OpenRISC 1000 ok for commercial products? > > > > > > > - I doubt LEON 2 (and maybe OpenRISC 1000) can fit in "400K > > > > > > > gates" > > > > > > > > You could also consider YARI (http://yari.thorn.ws). It's a > > > > > > > bit weak in the documentation department though but has > > > > > > > great tools. The hardware debugger still work in progress, > > > > > > > but YARI has excellent simulation support. > > > > > > > > Regards, > > > > > > > Tommy > > > > > > > thanks tommy. > > > > > > > why do you think OpenRISC 1000 is not suitable for commercial > > > > > > projects? > > > > > > > thanks. > > > > > > it doesnt fir s3-400 as a starter > > > > > > Antti > > > > > hi again, > > > > > i decided to go with LEON 2 processor, but i could not find a > > > > download location for it. Can some one point me to a link? > > > > > thanks > > > > MicroBlaze is nice and easy to use, but with s3-400 you won't have > > > much space left. Since the processor could not digest data in real > > > time, you probably need a frame buffer also, so bigger FPGA is > > > probably inevitable. > > > You might consider taking this imaging development kit for a > > > start:www.optomotive.si > > > > Cheers, > > > > Ales > > > Hi Ales, thanks for the info. I will have a look in to your > > suggesstion as well. > > > btw, i have decided to implement all algorithms in a normal PC first > > to find out processing power requirements. If requirements are too > > high and algorithms cannot be run inside s3-400 with required timing > > constraints, the whole project is kind of become useless. > > > Assuming s3-400 is capable of delivering the throughput, what i need > > now is a processor (open source LGPL like) that fits inside this > > device without much of a problem leaving some resources for other > > stuff like USB core etc. This makes me to remove both OpenRISC and > > LEON from consideration. What are the potions i have now? > > > I had a look in to YARI, and niktech, but not sure how much software > > development support (compilers, debuggers, etc) they have. I have also > > tried MIPS based processor as well. I need your support to chose the > > best one! > > > thanks > > What are you actually looking for the processor to do? =A0If you're > implementing most of your algorithm in hardware (i.e., the point of an > FPGA), then you should be able to get by with a fairly minimal > softcore like a Picoblaze. =A0The tool support is, well at least they're > there. =A0It's rock stable, free for practically any use in a Xilinx > chip, and coding in assembly builds character. =A0More to the point, you > could put several of them in an S3-400 with room to spare. > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order this is what i thought. im going to use the processor for all processing without any hardware signal processing support. Assuming s3-400 is enough, im trying to find a processor that fit it well. ThanksArticle: 140680
On Thu, 21 May 2009 09:23:13 -0700 (PDT) CMOS <manusha1980@gmail.com> wrote: > On May 21, 9:18=A0pm, Rob Gaddi <rga...@technologyhighland.com> wrote: > > On Thu, 21 May 2009 09:09:24 -0700 (PDT) > > > > > > > > CMOS <manusha1...@gmail.com> wrote: > > > On May 21, 3:57=A0pm, ales.gor...@gmail.com wrote: > > > > On May 21, 10:42=A0am, CMOS <manusha1...@gmail.com> wrote: > > > > > > > On May 21, 9:35=A0am, "Antti.Luk...@googlemail.com" > > > > > > > <Antti.Luk...@googlemail.com> wrote: > > > > > > On May 21, 7:30=A0am, CMOS <manusha1...@gmail.com> wrote: > > > > > > > > > On May 21, 12:17=A0am, Tommy Thorn <tommy.th...@gmail.com> > > > > > > > wrote: > > > > > > > > > > On May 20, 11:05=A0am, CMOS <manusha1...@gmail.com> wrote: > > > > > > > > > > > hi all, > > > > > > > > > im planning to implement barcode scanning using a CMOS > > > > > > > > > sensor. The processing needs to happen inside a FPGA, > > > > > > > > > so im evaluating my options in choosing a > > > > > > > > > propersoftprocessor for the task. these are my > > > > > > > > > requirements. > > > > > > > > > > > 1) open source and need to be able to be used in > > > > > > > > > commercial products 2) need to have good documentation > > > > > > > > > and support tools (toolchain, simulators, emulators) > > > > > > > > > 3) robust and stable > > > > > > > > > 4) need to use in an xilinx spartan 3 device with 400K > > > > > > > > > gates. > > > > > > > > > > > i know aboutprocessorsOpenRISC 1000, NIOS 2 and LEON > > > > > > > > > 2, but not sure how good they are with regard to my > > > > > > > > > requirements, specially the (2), (3) and (4) above. > > > > > > > > > Please help. > > > > > > > > > > > in addition, i like to here about microblaze and its > > > > > > > > > licensing fees structure > > > > > > > > > > A few points: > > > > > > > > - Nios II and MicroBlaze aren't open source, but both > > > > > > > > are very good. > > > > > > > > - Is OpenRISC 1000 ok for commercial products? > > > > > > > > - I doubt LEON 2 (and maybe OpenRISC 1000) can fit in > > > > > > > > "400K gates" > > > > > > > > > > You could also consider YARI (http://yari.thorn.ws). > > > > > > > > It's a bit weak in the documentation department though > > > > > > > > but has great tools. The hardware debugger still work > > > > > > > > in progress, but YARI has excellent simulation support. > > > > > > > > > > Regards, > > > > > > > > Tommy > > > > > > > > > thanks tommy. > > > > > > > > > why do you think OpenRISC 1000 is not suitable for > > > > > > > commercial projects? > > > > > > > > > thanks. > > > > > > > > it doesnt fir s3-400 as a starter > > > > > > > > Antti > > > > > > > hi again, > > > > > > > i decided to go with LEON 2 processor, but i could not find a > > > > > download location for it. Can some one point me to a link? > > > > > > > thanks > > > > > > MicroBlaze is nice and easy to use, but with s3-400 you won't > > > > have much space left. Since the processor could not digest data > > > > in real time, you probably need a frame buffer also, so bigger > > > > FPGA is probably inevitable. > > > > You might consider taking this imaging development kit for a > > > > start:www.optomotive.si > > > > > > Cheers, > > > > > > Ales > > > > > Hi Ales, thanks for the info. I will have a look in to your > > > suggesstion as well. > > > > > btw, i have decided to implement all algorithms in a normal PC > > > first to find out processing power requirements. If requirements > > > are too high and algorithms cannot be run inside s3-400 with > > > required timing constraints, the whole project is kind of become > > > useless. > > > > > Assuming s3-400 is capable of delivering the throughput, what i > > > need now is a processor (open source LGPL like) that fits inside > > > this device without much of a problem leaving some resources for > > > other stuff like USB core etc. This makes me to remove both > > > OpenRISC and LEON from consideration. What are the potions i have > > > now? > > > > > I had a look in to YARI, and niktech, but not sure how much > > > software development support (compilers, debuggers, etc) they > > > have. I have also tried MIPS based processor as well. I need your > > > support to chose the best one! > > > > > thanks > > > > What are you actually looking for the processor to do? =A0If you're > > implementing most of your algorithm in hardware (i.e., the point of > > an FPGA), then you should be able to get by with a fairly minimal > > softcore like a Picoblaze. =A0The tool support is, well at least > > they're there. =A0It's rock stable, free for practically any use in a > > Xilinx chip, and coding in assembly builds character. =A0More to the > > point, you could put several of them in an S3-400 with room to > > spare. > > > > -- > > Rob Gaddi, Highland Technology > > Email address is currently out of order >=20 > this is what i thought. > im going to use the processor for all processing without any hardware > signal processing support. Assuming s3-400 is enough, im trying to > find a processor that fit it well. >=20 > Thanks Then, not to question the baseline assumptions of your project, but if you're primarily looking for your FPGA to look like a microprocessor, perhaps you'd be better off looking for a microprocessor? --=20 Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 140681
Hello everybody, I have a Spartan 3A connected to the JTAG chain. the chain is composed only by the FPGA. When using IMPACT and I try to inizialaze the chain I have the standard error message: ERROR:iMPACT:585 - A problem may exist in the hardware configuration. Check that the cable, scan chain, and power connections are intact, that the specified scan chain configuration matches the actual hardware, and that the power supply is adequate and delivering the correct voltage. But when I click on Debug->validate chain then I have the following message Validating chain... Boundary-scan chain validated successfully. Does that mean that the chain is OK, but the problem is somewere else? my Vccaux = 2.5V, the PROG pin is High, M0,M1,M2 = 1 0 1 (1 = 3.3V could this be the problem? maybe I should have used Vccaux) Suspend = 0 Any idea please? Thanks, FrancescoArticle: 140682
On Thu, 21 May 2009 08:56:15 -0700 (PDT), Weng Tianxiang wrote: >If M5 Xilinx implementation were carried out for M3 or M4, you >couldn't tell there was a transaction on X, >because it didn't generate a transaction information except it really >happend internally. >It may violate the true spirit of coding, but it doesn't hurt anybody >and always gives the correct result. Yes, I completely agree. They are the same for synthesis, in every tool I have tried. >M9: process (X, Y1) >begin > if X = '1' then > Y <= Y1; > end if; >end process; > >Does it mean: >X is connected to the latch enable terminal and Y1 to data input >terminal and Y is configured as a transparent latch? Yes, exactly. It is a good description both for simulation and for synthesis. The problem, of course, is that many FPGAs do not have good latch primitives (except, maybe, on their I/O pads) and so you can get very strange hardware implementations that will cause trouble with static timing analysis. Regards -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 140683
Mark wrote: > Ok neat. But why not just code the algorithm in straight verilog or > VHDL, instead of C generates verilog? ... > You don't need to calculate "one-bit per clock" - rather one-bit per > ITERATION. Who says each iteration must be a clock tick? Just > implement the procedural code for the logic update of one bit and > stick a 'for' loop around it for 'n' bits. Boom, done. Let > the synthesis tool optimize, and produce the big XOR trees. I agree, but not everyone is a language wonk. This is straightforward in vhdl, and has been covered repeatedly in the vhdl newsgroup. If you have done it in verilog, let's see the code. > The C generated verilog code > is unmanageable. http://www.easics.be/webtools/crctool Is a similar generator that has been around for years. It produces the same "unmanageable" code that many have nonetheless managed to paste in and use successfully -- Mike TreselerArticle: 140684
On May 21, 4:45=A0pm, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On May 21, 5:26=A0pm, jacko <jackokr...@gmail.com> wrote: > > > > > Hi > > > 72MHz it's hot! But cool. Lower un-necessary D_O pin state transitions > > etc. Estimated 17 MIPS on 8 bit bus. > > >http://nibz.goglecode.comfordownload. Any improvements for speed or > > power efficiency while keeping low area welcome. > > > BSD license, or 1 core (instruction stream) per chip (packaged > > semiconductor or logic substrate) license. > > > 44% of MAX II 1270 C5 (527 LEs in speed technology) > > > 8 Bit data bus, and ALU now 8 bit pipelined, as 16 bit is same space > > with no pipeline. ALU completion in following instruction fetch. 16 > > bit ISA. Stack style of programming. > > > Clock possibly higher as critical path driven from latched value > > register. > > > Interleave RW for full cycle RW_O =3D '0' on both hi and low byte (quit= e > > a large part of the design). > > > A full Moore machine, all outputs driven by registers. In full custom > > this allows the large IO pad drivers to provide the feedback. Much of > > the instruction decode is pipelined due to most significant decoded > > bits are in the low byte. > > > Should be suitable for interfacing to BRAM (with common address on > > read and write) or external SRAM. > > > cheers jacko > > > p.s. much of the pipelining is only possible with a low logic area > > because of the half width data bus dual fetching of data. Even though > > the design is big endian, the fetches and stores are done little > > endian for the usual carry propergation reasons, and for instruction > > decode efficiency. > > goglecode? > > G-spot? > have you ever found it? > > Antti googlecode um yes my spelling is bad. nibzG.vhd is the filename.. Chrome doesn't (didn't) recognize the word as a spelling error. It's a full Moore state machine now, with none of the Mealy race conditions. In development Mealy is easier to flesh out a design to roughly (ignoring race conditions not sure if state transition extra terms get added automatically anyhow) do whats wanted. But in the end I had to optimize it to a Moore machine with its greater performance. I hope it's correct, but I have not built any IO yet to really test it. It looks correct on the readings of the code. I haven't put any timing constraints on it yet but speed could be raised. As 72MHz > 66MHz I don't intend to do this yet. unless a glaring error is found, this version will remain as the final one to go toward the reference system. cheers jackoArticle: 140685
> On May 20, 11:24 am, Mike Treseler wrote:
>> I can eliminate the requirement in my
>> code by adding a synchronous handshake
>> or pipeline.
>>
>> -- Mike Treseler
Andy wrote:
> Not sure I understand...
It has been my experience, that if something
I have coded doesn't make Fmax, my time
is best spent questioning my assumptions
and revising the design.
Let's say I code a 64 bit "/" operation
(which uses lpm_divide for altera)
in one tick.
Even if I properly constrain
this blob of logic to 27 ticks,
I might very well find the
resulting netlist un-routable.
Maybe I can make better use
of all that time.
-- Mike Treseler
Article: 140686"austin" <austin@xilinx.com> wrote in message news:a193c66c-bf74-4f77-ba75-a18ba5957165@w35g2000prg.googlegroups.com... > Syms, > > The DCM never attenuates jitter. It can not be accidentally 'correct' > all the time (zig for every zag...). It is a delay line. What goes > in, is guaranteed to come out. > > The DCM only changes one tap at a time (based on the FACTORY_JF > setting, it is that number times 6 or 36 -- depending on family -- > input clocks for one tap change). The FACTORY_JF is completely miss- > leading, as the intent was to allow the DCM to tolerate input jitter, > but correcting often, or not so often, does nothing to tolerate input > jitter. And since it only updates one tap, the FACTORY_JF also does > nothing to increase or decrease the output jitter. The only time we > recommended changing the FACTORY_JF setting was for the Vccaux dV/dt ' > issue' on Virtex II (subsequently fixed in all later devices). > > I suspect that if the output is a PWM signal, that jitter is no issue > whatsoever, as the PWM signal is a signal that has potentially 100% > "jitter" just to do what it is supposed to be doing. I am not sure > what the poster really is concerned about. > Hi Austin, I'm building fractional-N synthesizers like this using the Spartan 3: http://www.holmea.demon.co.uk/Frac3/Main.htm > There is a hidden setting to freeze the DCM updates of the taps, but > it really isn't of any use, other than for testing (does the added tap > switch jitter break the design? If so, you are so close to your > timing margin -- no slack -- that you really need to find and > constrain the paths where the device has insufficient slack). > > Austin What is the hidden setting? I'm designing a new synthesizer with two PLLs. One PLL is the same as in my design above. The other will lock the VCXO reference to an external standard. The standard is a very clean and stable 5 MHz which I would like to divide down to 1 MHz or 500 KHz. Unfortunately, in the first spin of the PCB, the 5 MHz enters on an LVDS pair in a corner close to one of the DCMs, and I was wondering if I could use the DCM to do the division. Next time, I will probably use a global clock pair as I do for the VCO and XCO clocks.Article: 140687
phil hays wrote:
...
> the only way that I'm aware of to get a
> consistent result is to start with a fresh directory.
ise 10.1 allows project exports of type tcl or ise.
For me, the tcl restore worked, the ise didn't.
...
> One option for doing this would be to have the make file call a Project
> Navigator Tcl script (using xtclsh). This script would create a
> fresh .ise file every run, and could also be used to run from the GUI. I
> posted a script for this sometime ago, and will update it if desired.
If do you update it, I would make use of it.
-- Mike Treseler
Article: 140688I'm starting on the video. -- The display -- =========== -- The generated vga mode is 640*480 pixels. -- This is reduced with a border (black) -- to 512*256. This is split into 1024 -- character cells of 16*8 pixels. -- The character data starts at base address -- $E000 and occupies the top 8K cells of -- memory. As there are 8 lines per character -- there is a possible 1024 character glyphs. -- This allows full bit mapped graphics. -- Each character is indirectly assigned via -- the character code and colour table in -- the lowest 1K cells of memory. It is -- shadowed behind the boot ROM and is write -- only. Each entry has the lower 10 bits as -- a character index, and 6 high bits for -- forground (15-13) and background (12-10) -- colours. RGB bit order with R being most -- significant. -- A full decenders display can be made if -- the display is turned on edge. Sounds good to me, any comments? cheers jackoArticle: 140689
I'm starting on the video. -- The display -- =========== -- The generated vga mode is 640*480 pixels. -- This is reduced with a border (black) -- to 512*256. This is split into 1024 -- character cells of 16*8 pixels. -- The character data starts at base address -- $E000 and occupies the top 8K cells of -- memory. As there are 8 lines per character -- there is a possible 1024 character glyphs. -- This allows full bit mapped graphics. -- Each character is indirectly assigned via -- the character code and colour table in -- the lowest 1K cells of memory. It is -- shadowed behind the boot ROM and is write -- only. Each entry has the lower 10 bits as -- a character index, and 6 high bits for -- forground (15-13) and background (12-10) -- colours. RGB bit order with R being most -- significant. -- A full decenders display can be made if -- the display is turned on edge. Sounds good to me, any comments? Maybe high to low index order of the raster, so only 6.25MHz memory bandwidth used cheers jackoArticle: 140690
On May 21, 2:15=A0am, Antti.Lukats wrote: > there is also TC5 available with full sources if you search > its a newer version of the TC, it has some assembler included in the > package > > TC5 is licensed as MSL Microsoft Reseach License > what says rree for non commercial Actually, it isn't that easy to find. It is included in the DDR2 controller (which is itself very interesting) test project for the BEE3 board: http://research.microsoft.com/en-us/downloads/12e67e9a-f130-4fd3-9bbd-f9e44= 8cd6775/ With the merging of the data memory and the registers, this feel even more like a Picoblaze/AVR8/PIC and the fact that it is trivial to user a larger program memory means it could be interesting even for large problems. -- JecelArticle: 140691
I'm focusing on the xilinx ip core for a while. The Fibre Channel IP core supports VII pro, V4 FX, which both have the ppc hard core ,but since V5 FXT is a more powerful device , Why doesn't it support this core for V5 FXT? And Fibre Channel IP Core in V4 FX can run in 4Gbps, but only 2Gbps in V5 LXT. why?Article: 140692
On May 21, 11:31=A0pm, Jacko <jackokr...@gmail.com> wrote: > I'm starting on the video. > > -- The display > -- =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > -- The generated vga mode is 640*480 pixels. > -- This is reduced with a border (black) > -- to 512*256. This is split into 1024 > -- character cells of 16*8 pixels. > -- The character data starts at base address > -- $E000 and occupies the top 8K cells of > -- memory. As there are 8 lines per character > -- there is a possible 1024 character glyphs. > > -- This allows full bit mapped graphics. > -- Each character is indirectly assigned via > -- the character code and colour table in > -- the lowest 1K cells of memory. It is > -- shadowed behind the boot ROM and is write > -- only. Each entry has the lower 10 bits as > -- a character index, and 6 high bits for > -- forground (15-13) and background (12-10) > -- colours. RGB bit order with R being most > -- significant. > > -- A full decenders display can be made if > -- the display is turned on edge. > > Sounds good to me, any comments? Maybe high to low index order of the > raster, so only 6.25MHz memory bandwidth used > > cheers jacko Jack once you start a video logical next steps are 2) release RECORD button 3) upload to youtube [optional] are you still recording? or what it is what you started? if you started thinkig about adding video to nibz then why not stop thinking and go on doing? if something feels good to you then go ahead and and do it. why do you need someone to tell you that? FYI most people are used to count memory capacity in bits or bytes, you are using "jacko cell's as measurement unit this is not so well known, at least now if you want comment on the new nibz: 1) MAX II is WAY too expensive for considering to be used for soft processor, so it is totally nonsense targetting MAX II 2) a soft core optimized for MAX II makes little to none sense on any other FPGA than MAX II based on [1] and [2] you should get some decent FPGA board and make some real processor that has real use also. if you need some board, I would be happy to donate some. sorry that i say what i think, some people do not appreciate it, but it is what i think really i tried to make soft core useable on MAX II - 240, but never fully finished it, it may have been useful, as 240 is still cheap but core that is useable in 1270 or 2220 makes no sense as the price is not comparable any more. I am doing something that is optimized for one FPGA as well, but i'd say that makes sense in my case the design AP32ACT is optimized for A3P060 and 1) is fully tested on target board 2) utilizes nearly 100% of _any_ type of resources available in that FPGA 3) is supported by high level language compiler 4) has proven tested uart bootloader 5) has proven tested SD card bootloader 6) has several demos, interrupt handler, character LCD hello,.. funnily, I am thinking adding video too :) but, I am not considering the AP32ACT to be used in any other FPGA then the one it was originally targetted for, because any other FPGA (i dont call MAX II FPGA, they are CPLDs') has more resources useable and can use more featured soft core AnttiArticle: 140693
On May 22, 12:06=A0am, Jecel <je...@merlintec.com> wrote: > On May 21, 2:15=A0am, Antti.Lukats wrote: > > > there is also TC5 available with full sources if you search > > its a newer version of the TC, it has some assembler included in the > > package > > > TC5 is licensed as MSL Microsoft Reseach License > > what says rree for non commercial > > Actually, it isn't that easy to find. It is included in the DDR2 > controller (which is itself very interesting) test project for the > BEE3 board: > > http://research.microsoft.com/en-us/downloads/12e67e9a-f130-4fd3-9bbd... > > With the merging of the data memory and the registers, this feel even > more like a Picoblaze/AVR8/PIC and the fact that it is trivial to user > a larger program memory means it could be interesting even for large > problems. > > -- Jecel yes it did take 2 minutes of searching well when I did NOT know it exists :) AnttiArticle: 140694
"Brian Drummond" <brian_drummond@btconnect.com> wrote in message news:cqca159a797e841uticu3qcps64a4t54pu@4ax.com... > On Wed, 20 May 2009 10:32:06 +0100, "HT-Lab" <hans64@ht-lab.com> wrote: > >>Does anybody know how to disable the CONV_INTEGER warnings in ISIM (11.1)? >> >>at 3000290500 ps(1), Instance /cpu_top_tb/U_12/ : Warning: CONV_INTEGER: >>There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been >>converted to 0. >>at 3000365500 ps(1), Instance /cpu_top_tb/U_12/ : Warning: CONV_INTEGER: >>There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been >>converted to 0. > > I don't see these errors from CONV_INTEGER because I use numeric_std > instead, > but it looks like the same situation. > > My response is to identify the worst culprits and apply "to_01" functions > in > appropriate places. Useful tip, Thanks, Hans www.ht-lab.comArticle: 140695
<Antti.Lukats@googlemail.com> wrote in message news:7ba4416d-4d55-4b6f-bd7b-879df0d8faa1@x5g2000yqk.googlegroups.com... On May 21, 5:26 pm, jacko <jackokr...@gmail.com> wrote: >> Hi >> >> 72MHz it's hot! But cool. Lower un-necessary D_O pin state transitions >> etc. Estimated 17 MIPS on 8 bit bus. .. snip > >goglecode? > >G-spot? >have you ever found it? Hahahaha, very good.....:-) Hans www.ht-lab.com > >AnttiArticle: 140696
"HT-Lab" <hans64@ht-lab.com> wrote in message news:W7QQl.80572$861.55894@newsfe12.ams2... > Does anybody know how to disable the CONV_INTEGER warnings in ISIM (11.1)? > > at 3000290500 ps(1), Instance /cpu_top_tb/U_12/ : Warning: CONV_INTEGER: > There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been > converted to 0. > at 3000365500 ps(1), Instance /cpu_top_tb/U_12/ : Warning: CONV_INTEGER: > There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been > converted to 0. > In my humble experience, having an undefined 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand is rarely intentional and I'd hate to turn off checking for all such cases. Wouldn't it be better to see why it happens, perhaps initialising some variables to get rid of any 'U's?Article: 140697
CMOS <manusha1980@gmail.com> writes: > btw, i have decided to implement all algorithms in a normal PC first > to find out processing power requirements. If requirements are too > high and algorithms cannot be run inside s3-400 with required timing > constraints, the whole project is kind of become useless. > Excellent decision. Normally, this forum has messages of the sort "I've decided to do some algorithms in FPGA, please send me code" :) One point to bear in mind - the processing that an FPGA is good at is not necessarily what a PC is good at. You need to think hard about memory, which is in short supply in an FPGA in quantity terms. Memory bandwidth to independent processing blocks can be abundant though, the FPGA you are looking at has 16 BRAMs, so if you clock them at 100MHz (not pushing the speed of the BRAMs by any means), and use them in 8-bit configuration (or even 9-bits - that's good for some image processing apps) gets you 1.6GBytes/sec of internal bandwidth (please excuse my use of the convenient but non-comms-accurate use of "bandwidth" for a short while :). Always assuming your algorithms are parallel enough to use it :) The lack of RAM changes image processing from the "PC-mindset"... An external framebuffer gets you the quantity, but you can't approach the PC's bandwidth - dual channels of 64 bit wide multi-hundred MHz DDR - with a small Spartan device. The latency of external DRAM will need accounting for to maximise your use of the external bandwidth you have available. And your PC probably has several MBytes of L2 cache, which has lower latency and yet more bandwidth... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 140698
Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> writes: > Yes, exactly. It is a good description both for simulation > and for synthesis. The problem, of course, is that many > FPGAs do not have good latch primitives (except, maybe, on > their I/O pads) and so you can get very strange hardware > implementations that will cause trouble with static > timing analysis. Hi Jonathan, I noticed whilst delving with FPGA editor into Xilinx devices that there is a latch option within the flipflop block - have you ever used them? Will synth tools map to them do you know? As an aside - the Virtex-5 version of Microblaze has 3 latches buried deep inside it... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 140699
Hi Mikhail, Thanks for the clarifying, but there is still something that I have not very clear. > From the data stream point of view an interpolate by 2 =A0filter is simpl= y a > device producing two output sample for each input sample. It can be run i= n > burst mode at any frequency which is more or equal 2x your input sample > frequency. If you are using Xilinx take a look at their FIR IP cores. I have tried this new system, but still we have not. I have place a FIR interpolator x2 before to enter in the fifo: In Burst Mode =3D IFFT (at 64MHz / 2) ---> FIR Interpolator x2 (64MHz) ---> FIFO In Timing Mode =3D FIFO (at 64MHz / 3.5 --- Nominal sample time 64MHz / 7 after interpolation x2 new sample time is 64MHz / 3.5) How interpolate "New sample time is 64MHz / 3.5" of 3.5 to achieve clock Rate of 64MHz ? Kappa.
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