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Yes, reference the DCM instructions. ---Matthew Hicks > rosaldorosa pisze: > >> I'm working on the high frequency project where I have adc converter >> able to scan Analog signal much faster then fpga. >> Is is possible to send a reference clock to ADC, then divide it (by 4 >> for example), and the resulting clock move in phase ( intentionally >> skew) into 4 phase shifted clocks. >> The simple parallel logic to multiply subtract. >> Is it possible at all? >> >> Does anyone has seen such solution in other projects? >> >> Thanks >> Robert Dorosa > I have ment divide by 4 into four parallel clock sources shifted in > phase ( 360deg/4). > Then four parallel aqusition processes. > Then combiner which collects all parallel data together ( compress). > I think it's more clear now. > Regards > Robert DorosaArticle: 141126
JuanC wrote: > If you have access to Chipscope you can run an ILA remotely using the > CSE server. You can do the same thing if using an altera signal tap > core. I guessed chipscope would do it, sadly we have no licences for that, we use Identify (since we have a University deal) I find it very good, except for the lack of remote mode. I can see it being a pain however, as the hardware is about to get sent to several remote sites.. so am sure it will come up again as a problem :( What I wish existed was that all 3 tools, (signal tap, chipscope and Identify) would have some way you could write your own plug in to interface to your Jtag.. network socket based or something. I also have another system, a VME based setup with upto 20 cards in it, all of them JTAG accessable via registers on the VME.. would be nice to be able to interface that to the tools easily... -- /\/\arc Kelly ..Just your average physicist trying to get by in a world full of normal people...Article: 141127
On Jun 7, 6:23=A0pm, iquadri <iqua...@gmail.com> wrote: > Hi. I am using Virtex-4 device for dynamic partial reconfiguration. > Partial bitstream is stored on Compact Flash Card. PowerPC is used to > fetch the partial bitstream from CF card to ICAP. How to measure the > power consumption for the dynamic partial reconfiguration using > PlanAhead and ISE, EDK? It seems difficult to use XPower to estimate > the power for dynamic partial reconfiguration. Any answer would be > great for me. Thanks. iquadri, There are two types of power consumption involved: 1- Power consumption during the process of Partial reconfiguration (Depends more on the device itself) 2- Power consumption after the (partial) reconfiguration is loaded in the FPGA device (Dependant on switching activity in the device). I think that the tools like PlanAhead,ISE, EDK may not be very helpful in this regard. Although you can use Xpower to approximate netlists' power consumption against a given frequency. However, a better approach would be to use a power analysis apparatus used in the following research work: http://portal.acm.org/citation.cfm?id=3D1503062 http://www.springerlink.com/content/hpj1065030307132/ Hope this helps, /MoazzamArticle: 141128
Hi all, I am wondering if it is possible to have both the 06 and O5 Outputs of the LUT registered with the Flip-flop within the Slice when I use the LUT to implement two 5 Input Functions. My understanding is No but could not find a confirmation on the User Guide. Can anyone clarify? Thanks in advance, Venkat.Article: 141129
why is it that refresh to refresh period in case of 1gbddr comes to the order of 34 cycles and in case of 2gbDDR comes to the order of 52 cycles(as per Micron Data sheet)where as logically the refresh to refresh period should be less in case of bigger memory..can somebody clarify this for me...???? Thanks in advance DAJArticle: 141130
I wrote: > In fact, all the options for getting that > extra write port pretty much annul the performance benefits of running > multiple instructions. (And I haven't even started talking about the > bypass network and the hazard detection here). rickman kibitzed: > You can use two write ports on block rams. =A0They can be hard to infer, > but they can always be instantiated. Your register files are write-only? You can't have two write ports to a memory block if you need to read arbitrary locations as well. Unfortunately there isn't any one good solution, tough there are some options. For example : - Time multiplexing (there goes the benefit of superscalar), - Banking (Complicated and performance depends on few conflicts), - Inferred from logic (expensive, but sometimes the best option), and - "Distributed": represent each location as the sum of parts (one cycle extra write latency and uses a lot of memory blocks, eg. 2w4r =3D 10 blocks). TommyArticle: 141131
It has been a while since Xilinx started with "New Virtex and Spartan is here!" but there is no concrete data about actual devices yet. New devices have some interesting features ( judging from PR materials) but seem a bit behind Altera's newest devices at least in PCIe connectivity front. All you will get with Spartan 5 wil be PCIe x1... Are there non-Virtex cheap devices with decent PCIe x1 with Xilinx and when will new devices be available ?Article: 141132
On Jun 8, 3:19=A0am, Tommy Thorn <tommy.th...@gmail.com> wrote: > I wrote: > > In fact, all the options for getting that > > extra write port pretty much annul the performance benefits of running > > multiple instructions. (And I haven't even started talking about the > > bypass network and the hazard detection here). > > rickman kibitzed: > > > You can use two write ports on block rams. =A0They can be hard to infer= , > > but they can always be instantiated. > > Your register files are write-only? You can't have two write ports to > a memory block if you need to read arbitrary locations as well. > > Unfortunately there isn't any one good solution, tough there are some > options. For example : > - Time multiplexing (there goes the benefit of superscalar), > - Banking (Complicated and performance depends on few conflicts), > - Inferred from logic (expensive, but sometimes the best option), and > - "Distributed": represent each location as the sum of parts (one > cycle extra write latency and uses a lot of memory blocks, eg. 2w4r =3D > 10 blocks). > > Tommy I think you are mistaken. The read and write must share an address, but you can do either a read or a write on either clock cycle on each port. If you need dual ported ram that can do both read and write simultaneously, you can run the RAM at *double speed* and in effect multiplex it. I doubt that the block ram in FPGAs will be the speed limiting factor even when running at a double speed clock. RickArticle: 141133
On 8 June, 11:13, Brane2 <bran...@avtomatika.com> wrote: > It has been a while since Xilinx started with "New Virtex and Spartan > is here!" but there is no concrete data about actual devices yet. > > New devices have some interesting features ( judging from PR > materials) but seem a bit behind Altera's newest devices at least in > PCIe connectivity front. All you will get with Spartan 5 wil be PCIe > x1... > > Are there non-Virtex cheap devices with decent PCIe x1 with Xilinx and > when will new devices be available ? this info is all classified still ISE 11.2 will add support for v-6/s-6 but it still not announced when the s-6 LXT devices will become available AnttiArticle: 141134
wallge <wallge@gmail.com> writes: > On Jun 6, 2:11 am, Mike Harrison <m...@whitewing.co.uk> wrote: >> >> wallge <wal...@gmail.com> wrote: >> >> >> < I am looking at doing an FPGA video processor board design for with an >> >> < analog VGA style component output. >> >> (snip) >> >> Take a look at the Chrontel CH7301A - it does analogue VGA and DVI output, and has a DDR input to >> save on pins. Seconded. Make sure you have a really good clock - using DVI-D, the monitors don't care too much about jitter as the clock is forwarded. Analogue is a whole different story though :) > > I have actually been considering the chrontel parts... the DDR input > is one thing that concerns me. For some applications I will have to > run my video at 1280x1024@60Hz (SXGA). This VESA clock speed for this > is 108MHz. My current system design will have the FPGA on a main > processor board and my VGA converter chip on a separate breakout IO > board. If I have to DDR-ize my SXGA outputs, we are now talking about > signals transitioning at 216MHz, which makes me worry about signal > integrity and timing issues. I am using a Cyclone III and am not sure > if I can meet this timing. I am also worried about these single ended > signals traversing the board to board connector between the FPGA board > and the breakout IO board... Anyone have an opinion on this? I'm doing 1024x768x60Hz with an S3ADSP (65MHz pixel clock, so, yes, quite a bit less than yours!). Looking at the signals on the scope I have bags of margin. I didn't length match my signals to any extreme degree (to within 25mm IIRC). I also put a DCM in to sweep the phase of the data wrt to the clock, and that validated my margin estimates. [Sorry, I can't provide actual numbers] > Also, do these DDR signals need to by at 2.5V standard, or will 3.3V > TTL/CMOS work just fine? Here, I'm doing it with 3.3V, but the 7301 has a separate IO supply pin that (according to the datasheet) will operate off 1.1 to 3.6V. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 141135
I was trying to download ISE 11.1 using their download manager, and managed to get to 50% when it came up with an error. So I left it while the next day and tried to start again from 50% but was still getting the error. I thought maybe their website was down but it cant be as I have been able to start a new download from the beginning. This seems crazy to me that their download manager is not working correctly and you end up losing all the data that you have already got. Why dont they just let you use your own download manger? JonArticle: 141136
I have generated a memory with coregen. It has a write port clocked from clka and a registered read port clocked from clkb. When I simulate it the written data appears 2 clk cycles after the address changes which is what I expect. However there is also a 100ps delay from the clk edge to when the data changes. So I basically have a delay of 2 clk cycles plus 100ps. Is this an error or have I missed something? Cheers JonArticle: 141137
On Jun 8, 3:17 am, "DAJ" <donia.j...@gmail.com> wrote: > why is it that refresh to refresh period in case of 1gbddr comes to the > order of 34 cycles and in case of 2gbDDR comes to the order of 52 cycles(as > per Micron Data sheet)where as logically the refresh to refresh period > should be less in case of bigger memory..can somebody clarify this for > me...???? > > Thanks in advance > > DAJ If I understand your question correctly, you are asking why the refresh rate of DRAM seems to depend on the size of the device? When DRAMs were much smaller, they worked with a fixed period to refresh the entire device. It became apparent early on that they couldn't maintain a fixed refresh period or the rate would become higher with each generation and become a larger and larger percentage of the available bandwidth. So with each new generation, they would double the size of the device, but increases the period of refreshing the entire device (normally by making the capacitors larger) to maintain a fixed refresh rate. I assume that in the 1 Gb case rather than change the geometry of each bit, they kept the design the same as the 512 Mb parts and just shrunk the cell size to allow twice as many bits with the same number of columns and rows. So to meet the refresh period spec, they had to require an increase in the refresh rate. I expect with the larger 2 Gb device, they went back to a 52 cycle refresh rate to maintain bandwidth. I don't know this specifically with these two parts, but based on what I do know, this sounds reasonable. RickArticle: 141138
On 8 Jun., 10:26, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On 8 June, 11:13, Brane2 <bran...@avtomatika.com> wrote: > > > It has been a while since Xilinx started with "New Virtex and Spartan > > is here!" but there is no concrete data about actual devices yet. > > Are there non-Virtex cheap devices with decent PCIe x1 with Xilinx and > > when will new devices be available ? > > this info is all classified still Well, I can't help with the timing fo the releases, but there are product briefs and product tables online: http://www.xilinx.com/products/v6s6.htm The HXT-parts are still missing, though. KoljaArticle: 141139
On Jun 7, 11:56=A0pm, Venkat <venkat.ja...@gmail.com> wrote: > Hi all, > > I am wondering if it is possible to have both the 06 and O5 Outputs of > the LUT registered with the Flip-flop within the Slice when I use the > LUT to implement two 5 Input Functions. > > My understanding is No but could not find a confirmation on the User > Guide. Can anyone clarify? > > Thanks in advance, > Venkat. I believe you can't do this in V5. I just attended a seminar on V6 and one of the new features they mentioned was adding a 2nd flip-flop to the slice so that both the outputs could be registered. John PArticle: 141140
On Jun 8, 5:10 am, "maxascent" <maxasc...@yahoo.co.uk> wrote: > I have generated a memory with coregen. It has a write port clocked from > clka and a registered read port clocked from clkb. When I simulate it the > written data appears 2 clk cycles after the address changes which is what I > expect. However there is also a 100ps delay from the clk edge to when the > data changes. So I basically have a delay of 2 clk cycles plus 100ps. Is > this an error or have I missed something? > > Cheers > > Jon The 100pS delay is from the model. It is there so that if you are debugging by using a waveform viewer it is obvious that the data comes AFTER the clock. ALArticle: 141141
But there isnt any 100ps delay on the actual device. JonArticle: 141142
On Mon, 08 Jun 2009 10:55:50 -0500 "maxascent" <maxascent@yahoo.co.uk> wrote: > But there isnt any 100ps delay on the actual device. > > Jon That depends on where in the chip you're routing the data to. Post-routing you could easily have 2-3 ns of delay. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 141143
But I dont understand why Xilinx have put this 100ps delay in the output that doesnt seems to relate to anything in the Virtex 5 datasheet. JonArticle: 141144
"maxascent" <maxascent@yahoo.co.uk> wrote in message news:dvidnUoYUYuBoLDXnZ2dnUVZ_vidnZ2d@giganews.com... > But I dont understand why Xilinx have put this 100ps delay in the output > that doesnt seems to relate to anything in the Virtex 5 datasheet. > It's common in models to put output delays on output to make waveforms more readable. Don't worry about it. It shouldn't affect functionality. If it does, you're probably doing something wrong!Article: 141145
On Jun 8, 9:32=A0am, "maxascent" <maxasc...@yahoo.co.uk> wrote: > But I dont understand why Xilinx have put this 100ps delay in the output > that doesnt seems to relate to anything in the Virtex 5 datasheet. Because there are too many "engineers" who don't understand the notion of a functional simulation with delta delays and these are the same engineers who litter their own code with "after 1 ns" and the like. It's babyfood for the lazy. -aArticle: 141146
On Jun 8, 1:25=A0am, rickman <gnu...@gmail.com> wrote: > On Jun 8, 3:19=A0am, Tommy Thorn <tommy.th...@gmail.com> wrote: > > > > > I wrote: > > > In fact, all the options for getting that > > > extra write port pretty much annul the performance benefits of runnin= g > > > multiple instructions. (And I haven't even started talking about the > > > bypass network and the hazard detection here). > > > rickman kibitzed: > > > > You can use two write ports on block rams. =A0They can be hard to inf= er, > > > but they can always be instantiated. > > > Your register files are write-only? You can't have two write ports to > > a memory block if you need to read arbitrary locations as well. > > > Unfortunately there isn't any one good solution, tough there are some > > options. For example : > > - Time multiplexing (there goes the benefit of superscalar), > > - Banking (Complicated and performance depends on few conflicts), > > - Inferred from logic (expensive, but sometimes the best option), and > > - "Distributed": represent each location as the sum of parts (one > > cycle extra write latency and uses a lot of memory blocks, eg. 2w4r =3D > > 10 blocks). > > > Tommy > > I think you are mistaken. LOL. You preceed to ... >=A0The read and write must share an address, ... confirm what I wrote. > but you can do either a read or a write on either clock cycle on each > port. =A0If you need dual ported ram that can do both read and write > simultaneously, you can run the RAM at *double speed* and in effect > multiplex it. The very list option I listed. >=A0I doubt that the block ram in FPGAs will be the speed > limiting factor even when running at a double speed clock. Doubt as much as you like. I've been there and got the T-shirt. TommyArticle: 141147
Andy Peters wrote:
> Because there are too many "engineers" who don't understand the notion
> of a functional simulation with delta delays and these are the same
> engineers who litter their own code with "after 1 ns" and the like.
... and some vendor models started life as verilog,
which has no clean delta delay.
If I write my own synthesis code,
I don't need the vendor model
of the secret netlist.
-- Mike Treseler
Article: 141148On Jun 8, 12:32=A0pm, "maxascent" <maxasc...@yahoo.co.uk> wrote: > But I dont understand why Xilinx have put this 100ps delay in the output > that doesnt seems to relate to anything in the Virtex 5 datasheet. > > Jon Very often I have found that Xilinx models have gated clocks or at least clock signals with buffering on them. Sometimes these lead to misbehavior of the simulation if there is no delay. An earlier version of the block RAM used to show read data on the same clock edge where the address was changed instead of one cycle later. I wouldn't spend too much time trying to second guess why they "fixed" the model by adding delay rather than simplifying the clock path. Just because Xilinx is a large company with a lot of resources doesn't mean that everyone who writes models for them is a great expert. Very often such large companies use summer co-op students and the like to do this sort of grunt-work. Just my 2 cents, GaborArticle: 141149
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