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Moti Litochevski <motilito@gmail.com> wrote in news:4498adf2-c6b8-4d8c-a54a- 946dc779e3c3@f16g2000vbf.googlegroups.com: > On Jun 10, 11:44 am, recoder <kurtulmeh...@gmail.com> wrote: >> Dear All, >> We have implemented a high speed qpsk demodulator in a FPGA >> demodulator board. >> Until now we fed the I and Q inputs from another board by wire. >> Now we are looking for an IF board that can take a 70 Mhz RF signal >> and output the I and Q signals to be fed to our FPGA board. >> Can anybody recommend one? >> Thanx in advance > > Have you looked at Sundance boards? > I did not try them yet but I found them when looking for the same > thing. > It will not be cheap but it's on the shelf (let's hope). > > Regards, > Moti You might take a look at our dspblo a9238 or a9248. These are I & Q boards that work with our dspblok 21369+fpga boards. Here is a link: http://www.danvillesignal.com/dspblok/dspblok-a9238-analog-devices-ad9238-hi- speed-adc-i/o-board.html (My newsreader won't let me have enough lines to remove the wrap) Al Clark Danville SignalArticle: 141201
hi all ,
i have successfully implemented the web server into my S3A board.
presently i am using DDR memory to store my web page and elf file
using XMD.
my application is like board can not be always connected to PC by
JTAG.
So my questions are :
1.is this every time essential, to store my webpage.mfs and exe.elf
into
DDR when i download bit stream into FPGA.(initially board is
switched
OFF so no file was in DDR RAM)
2. Is there any way so that i can include webpage.mfs and exe.elf
in
download.bit file itself.and then i will store this bit file in
platform flash.so every time when i switch on the board FPGA will
boot automatically.
3. OR i have to use external FLASH memory to store the webpage.mfs
and
exe.elf permanently.
I AM USING :
1.XP
2.XILINX EDK 10.1
3.XILINX S3A Starter Kit.(having S3A FPGA,external FLASH and DDR
memory )
Article: 141202On Jun 10, 7:55=A0pm, Pablo <pbantu...@gmail.com> wrote: > I receive this message when I build "Software Applications". > > I am not sure but I think that hardware is not right although I don't > receive any error message when I build the Bitstream. > > /cygdrive/c/Windows/Temp//ccDJflt9.s: Assembler messages: > /cygdrive/c/Windows/Temp//ccDJflt9.s:72: Error: register expected, but > saw 'rfsli' > /cygdrive/c/Windows/Temp//ccDJflt9.s:72: Warning: ignoring operands: > rfsli > make: *** [mb0_thread/executable.elf] Error 1 > Done! > > my best regards Seems like you are using rfsli when it should be rfsl0 (or rather rfsl<n> where n is the fsl channel. Can you show the code section where you using the fsl interface? G=F6ranArticle: 141203
On 11 jun, 05:50, OutputLogic <evgen...@gmail.com> wrote: > FPGA timing closure is a time-consuming task and sometimes a source of > heated debates between team members. > My question to this group is what is a safe margin in static timing > analysis in which a design will still work. > Specifically, if a critical net in Xilinx Virtex5 -2 chip running at > 250 MHz misses timing by 100ps is it still ok. > I understand that there are factors like temperature, voltages, > jitter, etc. to consider, and it's always better to meet timing. But > I'm interested in how much the timing can be violated if a design is > running under "normal" conditions in a lab. Just yesterday I had a design with a Virtex4 sx35-11 in the lab that just barely runs at 280MHz according to the ISE10 static timing analyzer (~ 10 ps slack). I was able to run it up to 345 MHz without much of a problem. So, based on my experience with this (and other setups in the past), missing timing by 100ps shouldn't give you any problems as long as it's a controlled lab setup, i.e. moderate die- temperatue, decent voltage, etc. If it does work unreliably, then my guess is there is something wrong with the design (underconstrained, unstable voltage, excessive jitter,...). BartArticle: 141204
On 10 jun, 22:20, "MM" <mb...@yahoo.com> wrote: > > And two boards at the same time with the same executable.elf??? > > It probably doesn't matter whether you are trying to load the same file or > not. But I guess you could probably do it by connecting your boards in a > single JTAG chain... > > /Mikhail Do you recommend me to put every TDI, TDO, TCK pin into the same Header?Article: 141205
On 11 jun, 08:13, Goran_Bilski <goran.bil...@xilinx.com> wrote: > On Jun 10, 7:55=A0pm, Pablo <pbantu...@gmail.com> wrote: > > > I receive this message when I build "Software Applications". > > > I am not sure but I think that hardware is not right although I don't > > receive any error message when I build the Bitstream. > > > /cygdrive/c/Windows/Temp//ccDJflt9.s: Assembler messages: > > /cygdrive/c/Windows/Temp//ccDJflt9.s:72: Error: register expected, but > > saw 'rfsli' > > /cygdrive/c/Windows/Temp//ccDJflt9.s:72: Warning: ignoring operands: > > rfsli > > make: *** [mb0_thread/executable.elf] Error 1 > > Done! > > > my best regards > > Seems like you are using rfsli when it should be rfsl0 (or rather > rfsl<n> where n is the fsl channel. > Can you show the code section where you using the fsl interface? > > G=F6ran This is my system.mhs section: BEGIN microblaze PARAMETER INSTANCE =3D microblaze_0 PARAMETER HW_VER =3D 7.10.d PARAMETER C_INSTANCE =3D microblaze_0 PARAMETER C_DEBUG_ENABLED =3D 1 PARAMETER C_FSL_LINKS =3D 4 BUS_INTERFACE DPLB =3D mb_plb_0 BUS_INTERFACE IPLB =3D mb_plb_0 BUS_INTERFACE DEBUG =3D debug_module_MBDEBUG_0 BUS_INTERFACE DLMB =3D dlmb_0 BUS_INTERFACE ILMB =3D ilmb_0 BUS_INTERFACE SFSL0 =3D fsl_v20_0 BUS_INTERFACE MFSL0 =3D fsl_v20_1 BUS_INTERFACE SFSL1 =3D fsl_v20_2 BUS_INTERFACE MFSL1 =3D fsl_v20_3 BUS_INTERFACE SFSL2 =3D fsl_v20_4 BUS_INTERFACE MFSL2 =3D fsl_v20_5 BUS_INTERFACE SFSL3 =3D fsl_v20_0_mb0 * Microblaze works as slave (ONLY) PORT MB_RESET =3D mb_reset PORT Interrupt =3D Interrupt END =20 Azq_reg is the custom peripheral connected by FSL Bus BEGIN azq_reg PARAMETER INSTANCE =3D azq_reg_0 PARAMETER HW_VER =3D 1.00.a PARAMETER Value =3D 0x00000000 BUS_INTERFACE MFSL =3D fsl_v20_0_mb0 END =20 The FSL Bus BEGIN fsl_v20 PARAMETER INSTANCE =3D fsl_v20_0_mb0 PARAMETER HW_VER =3D 2.11.a PARAMETER C_EXT_RESET_HIGH =3D 0 PORT FSL_Clk =3D sys_clk_s PORT SYS_Rst =3D net_gnd END And the Azq_Reg.vhd: ---------------------------------------------------------------------------= --- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity azq_reg is generic ( Value: in std_logic_vector(31 downto 0) :=3D "00000000000000000000000000000010" ); port ( -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add or delete. FSL_Clk : in std_logic; FSL_Rst : in std_logic; FSL_S_Clk : out std_logic; FSL_S_Read : out std_logic; FSL_S_Data : in std_logic_vector(0 to 31); FSL_S_Control : in std_logic; FSL_S_Exists : in std_logic; FSL_M_Clk : out std_logic; FSL_M_Write : out std_logic; FSL_M_Data : out std_logic_vector(0 to 31); FSL_M_Control : out std_logic; FSL_M_Full : in std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); attribute SIGIS : string; attribute SIGIS of FSL_Clk : signal is "Clk"; attribute SIGIS of FSL_S_Clk : signal is "Clk"; attribute SIGIS of FSL_M_Clk : signal is "Clk"; end azq_reg; architecture EXAMPLE of azq_reg is -- Total number of input data. constant NUMBER_OF_INPUT_WORDS : natural :=3D 8; -- Total number of output data constant NUMBER_OF_OUTPUT_WORDS : natural :=3D 8; type STATE_TYPE is (Idle, Read_Inputs, Write_Outputs); signal state : STATE_TYPE; -- Accumulator to hold sum of inputs read at any point in time signal sum : std_logic_vector(0 to 31); -- Counters to store the number inputs read & outputs written signal nr_of_reads : natural range 0 to NUMBER_OF_INPUT_WORDS - 1; signal nr_of_writes : natural range 0 to NUMBER_OF_OUTPUT_WORDS - 1; begin FSL_S_Read <=3D FSL_S_Exists when state =3D Read_Inputs else '0'; FSL_M_Write <=3D not FSL_M_Full when state =3D Write_Outputs else '1'; FSL_M_Data <=3D Value; *** I use this peripheral to identify the microblaze processor. ..... .....Article: 141206
>> Hi, >> >> I am new to this site but i found the topic very helpful for me. I just >> need to know if the DDR memory is the only memory that can store MPSoC >> systems (up to 8 Microblaze systems) on the ML403 board. Can we use the >> SRAM too? And how much would it hold (up to how many microblaze >> processors)? and in case I am using the FPGA's BRAMs as cache memories, >> would that affect how many microblaze that could be added? >> >> Thanks a lot, >> N > >No external memories are required by a MB since its elf and stack/heap >can be stored in local BRAM. On large fpgas you can probably squeeze >in at least a dozen MB. If the elf or stack/heap is so large that it >doesn't fit in BRAM, then you can also use external DDR2 or SRAM or >Flash. Using BRAM for other purposes simply reduces the amount >available for MB(s). > >The DDR2 uses the Xilinx multiport memory controller (MPMC described >in DS643) with max 8 ports per bank, while the SRAM (or Flash) uses >the Xilinx multi-channel external memory controller (XPS MCH EMC >described in DS575) with max 4 ports. On the Xilinx MLxxx boards there >is only 1 bank of DDR2, SRAM or Flash, while other boards may have >multiple banks. > >For higher throughput and higher energy efficiency, it makes sense to >move functionality from sw targets to hw targets. >/Per > Thanks for the quick feedback, and I am sorry but I am quite new to the MPSoC domain on the Xilinx boards. The thing is that I have to use 12 Microblaze processors on my FPGA (ML403 board). The code segment of all of them doesn't fit on the local BRAMs in the FPGA and that is why I am in need to use external memories to store this segment. Also, I wish to use the BRAMs as cache memories for these MBs (I and D cache). My main question is: can I fit 12 Microblaze processors on external memory (on DDR or SRAM)? Let us say I have one MPMC controller with 8 ports, can I add another controller with different start and end addresses than the previous and then I will have 16 ports? Thanks in advance NArticle: 141207
at least the tracert can not resolve the DNS any more hm, my last full snapshot from oc is done more than a year ago :( lets see maybe the trouble is just temporary one AnttiArticle: 141208
"Antti" <Antti.Lukats@googlemail.com> wrote in message news:1c80a70a-b0ac-44d2-80c0-52434f6caf33@x5g2000yqk.googlegroups.com... > at least the tracert can not resolve the DNS any more > > hm, my last full snapshot from oc is done more than a year ago :( > > lets see maybe the trouble is just temporary one > > Antti Seems to works fine for me. Your DNS might be cached locally. Pinging www.opencores.org [213.115.14.150] with 32 bytes of data: Reply from 213.115.14.150: bytes=32 time=71ms TTL=51 Reply from 213.115.14.150: bytes=32 time=61ms TTL=51 Reply from 213.115.14.150: bytes=32 time=61ms TTL=51 Reply from 213.115.14.150: bytes=32 time=67ms TTL=51 Hans www.ht-lab.comArticle: 141209
On Jun 11, 12:23=A0pm, "HT-Lab" <han...@ht-lab.com> wrote: > "Antti" <Antti.Luk...@googlemail.com> wrote in message > > news:1c80a70a-b0ac-44d2-80c0-52434f6caf33@x5g2000yqk.googlegroups.com... > > > at least the tracert can not resolve the DNS any more > > > hm, my last full snapshot from oc is done more than a year ago :( > > > lets see maybe the trouble is just temporary one > > > Antti > > Seems to works fine for me. Your DNS might be cached locally. > > Pingingwww.opencores.org[213.115.14.150] with 32 bytes of data: > > Reply from 213.115.14.150: bytes=3D32 time=3D71ms TTL=3D51 > Reply from 213.115.14.150: bytes=3D32 time=3D61ms TTL=3D51 > Reply from 213.115.14.150: bytes=3D32 time=3D61ms TTL=3D51 > Reply from 213.115.14.150: bytes=3D32 time=3D67ms TTL=3D51 > > Hanswww.ht-lab.com hi thanks eh i tried from 2 different PCs connected to 2 different ISP's and both had no DNS lookup so got me worried it works with numeric IP :) AnttiArticle: 141210
>On Jun 11, 12:23=A0pm, "HT-Lab" <han...@ht-lab.com> wrote: >> "Antti" <Antti.Luk...@googlemail.com> wrote in message >> >> news:1c80a70a-b0ac-44d2-80c0-52434f6caf33@x5g2000yqk.googlegroups.com... >> >> > at least the tracert can not resolve the DNS any more >> >> > hm, my last full snapshot from oc is done more than a year ago :( >> >> > lets see maybe the trouble is just temporary one >> >> > Antti >> >> Seems to works fine for me. Your DNS might be cached locally. >> >> Pingingwww.opencores.org[213.115.14.150] with 32 bytes of data: >> >> Reply from 213.115.14.150: bytes=3D32 time=3D71ms TTL=3D51 >> Reply from 213.115.14.150: bytes=3D32 time=3D61ms TTL=3D51 >> Reply from 213.115.14.150: bytes=3D32 time=3D61ms TTL=3D51 >> Reply from 213.115.14.150: bytes=3D32 time=3D67ms TTL=3D51 >> >> Hanswww.ht-lab.com > >hi thanks > >eh i tried from 2 different PCs connected to 2 different ISP's and >both had no DNS lookup so got me worried >it works with numeric IP :) > >Antti > I just tried it from this PC, and it fine from the domain-nume/URL - snazzy new-ish look, too!Article: 141211
http://www.opendns.com/Article: 141212
On Jun 11, 11:37=A0am, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On Jun 11, 12:23=A0pm, "HT-Lab" <han...@ht-lab.com> wrote: > > > > > "Antti" <Antti.Luk...@googlemail.com> wrote in message > > >news:1c80a70a-b0ac-44d2-80c0-52434f6caf33@x5g2000yqk.googlegroups.com... > > > > at least the tracert can not resolve the DNS any more > > > > hm, my last full snapshot from oc is done more than a year ago :( > > > > lets see maybe the trouble is just temporary one > > > > Antti > > > Seems to works fine for me. Your DNS might be cached locally. > > > Pingingwww.opencores.org[213.115.14.150] with 32 bytes of data: > > > Reply from 213.115.14.150: bytes=3D32 time=3D71ms TTL=3D51 > > Reply from 213.115.14.150: bytes=3D32 time=3D61ms TTL=3D51 > > Reply from 213.115.14.150: bytes=3D32 time=3D61ms TTL=3D51 > > Reply from 213.115.14.150: bytes=3D32 time=3D67ms TTL=3D51 > > > Hanswww.ht-lab.com > > hi thanks > > eh i tried from 2 different PCs connected to 2 different ISP's and > both had no DNS lookup so got me worried > it works with numeric IP :) > > Antti I had the same problem until I restarted my dns (I use my own dns - not the provider one) Maybe they experienced some dns problem and now the provider dns cached it... I think you should wait the cache expire... or ask the provider to restart their dns Regards SandroArticle: 141213
On Jun 11, 12:34=A0am, "jayantbala" <jayantb...@gmail.com> wrote: > hi all , > =A0 =A0 =A0 =A0 i have successfully implemented the web server into my S3= A board. > =A0 =A0 =A0 =A0 presently i am using DDR memory to store my web page and = elf file > using =A0XMD. > =A0 =A0 =A0 =A0 my application is like board can not be always connected = to PC by > JTAG. > =A0 =A0 =A0 =A0 So my questions are =A0: > > =A0 =A0 =A0 =A01.is this every time essential, to store my webpage.mfs an= d exe.elf > into > =A0 =A0 =A0 =A0DDR when i download bit stream into FPGA.(initially board = is > switched > =A0 =A0 =A0 =A0OFF so no file was in DDR RAM) > > =A0 =A0 =A0 =A02. Is there any way so that i can include webpage.mfs and = exe.elf > in > =A0 =A0 =A0 =A0 =A0download.bit file itself.and then i will store this bi= t file in > =A0 =A0 =A0 =A0 =A0platform flash.so every time when i switch on the boar= d FPGA will > > =A0 =A0 =A0 =A0 =A0boot automatically. > > =A0 =A0 =A0 =A03. OR i have to use external FLASH memory to store the web= page.mfs > and > =A0 =A0 =A0 =A0 =A0exe.elf permanently. > > =A0 =A0 =A0I AM USING : > =A0 =A0 =A01.XP > =A0 =A0 =A02.XILINX EDK 10.1 > =A0 =A0 =A03.XILINX S3A Starter Kit.(having S3A FPGA,external FLASH and D= DR > memory ) If your code doesn't fit in block RAM, you will need to store it somewhere. That somewhere is probably going to be an external flash device. You will need to make sure you have a bootloader somewhere that can start the system at power up. Typically, this is stored in BRAM, but if you set the system up properly, you may be able to boot from external flash. Also, unless you licensed the MAC core, it will time out after 8 hours or so. This restriction is lifted if the JTAG port is active. I'm not sure if you actually have to be debugging anything, but the pod does have to have a green light. There are workarounds for this - specifically driving the config pin with a user I/O signal to restart the FPGA. I did this on an ML403, and it worked fairly reliably - but you have to be able to tolerate some downtime. In my case, the application was very small - and entirely stored in BRAM - so the downtime was fairly small.Article: 141214
On Jun 11, 1:45=A0am, "naim32" <engineer_n...@yahoo.com> wrote: > >> Hi, > > >> I am new to this site but i found the topic very helpful for me. I > just > >> need to know if the DDR memory is the only memory that can store MPSoC > >> systems (up to 8 Microblaze systems) on the ML403 board. Can we use > the > >> SRAM too? And how much would it hold (up to how many microblaze > >> processors)? and in case I am using the FPGA's BRAMs as cache > memories, > >> would that affect how many microblaze that could be added? > > >> Thanks a lot, > >> N > > >No external memories are required by a MB since its elf and stack/heap > >can be stored in local BRAM. On large fpgas you can probably squeeze > >in at least a dozen MB. If the elf or stack/heap is so large that it > >doesn't fit in BRAM, then you can also use external DDR2 or SRAM or > >Flash. Using BRAM for other purposes simply reduces the amount > >available for MB(s). > > >The DDR2 uses the Xilinx multiport memory controller (MPMC described > >in DS643) with max 8 ports per bank, while the SRAM (or Flash) uses > >the Xilinx multi-channel external memory controller (XPS MCH EMC > >described in DS575) with max 4 ports. On the Xilinx MLxxx boards there > >is only 1 bank of DDR2, SRAM or Flash, while other boards may have > >multiple banks. > > >For higher throughput and higher energy efficiency, it makes sense to > >move functionality from sw targets to hw targets. > >/Per > > Thanks for the quick feedback, and I am sorry but I am quite new to the > MPSoC domain on the Xilinx boards. > > The thing is that I have to use 12 Microblaze processors on my FPGA (ML40= 3 > board). The code segment of all of them doesn't fit on the local BRAMs in > the FPGA and that is why I am in need to use external memories to store > this segment. Also, I wish to use the BRAMs as cache memories for these M= Bs > (I and D cache). My main question is: can I fit 12 Microblaze processors = on > external memory (on DDR or SRAM)? Let us say I have one MPMC controller > with 8 ports, can I add another controller with different start and end > addresses than the previous and then I will have 16 ports? > > Thanks in advance > N You can't chain MPMCs -- the SDRAM port is not compatible with the user port. You can potentially use 8x MB using a MPMC and 4x MB using MCHEMC, but I've never tried that. I'm also not sure that 12 MB fit on a ML403 (which is rather small). Why 12 MB? Moving functionality from sw to hw is normally recommended.Article: 141215
On Jun 10, 8:50=A0pm, OutputLogic <evgen...@gmail.com> wrote: > Specifically, if a critical net in Xilinx Virtex5 -2 chip running at > 250 MHz misses timing by 100ps is it still ok. Hello, Please keep in mind tbat the ISE timing analysis tool by default assumes worst case voltage ranges, worst case temperature, and worst case process for maximum delay analysis (and similarly for minimum delay analysis). So, if you have positive slack and a well-designed PCB, there should be no issues for any environment. Hence, I have no issues testing out a design with even a bit of negative slack to save time, since I don't keep my lab at 50C. How far you can go down this path is an intuition issue rather than an engineering issue. In particular, although I will try out designs with marginal negative slack for test, if there are any "weird issues", I won't spend even a moment trying to debug them and will instead make a design that meets timing. - NathanArticle: 141216
Hey all -- Just got an email from Xilinx marking discontinuations on the XC3S50 in the CP132 package. Their recommendation for anyone using them is the XC3S100E, rebuilding the FPGA, and respinning the PCB. Not to sound alarmist, but I hadn't quite gotten to the point of considering the Spartan 3s to be a "fossil" family yet. It seems early in the lifecycle to be discontinuing parts with no replacement and, while I don't have any designs around this part, it pricks up my ears with regard to the many XC3S200-TQ144 designs I've got going. Does anyone have any thoughts regarding Xilinx and part longevity? And, more to the point, thoughts regarding the other players on the field and whether they're any better/worse? Thanks, Rob -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 141217
Ron, Discontinuance of a package for a part is not unusual: if that package isn't selling, then it makes no sense to lose money on providing it. The silicon itself, lasts a very long time. Why? If there are lots of designs using the part, then it makes sense to sell it as long as it is used. It was not long after I joined Xilinx, 11 years ago now, that the XC2064 (the very first product) was discontinued. That is 14years of support and sales before a "last time buy" opportunity. The other part discontinued as the 4KXV family (220nm) a few years ago. The 4KXV was completely over-shadowed by Virtex, and then Virtex E, so it was discontinued. We still sell everything else: with the 3000 series FPGA probably the oldest, and still shipping products.Article: 141218
On Jun 11, 8:01=A0pm, austin <aus...@xilinx.com> wrote: > Ron, > > Discontinuance of a package for a part is not unusual: =A0if that > package isn't selling, then it makes no sense to lose money on > providing it. > > The silicon itself, lasts a very long time. =A0Why? =A0If there are lots > of designs using the part, then it makes sense to sell it as long as > it is used. > > It was not long after I joined Xilinx, 11 years ago now, that the > XC2064 (the very first product) was discontinued. =A0That is 14years of > support and sales before a "last time buy" opportunity. > > The other part discontinued as the 4KXV family (220nm) a few years > ago. =A0The 4KXV was completely over-shadowed by Virtex, and then Virtex > E, so it was discontinued. > > We still sell everything else: with the 3000 series FPGA probably the > oldest, and still shipping products. Well, S3 is the ONLY low cost family currently shipping, so it is the NEWEST shipping family (there are no s-6 yet) so obsoleting a package from the LATEST and ONLY low cost family shipping is alarming imagine altera would drop a package from Cyclone-III ? dropping S3 package is same thing.. so it does soung alarming to few people... AnttiArticle: 141219
It depends on the cost of failure. Is this a lab experiment, where failure is not going to seriously impact your repair/replacement costs (or lost customer confidence), or is this going into a shipping product, or might its failure (even in a lab) cause/allow expensive damage to something else? AndyArticle: 141220
On Thu, 11 Jun 2009 10:01:54 -0700 (PDT), austin <austin@xilinx.com> wrote: >Ron, > >Discontinuance of a package for a part is not unusual: if that >package isn't selling, then it makes no sense to lose money on >providing it. I was told by a disti that Xilinx basically package devices to order from stock die, so how much cost is there in continuing to supply even relatively low volumes? Or are there some variants that use different die for different packages?Article: 141221
On Jun 10, 9:44=A0am, recoder <kurtulmeh...@gmail.com> wrote: > Dear All, > =A0We have implemented a high speed qpsk demodulator in a FPGA > demodulator board. > Until now we fed the I and Q inputs from another board by wire. > Now we are looking for an IF board that can take a 70 Mhz RF signal > and output the I and Q signals to be fed to our FPGA board. > Can anybody recommend one? > Thanx in advance Have a look at the following hardware that would fit your specs: - DAQ I/Q data acquisition mezzanine card : http://www.sundance.com/web/files/productpage.asp?STRFilter=3DSMT350 - FPGA processing board : http://www.sundance.com/web/files/productpage.asp= ?STRFilter=3DSMT900 Note: Other form factors are available depending on your need. Thank you.Article: 141222
Hi All, I am trying to install ISE webpack 10.1 webinstall on my machine. I have Vista Business 64 bit OS. I dowloaded and saved the file on my drive and execute the setup file. I entered the Product ID but the installation program is only showing the ISE programming tool option active not the ISE Design tool active at all. Can anyone tells me what is the problem, Regards, JohnArticle: 141223
> >You can't chain MPMCs -- the SDRAM port is not compatible with the >user port. You can potentially use 8x MB using a MPMC and 4x MB using >MCHEMC, but I've never tried that. I'm also not sure that 12 MB fit on >a ML403 (which is rather small). > >Why 12 MB? Moving functionality from sw to hw is normally recommended. > I have to migrate a system into my board and compare them. If 12 can not fit, its okay. I have one more question regarding the DDR, I can add up to 8x MBs on the DDR each including I and D cache? I mean, if I enabled the I and D cache for my MBs, still I can fit 8 on the DDR? Thanks NArticle: 141224
On Jun 12, 6:01=A0am, Mike Harrison <m...@whitewing.co.uk> wrote: > On Thu, 11 Jun 2009 10:01:54 -0700 (PDT), austin <aus...@xilinx.com> wrot= e: > >Ron, > > >Discontinuance of a package for a part is not unusual: =A0if that > >package isn't selling, then it makes no sense to lose money on > >providing it. > > I was told by a disti that Xilinx basically package devices to order from= stock die, so how much > cost is there in continuing to supply even relatively low volumes? > Or are there some variants that use different die for different packages? That's true, but hidden in these discontinuations is often some other 'trigger' as well. There may be a issue with the package, or that package and one foundry die combination, and then the question becomes is the (re) engineering justified ? FPGAs also rather make a rod for their own backs, with so many package variations. I have seen semi companies define 'Preferred families', so that lower volume users can be steered to similar parts, and that simple step helps avoid obsolesce scares. Perhaps FPGA vendors could learn something here ? -jg
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