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On Thu, 04 Jun 2009 07:42:52 -0500 "PeterUK" <mastermaster01@hotmail.com> wrote: > Hi everyone, > I cannot simulate a simple AND Gate > > the original project: > I have downloaded the AND gate VHDL to a CPLD and it works file > without adding extra bits to simulate. > You create the ucf file and download to the CPLD and then real time > I've tested the out put and it works fine > > I am getting to the AND gate project becuase I am having problem > simulating bigger VHDL code. trying to understand the basic. > > When I simulate in ISim from 11.1 suite, I went step by step and I > figured out the simulation only run through the code outputC <= > inputA and inputB; only once. > > So I added a SEQ and simulater again and this time it does do back to > the VHDL file and run outputC <= inputA and inputB; every time the > clk rising > > the problem I have now is I cannot simulate a simple AND Gate in Isim > look at the tb file I have create when inputA is like the clock, > inputB is high always, but outputC is dead > > [codesnip] > Yes, the problem is your test is silly. What you coded is an AND gate feeding the D input of a flip-flop. Nothing wrong there, but then you decided that one of the AND inputs should _also_ be the flip-flop clock, and proceeded to wildly violate the setup timing of the flop. For a slightly more useful sim, try ripping all references to inputA out of your clock process, and just using as a combinational statement: inputA <= not inputA when rising_edge(clk); That will toggle inputA every clock cycle, leaving it nice and stable when your rising clock edge hits your flop, and give you a toggling output. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 141076
On May 13, 5:29=A0pm, DH <dh1...@gmail.com> wrote: > Hi, > > I'm trying to find an open source processor as a basis for a research, > preferably it is in VHDL and implements a 5-stage RISC pipeline with > bypassing (exceptions are not a concern), of course if you know of any > processor with a clean 5-stage pipeline with bypassing, please let me > know. It would be awesome if it implements the MIPS ISA. > > I've tried the open cores website, and have looked at 2 MIPS ISA > implementations: Plasma and miniMIPS. > Problem is Plasma does not deal with bypassing and is not a 5-stage > pipeline, and miniMIPS is rather weird, it process instructions every > other cycle, so it would process, then it would pause everything on > the next cycle. > > So I'm wondering maybe there would be someone out there on the > internets that know about this, please help me out :) Thanks! > > Regards, > David. Two more: OpenSparc : http://www.opensparc.net/ Java processor : http://www.jopdesign.com/ I haven't tried them yet. -outputlogic -- visit http://outputlogic.com : tools that improve productivity --Article: 141077
"Bond" <prashant.gyawali@gmail.com> wrote in message news:9c207959-16c6-4d93-b8bb-597d70db8120@r34g2000vba.googlegroups.com... On Jun 3, 6:22 pm, whygee <why...@yg.yg> wrote: > > Bond wrote: > > I have to use the > > formula A=(t1/t2-50)/12.5. can a hardware module process this kind of > > formula or it should be left for microblaze. > > Now, the "-50" term is unclear. actully the term 't1/t2' is duty cycle and we subtract 50 from the value of the duty cycle. so it is a constant. ============== It's probably duty cycle expressed as a percentage. "-50" normalizes it to 50% duty cycle. "/12.5" says to take 1/8 of that value, and express the result as a ratio rather than a percentage. You're all the way home without complex calculations if you can have duty ratio supplied as a N/256 fraction (or some other power of 2 fraction) rather than a percentage, and can accept the result similarly expressed. As homework problems go, this one is pretty cheesy, and all who helped are guilty of depriving you of your education. Consider the above a willful and spiteful tax on your future earning potential.Article: 141078
Marc Kelly wrote:
> I have an interesting idea/wish and wonder if anyone has had the same
> and found a way to solve it.
>
> I often work away from the physical hardware I am playing with and more
> recently I've been having a pain trying to find the best way to do
> debugging.
...
> Ideas are welcome...
I use simulation.
-- Mike Treseler
Article: 141079On Jun 4, 12:26=A0am, David <dh1...@gmail.com> wrote: > On May 21, 6:06=A0am, Tommy Thorn <tommy.th...@gmail.com> wrote: > > > > > On May 18, 5:06=A0pm, DH <dh1...@gmail.com> wrote: > > > > Hi, thanks to everyone that replied to this post! I really appreciate > > > it. > > > > To Antti: Thanks, the YARI processor looks like a good processor. > > > Why thank you :-) > > > > Update: After some discussion at school, I'm going > > > to use the CoWare processor designer at school to make my processor > > > now, it provides a reference 5 stage pipelined RISC core with > > > bypassing done already, it's not MIPS, but there's compiler/assembler= / > > > linker available. The best thing about this tool (though may be hard > > > to do, we'll see) is that you can use it to generate the tool chain > > > along with the processor RTL code. I will fall back to good old VHDL > > > if this tool doesn't deliver, thanks to everyone that replied to this > > > post! > > > Good luck with that. If you change your mind and want to give YARI a > > spin, I can help you. > > > It might be useful to know how your core will be used. Fx. will it be > > backed up with external memory or used as an embedded processor using > > only the FPGA provided memory blocks? Which parts of the processor are > > you planning on experimenting with? > > > Cheers, > > Tommy > > Hi Tommy, > =A0 sorry for the late response, thanks for the offer :) > my experimentation is going to use FPGA's internal RAM, and with > Altera DE2 being my dev board, I have to deal with the synchronous RAM > issue some designs I found to have (they use async ram). > I'm experimenting with splitting the RISC pipeline into two pipelined > parts, with each responsible for different instructions from the > original RISC's instruction set. So for example if original ISA have 4 > instructions A B C D, A and B are on the first pipeline, C and D are > on the second pipeline. This is why I need to look for a processor > with a 5 stage pipeline. > I actually have a 5 stage pipelined processor and have modified it to > work with my supplemental pipeline, now I need to consider the > compilation issues... a rather large task IMHO... Not that it is important for me to understand, but I don't follow what you are trying to do. Why is a 5 stage pipeline required to split your processor into two parallel pipelines? That is what you are doing, right? RickArticle: 141080
Mike Treseler wrote: > Marc Kelly wrote: > >> I have an interesting idea/wish and wonder if anyone has had the same >> and found a way to solve it. >> >> I often work away from the physical hardware I am playing with and more >> recently I've been having a pain trying to find the best way to do >> debugging. > ... >> Ideas are welcome... > > I use simulation. > -- Mike Treseler The full board simulation is fine for the things I can think of, just its just pretty hard to connect the modelsim to a real 1Gig ethenet stream and process real data at line speed looking for the 1 in million packet that is causing problems... the hardware can do it a lot faster but it would be nice if I didn't have to sit with it all day waiting for it to fall over. -- /\/\arc Kelly ..Just your average physicist trying to get by in a world full of normal people...Article: 141081
MikeWhy wrote: > As homework problems go, this one is pretty cheesy, and all who helped > are guilty of depriving you of your education. Consider the above a > willful and spiteful tax on your future earning potential. Sorry mike, I couldn't resist... Maybe I did too much DSP, or too little lately... old cravings resurface, you know... yg -- http://ygdes.com / http://yasep.orgArticle: 141082
On Jun 4, 3:30=A0pm, Marc Kelly <phmpk@reverse_this_gro.sndnyd.ranehca> wrote: > Mike Treseler wrote: > > Marc Kelly wrote: > > >> I have an interesting idea/wish and wonder if anyone has had the same > >> and found a way to solve it. > > >> I often work away from the physical hardware I am playing with and mor= e > >> recently I've been having a pain trying to find the best way to do > >> debugging. > > ... > >> Ideas are welcome... > > > I use simulation. > > =A0 =A0 =A0 =A0-- Mike Treseler > > The full board simulation is fine for the things I can think of, just > its just pretty hard to connect the modelsim to a real 1Gig ethenet > stream and process real data at line speed looking for the 1 in million > =A0packet that is causing problems... the hardware can do it a lot faster > but it would be nice if I didn't have to sit with it all day waiting for > it to fall over. > > -- > /\/\arc Kelly > ..Just your average physicist trying to get by in a world full of normal > people... Any chance you could move all of the development tools into the lab so you only need to run the PC remotely, and not transfer the files? Regards, GaborArticle: 141083
Hi All I am implementing the I2C Slave and i am using two data lines for sda input and sda output. MY question is that shall I expect from I2C bus to give me Z as input in place of 1 Shall I drive output 1 as Z to the sda_out Secondly We cannot synthesize Z as an input but can drive the output as Z any reason I have used an interal sda signal and sampled the SDA_input as SDA_internal<= '1' when SDA_input = 'Z' else '0' ; it is stucking the output /input to gnd and vcc in synthesis Pls specify Thanks VipulArticle: 141084
gabor wrote: > Any chance you could move all of the development tools into the > lab so you only need to run the PC remotely, and not transfer > the files? I was just trying to find a away to keep my development on my laptop, where everything is nicely installed. I will probably revert to installing a full development suite onto the desktop in the lab and using rsync to keep it up to date, unless my experiments with USB over IP tomorrow work out. It just struck me that it would be something other people had come across needing to do. If i find a good solution, I shall let people know.. -- /\/\arc Kelly ..Just your average physicist trying to get by in a world full of normal people...Article: 141085
"whygee" <whygee@yg.yg> wrote in message news:4a282a52$0$294$7a628cd7@news.club-internet.fr... > MikeWhy wrote: >> As homework problems go, this one is pretty cheesy, and all who helped >> are guilty of depriving you of your education. Consider the above a >> willful and spiteful tax on your future earning potential. > Sorry mike, I couldn't resist... > Maybe I did too much DSP, or too little lately... > old cravings resurface, you know... > yg Nah. It's great that that you took the time to help. I wrote poorly. I meant he was cheating himself out of an education by asking for *too* much help.Article: 141086
On Jun 4, 5:19=A0pm, VIPS <thevipulsi...@gmail.com> wrote: > Hi All > > I am implementing the I2C Slave and i am using two data lines for sda > input and sda output. > > MY question is that shall I expect from I2C bus to give =A0me Z as input > in place of 1 > No. That would be bad. A real I2C bus has a pullup resistor to provide a weak 1 when not driven. > Shall I drive output 1 as Z to the sda_out > Yes, this is essentially open-drain. > Secondly We cannot synthesize Z as an input but can drive the output > as Z any reason > As I said you should not be getting Z inputs. Z outputs are used to turn off your driver to emulate open-drain using a tristate driver. > I have used an interal sda =A0signal and sampled the SDA_input as > > SDA_internal<=3D '1' when SDA_input =3D 'Z' else '0' ; it is stucking the > output /input to gnd and vcc in synthesis > Again, this is wrong. SDA will be 1 when it isn't 0 as far as your device is concerned. The thing you really need to know is how long it takes to get there since there is no active high drive. When I designed my I2C slave I sampled the SDA and SCL signals using a higher-speed clock and then added a 5-stage deglitch / debounce to deal with the slow rise times. You can create a circuit without a high-speed clock, but if you use the SCL and SDA lines asynchronously (e.g. look for edges on them) you need to implement an input with hysteresis as specified in the I2C specification. > Pls specify > > Thanks > > VipulArticle: 141087
i have been asked to do a project in Xilinx virtex-5 wherein the requirement is to have a clock of very high frequency of the order of 800 Mhz.Can somebody help me with the generation of this and the possible routing strtegies to be used Thanks & Regards, DAJArticle: 141088
On Jun 4, 1:57=A0am, Marc Kelly <phmpk@reverse_this_gro.sndnyd.ranehca> wrote: > Hi, > > I have an interesting idea/wish and wonder if anyone has had the same > and found a way to solve it. > > I often work away from the physical hardware I am playing with and more > recently I've been having a pain trying to find the best way to do > debugging. > > I have a Linux machine at the lab, with usb and parallel jtag pods on > it, hooked up to the hardware. For downloading bit streams I usually scp > them to that machine, and then using VNC or ssh I fire up impact and use > that machine to flash the fpgas. > > Now, I also use Identify when things are not quite working as I expect, > and this is a pain to use like that, as it requires the whole design to > be copied over to the machine, and that take way to long over DSL. > > I know Impact can run as a server, and I have used that pretty often to > remote flash things. I also notice from digging into the Identify > directory ( identify/CseJtag/bin/lin) that it seems to use a core set of > Impact libraries... and I am sure you can guess my thinking here.. Is it > possible to get Identify to also use the remote Impact?? Or would that > require way to much forward thinking by the Tool makers... > > The second solution I thought of was "USB over IP" there are drivers for > this in latest linux, but they seem to fall over with the Xilinx POD, it > gets reset often, falls off the bus and then the tools loose connection.. > > Ideas are welcome... > > -- > /\/\arc Kelly > ..Just your average physicist trying to get by in a world full of normal > people... "IP over USB" is doable (there are USB network adapters), but "USB over IP" is hard to implement (don't want to get into details why). There are JTAG debuggers with the Ethernet interface, and I used to work with one to debug Linux apps on Freescale processors. It'd be nice if Xilinx adds such a pod to their existing ones with USB and Parallel interfaces. - evgeni -- visit http://outputlogic.com : tools that improve productivity --Article: 141089
On Jun 4, 8:20=A0am, LittleAlex <alex.lo...@email.com> wrote: > On Jun 3, 11:11=A0am, "MM" <mb...@yahoo.com> wrote: > > > "Allan Herriman" <allanherri...@hotmail.com> wrote in message > > >news:004237cd$0$9747$c3e8da3@news.astraweb.com... > > > > The Xilinx license is more flexible though - you can get a node locke= d > > > license and run multiple concurrent instances of the software on that > > > machine. > > > Do you know if the same can be done with a floating license, i.e. runni= ng > > multiple instances on a single machine with a single license? > > > /Mikhail > > The FlexLM floating license server checks the user count in the > license file. =A0Once "user count" licenses have been checked out, it > will not allow another check out to ANY machine. > > AL I did figure out what was going wrong: our network security was blocking the remote installation of the download manager. My work- around was to download at home and bring it in by sneaker-net. After installing 11.1 I got another shock: projects are now not backwards compatible with older versions of ISE. The project is converted to the new format and gets a .xise extension. This will significantly complicate collaboration as all users will need 11.1!Article: 141090
On Jun 4, 3:12=A0pm, "DAJ" <donia.j...@gmail.com> wrote: > i have been asked to do a project in Xilinx virtex-5 wherein the > requirement is to have a clock of very high frequency of the order of 800 > Mhz.Can somebody help me with the generation of this and the possible > routing strtegies to be used > > Thanks & Regards, > DAJ I did a quick check and the max DCM frequency is 550 MHz (for now), so you won't be able to do that internally.Article: 141091
>After installing 11.1 I got another shock: projects are now not >backwards compatible with older versions of ISE. The project is >converted to the new format and gets a .xise extension. This will >significantly complicate collaboration as all users will need 11.1! Xilinx projects have never been backward compatible as far as I can remember! /MikhailArticle: 141092
On Jun 3, 9:26=A0pm, David <dh1...@gmail.com> wrote: > On May 21, 6:06=A0am, Tommy Thorn <tommy.th...@gmail.com> wrote: > > > > > On May 18, 5:06=A0pm, DH <dh1...@gmail.com> wrote: > > > > Hi, thanks to everyone that replied to this post! I really appreciate > > > it. > > > > To Antti: Thanks, the YARI processor looks like a good processor. > > > Why thank you :-) > > > > Update: After some discussion at school, I'm going > > > to use the CoWare processor designer at school to make my processor > > > now, it provides a reference 5 stage pipelined RISC core with > > > bypassing done already, it's not MIPS, but there's compiler/assembler= / > > > linker available. The best thing about this tool (though may be hard > > > to do, we'll see) is that you can use it to generate the tool chain > > > along with the processor RTL code. I will fall back to good old VHDL > > > if this tool doesn't deliver, thanks to everyone that replied to this > > > post! > > > Good luck with that. If you change your mind and want to give YARI a > > spin, I can help you. > > > It might be useful to know how your core will be used. Fx. will it be > > backed up with external memory or used as an embedded processor using > > only the FPGA provided memory blocks? Which parts of the processor are > > you planning on experimenting with? > > > Cheers, > > Tommy > > Hi Tommy, > =A0 sorry for the late response, thanks for the offer :) > my experimentation is going to use FPGA's internal RAM, and with > Altera DE2 being my dev board, I have to deal with the synchronous RAM > issue some designs I found to have (they use async ram). I'm sorry but I could completely parse that statement. The DE2 is a Terasic board and it uses async SRAM whereas DE2-70 uses synchronous SRAM. Neither is hard to use IMO, and YARI comes with support for both. > I'm experimenting with splitting the RISC pipeline into two pipelined > parts, with each responsible for different instructions from the > original RISC's instruction set. So for example if original ISA have 4 > instructions A B C D, A and B are on the first pipeline, C and D are > on the second pipeline. This is why I need to look for a processor > with a 5 stage pipeline. I assume you are trying to make it superscalar, that is, issue more than one instruction each cycle? Otherwise there isn't much point to multiple parallel pipelines. IMO, the most challenging part about that this on an FPGA is that you cannot easily get the multiple write ports to the register file which you need to be able to retire multiple instructions per cycle. In fact, all the options for getting that extra write port pretty much annul the performance benefits of running multiple instructions. (And I haven't even started talking about the bypass network and the hazard detection here). Pretty much your best bet is a 2-VLIW with a compiler compiler controlled banked register file, but writing an industrial strength compiler backend for that is not for the faint of the heart. Of course, if it was easy, everybody would be doing it and what's the fun in that? :-) Good luck, Tommy > I actually have a 5 stage pipelined processor and have modified it to > work with my supplemental pipeline, now I need to consider the > compilation issues... a rather large task IMHO... > > Regards, > David.Article: 141093
On Jun 5, 1:54=A0am, soar2mor...@yahoo.com wrote: > On Jun 4, 3:12=A0pm, "DAJ" <donia.j...@gmail.com> wrote: > > > i have been asked to do a project in Xilinx virtex-5 wherein the > > requirement is to have a clock of very high frequency of the order of 8= 00 > > Mhz.Can somebody help me with the generation of this and the possible > > routing strtegies to be used > > > Thanks & Regards, > > DAJ > > I did a quick check and the max DCM frequency is 550 MHz (for now), so > you won't be able to do that internally. Use a PLL, for which the frequency ranges are 400 - 1200Mhz if I'm not mistaken. To get a design routed and meeting timing at that speed is another challenge. Good luck.Article: 141094
On Jun 4, 2:31=A0pm, j...@beniston.com wrote: > On 4 June, 12:29, Jaco Naude <naude.j...@gmail.com> wrote: > > > Hi > > > We've run into a problem where we get all zeros out of our filter > > (simple low-pass filter inside an IF sampler) in hardware. RDY behaves > > as expected, thus it seems like the coefficients (mif) file is not > > loaded during implementation or something else causes the coefficients > > to be all zeros in hardware. > > > In simulation the design works as expected. > > > Any ideas would be much appreciated? > > Jaco > > Have you tried a post P&R simulation? > > Are you sure it's the coefficients and not the input that is the > problem? > > Jon Thanks for the reply Jon. - We have not done a post P&R simulation yet since we are really pushed for time. But that's definitely an option. - We are sure the problem is not related to the inputs, as we have a logic analyzer pod connected to the input as well as the output of the filter. Thanks again, JacoArticle: 141095
Marc Kelly <phmpk@reverse_this_gro.sndnyd.ranehca> writes: > I have an interesting idea/wish and wonder if anyone has had the same > and found a way to solve it. It's been a little while since I've been using impact, but with Altera it's pretty easy to set up a remote Linux jtagserver (I've dug out a machine of the recycling can for this purpose) where you can run the fpga programmer as well as run signaltap and the NIOS debugger. I have ssh/kermit running on the machine so I can log in and run kermit to control the serial ports on the DUT-board. > The second solution I thought of was "USB over IP" there are drivers for > this in latest linux, but they seem to fall over with the Xilinx POD, it > gets reset often, falls off the bus and then the tools loose connection.. I've made my own programmer where I can upload fpga images over ethernet. No driver is required, you simply use tftp. However, I can only program FPGA's and other devices (like flash, microcontrollers etc) this way since I've not yet found any documentation on how to interface to signaltap, chipscope, or identify. I guess it should be possible to interface to the NIOS and Microblaze debuggers since they are wrapped around gdb. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 141096
"DAJ" <donia.jose@gmail.com> wrote in message news:4rCdnZ3pd8Eg27XXnZ2dnUVZ_o6dnZ2d@giganews.com... >i have been asked to do a project in Xilinx virtex-5 wherein the > requirement is to have a clock of very high frequency of the order of 800 > Mhz.Can somebody help me with the generation of this and the possible > routing strtegies to be used > > > > Thanks & Regards, > DAJ > > Run it internally at the order of 400MHz. Use the DDR FFs to get data in and out at the order of 800Mbits/pin. e.g. XAPP265 HTH., Syms.Article: 141097
Marc Kelly wrote: > gabor wrote: > >> Any chance you could move all of the development tools into the >> lab so you only need to run the PC remotely, and not transfer >> the files? > > I was just trying to find a away to keep my development on my laptop, > where everything is nicely installed. I will probably revert to > installing a full development suite onto the desktop in the lab and > using rsync to keep it up to date, unless my experiments with USB over > IP tomorrow work out. > > It just struck me that it would be something other people had come > across needing to do. If i find a good solution, I shall let people know.. > I evaluated various USB solutions recently. The one that seemed most reliable was USB Redirector (from www.incentivespro.com). We use that on our courses now when people program boards attached to their physical PC, but use tools installed on a virtualized PC. The USB is forwarded from the Virtual PC to the real PC. As other people have mentioned, the Xilinx Cableserver and the Altera Remote JTAG server also seem to work - though I've only tried these in the Linux -> PC direction, i.e. running the server on a PC which had the hardware attached, with the tools installed on Linux. There are problems with the Xilinx CableServer talking Linux -> PC in version 10.1.02 which are partially fixed in 10.1.03 and fully fixed in ISE 11. regards Alan -- Alan Fitch Senior Consultant Doulos – Developing Design Know-how VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24 1AW, UK Tel: + 44 (0)1425 471223 Email: alan.fitch@doulos.com Fax: +44 (0)1425 471573 http://www.doulos.com ------------------------------------------------------------------------ This message may contain personal views which are not the views of Doulos, unless specifically stated.Article: 141098
On Jun 5, 8:48=A0am, Jaco Naude <naude.j...@gmail.com> wrote: > On Jun 4, 2:31=A0pm, j...@beniston.com wrote: > > > > > > > > > On 4 June, 12:29, Jaco Naude <naude.j...@gmail.com> wrote: > > > > Hi > > > > We've run into a problem where we get all zeros out of our filter > > > (simple low-pass filter inside an IF sampler) in hardware. RDY behave= s > > > as expected, thus it seems like the coefficients (mif) file is not > > > loaded during implementation or something else causes the coefficient= s > > > to be all zeros in hardware. > > > > In simulation the design works as expected. > > > > Any ideas would be much appreciated? > > > Jaco > > > Have you tried a post P&R simulation? > > > Are you sure it's the coefficients and not the input that is the > > problem? > > > Jon > > Thanks for the reply Jon. > > - We have not done a post P&R simulation yet since we are really > pushed for time. But that's definitely an option. > > - We are sure the problem is not related to the inputs, as we have a > logic analyzer pod connected to the input as well as the output of the > filter. > > Thanks again, > Jaco Are you using symetrical filter? If yes then you might have problems with coefficients. Use symmetrical for a first test. Cheers, AlesArticle: 141099
Symplicity appears to be assigining the embeded flash core of the analog system to a flash block rather than a spare page of the flash memory. The result is the embeded flash core of the analog system ties up an entire 2Meg bit flash block. Has anyone seen this issue and know a solution. Has anyone been able to implement 4Meg-bit of flash memory and the analog functions in a AFS600?
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