Messages from 139675

Article: 139675
Subject: How to insert Chipscope blocks directly in Xilinx Project Navigator
From: techpaperx <mp.techpaper@googlemail.com>
Date: Wed, 8 Apr 2009 16:15:24 -0700 (PDT)
Links: << >> << T >> << A >>

Dear all,

1. I want to insert Chipscope blocks (ICON, ILA) into my design in
Xilinx project navigator.
2. I generated blocks from Chipscope Core Generator (.edn, .vhd, .ncf)
but I do not know how I can assign .edn file into project navigator.
3. I always used Mentor Graphics HDL Designer for design entry and it
was very easy in that. I also know how to use signal tap (for Altera)
but never used Chipscope directly with Project Navigator.

request for the some suggestions.
Thanks
Mukesh

Article: 139676
Subject: Re: ANN: Antti-Brain March issue released
From: Manny <mloulah@hotmail.com>
Date: Wed, 8 Apr 2009 16:18:05 -0700 (PDT)
Links: << >> << T >> << A >>

On Apr 8, 11:01=A0pm, Jon Elson <jmel...@wustl.edu> wrote:
> Antti wrote:
> > Hi
>
> >http://groups.google.com/group/antti-brain/files?hl=3Den
>
> > with a delay this month again :( the time is flying only faster..
> > but there are some new FPGA board photos included..
>
> > Antti
>
> Google now says all your pages are invalid! =A0Umm, might be a browser
> compatibility problem, I'm using Firefox on a Linux platform.
>
> Jon

Same here; Vista Firefox.

-Momo

Article: 139677
Subject: Re: @@@@@@@@About DSP48 used for 24bit * 18bit @@@@@@@@
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Thu, 09 Apr 2009 00:55:10 +0100
Links: << >> << T >> << A >>

On Wed, 8 Apr 2009 08:09:39 -0700 (PDT), bluesea.xjtu@gmail.com wrote:

>I want to use DSP48A for a Semi-Parallel FIR filter. Since DSP48A is
>18bit*18bit;so i need 2 slice of DSP48A for a multiplier. but how can
>i utilize the 2 slice DSP48A's internal 48bit post Adder for the
>Accumulation. or maybe it can only need the 3rd DSP48A for the
>Accumulation?

In which FPGA family?

- Brian

Article: 139678
Subject: Re: Two stage synchroniser,how does it work?
From: -jg <Jim.Granville@gmail.com>
Date: Wed, 8 Apr 2009 18:42:31 -0700 (PDT)
Links: << >> << T >> << A >>

On Apr 8, 8:40=A0pm, "kadhiem_ayob" <kadhiem_a...@yahoo.co.uk> wrote:
> If the flip output is irrelevant(being 0 or 1 or undefined) then we got
> problem with data value integrity rigt from the start of chain.
> We need to separate between the issue of metasatibilty probability and
> data value crossing.
> surely the probability of metastability goes down after every stage but
> data value goes wrong through anyway from the start irrespective of
> probability issue. This is what puzzles me.
>
> kadhiem

It's a probability game.
 You certainly can extend the settling time Clk-Q of
a FF, by very precise/bad change of D input.
 That aperture is very small.

 The Dual FF strives to reduce the multiplied odds,
of a Clk-Q change out of the second FF.

You cannot really call the data value 'wrong' as it needs to change to
trigger.
You _can_ call it delayed, but you expect delays anyway.

Most metastable models are very simple: A couple of datapoints, and
a straight line on log-log assumed through them.

-jg

Article: 139679
Subject: Re: ANN: Antti-Brain March issue released
From: -jg <Jim.Granville@gmail.com>
Date: Wed, 8 Apr 2009 18:46:02 -0700 (PDT)
Links: << >> << T >> << A >>

On Apr 9, 11:18=A0am, Manny <mlou...@hotmail.com> wrote:
> Same here; Vista Firefox.
>
> -Momo

Firefox/Win2000 here, shows 8 PDF's, one of which

AnttiBrain_Issue8_MAR2009.pdf  Antti.Lukats@googlemail.com 	1.6 MB
Apr 7

that pdf opens with a caption "Hello, from Amontec STM32!"
- seems OK to me ?

-jg

Article: 139680
Subject: Re: Chipscope debug in EDK
From: Ehsan <ehsan.hosseini@gmail.com>
Date: Wed, 8 Apr 2009 19:55:36 -0700 (PDT)
Links: << >> << T >> << A >>

On Apr 7, 10:46=A0pm, "teixeira" <teixeira...@gmail.com> wrote:
> I am working on a project with a microblaze.
> I have added some custom peripherals and would like to debug the internal
> signals.
> I am able to debug the input and output ports via the EDK design by addin=
g
> the supplied IPs.
>
> How can I insert a chipscope to debug the internal signals of my blocks?

I've not done this before in EDK but maybe it works. First, generate
the ICON and ILA core using Coregen (in ISE 10.1) or Chipscope (lower
versions) and copy the generated .ngc files to your project's
directory. Then find the templates inside .vho (assuming you are using
vhdl) files and instantiate them inside your custom peripherals vhdl
code and connect those internal signals to the ILA ports. Then
synthesize and implement your design.

Article: 139681
Subject: Re: Two stage synchroniser,how does it work?
From: rickman <gnuarm@gmail.com>
Date: Wed, 8 Apr 2009 21:22:04 -0700 (PDT)
Links: << >> << T >> << A >>

On Apr 8, 2:48 pm, "kadhiem_ayob" <kadhiem_a...@yahoo.co.uk> wrote:
> Thanks Muzaffar,
>
> I am not trying to achieve any practical problems. Thank goodness I have
> designed complete multiclock modulator systems for decades now.
> I am simply looking inside "my thoughts" and make sure I am not getting
> too old.
> I possibly understand data is either 0 or 1, the absolute value doesn't
> matter but the sequence does matter ofcourse and that a few clk latency is
> not an issue but the sequence of 0 and 1 from one clk must pass to second
> clk domain. Well it does in practice.
> The crux of my disorder lies in our thinking model: flip1 is at the mercy
> of its input and is thrown into chaos from time time. flip2 absorbs the
> impact, fair. Are we saying data sequence at Q1 correctly follows D1
> eventually despite the chaos? in that case no problem but literature says
> Q1 can be '0' or '1' or in between or oscilating or so then settle as '0'
> or '1'...
> if it does settle at D1 value then please ignore this post completely.
> It is simple primary math of vectors(ignoring latency):
> D1 => Q1
> Q1 is D2
> D2 => Q2
>
> so if Q2 = D1 then Q1 = D1
> Hence Q1 settles finally at end of clk period to D1(current or previous or
> next)

Yes, that is it pretty much.  Q1 will most probably settle in the
slack time of the clock cycle between Q1 and Q2.  The longer that
slack time is the more likely it is to settle to a point that after
some 5 ns it is 1 in a few billion billion billion or so.

The purpose of FF2 is to assure that the circuitry receiving this
signal sees a stable state within the clock to output delay spec.  So
while Q1 only has to be stable before the end of a clock cycle, Q2 has
to be stable within the specified time.

Rick

Article: 139682
Subject: Re: ANN: Antti-Brain March issue released
From: "Antti.Lukats@googlemail.com" <Antti.Lukats@googlemail.com>
Date: Wed, 8 Apr 2009 21:34:42 -0700 (PDT)
Links: << >> << T >> << A >>

On Apr 9, 4:46=A0am, -jg <Jim.Granvi...@gmail.com> wrote:
> On Apr 9, 11:18=A0am, Manny <mlou...@hotmail.com> wrote:
>
> > Same here; Vista Firefox.
>
> > -Momo
>
> Firefox/Win2000 here, shows 8 PDF's, one of which
>
> AnttiBrain_Issue8_MAR2009.pdf =A0Antti.Luk...@googlemail.com =A01.6 MB
> Apr 7
>
> that pdf opens with a caption "Hello, from Amontec STM32!"
> - seems OK to me ?
>
> -jg

Hi

seems ok yes, but thanks for reporting a problem, I will keep
monitoring as well
should they disappear from google, i will relocate all files to my own
server
so they will remain online for sure

Antti

Article: 139683
Subject: Re: About DSP48 used for 24bit * 18bit
From: rickman <gnuarm@gmail.com>
Date: Wed, 8 Apr 2009 21:49:18 -0700 (PDT)
Links: << >> << T >> << A >>

On Apr 8, 7:55=A0pm, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> On Wed, 8 Apr 2009 08:09:39 -0700 (PDT), bluesea.x...@gmail.com wrote:
> >I want to use DSP48A for a Semi-Parallel FIR filter. Since DSP48A is
> >18bit*18bit;so i need 2 slice of DSP48A for a multiplier. but how can
> >i utilize the 2 slice DSP48A's internal 48bit post Adder for the
> >Accumulation. or maybe it can only need the 3rd DSP48A for the
> >Accumulation?
>
> In which FPGA family?

Good question.

Article: 139684
Subject: reconfiguration in spartan 3
From: "samece" <samece87@gmail.com>
Date: Thu, 09 Apr 2009 00:59:58 -0500
Links: << >> << T >> << A >>


Hi all,
Am working with Spartan 3 starter kit.  May i know whether this kit
supports reconfiguration. My aim is to reconfigure the fpga for different
architectures.
Anyone pls help me in this regard as soon as you can..

Article: 139685
Subject: Programming in Microblaze
From: "samece" <samece87@gmail.com>
Date: Thu, 09 Apr 2009 01:06:44 -0500
Links: << >> << T >> << A >>

Hi all,
May i know how a simple addition operation can be performed using a
Microblaze processor implemented in a Spartan 3 kit (xc3s-4ft256).  I have
implemented the processor in the kit and have got stuck at developing any
application program for that processor.
Can anyone pls help me in this regard.

Article: 139686
Subject: Re: Programming in Microblaze
From: "Antti.Lukats@googlemail.com" <Antti.Lukats@googlemail.com>
Date: Wed, 8 Apr 2009 23:16:56 -0700 (PDT)
Links: << >> << T >> << A >>

On Apr 9, 9:06=A0am, "samece" <samec...@gmail.com> wrote:
> Hi all,
> May i know how a simple addition operation can be performed using a
> Microblaze processor implemented in a Spartan 3 kit (xc3s-4ft256). =A0I h=
ave
> implemented the processor in the kit and have got stuck at developing any
> application program for that processor.
> Can anyone pls help me in this regard.

result =3D a + b;

Article: 139687
Subject: opencores again with problems?
From: Antti <Antti.Lukats@googlemail.com>
Date: Wed, 8 Apr 2009 23:48:12 -0700 (PDT)
Links: << >> << T >> << A >>

account login claims wrong password
password reset works, but the new password is also not accepted

tried to create new account (as old account could not login)
but eh, just to download a single file i need to fill SO MUCH
information?
including phone number, etc..
and then it is sent "for approval"

eh, opencores is really getting JUST ANNOYING!!


Antti

Article: 139688
Subject: Re: opencores again with problems?
From: "Antti.Lukats@googlemail.com" <Antti.Lukats@googlemail.com>
Date: Thu, 9 Apr 2009 00:15:31 -0700 (PDT)
Links: << >> << T >> << A >>

On Apr 9, 9:48=A0am, Antti <Antti.Luk...@googlemail.com> wrote:
> account login claims wrong password
> password reset works, but the new password is also not accepted
>
> tried to create new account (as old account could not login)
> but eh, just to download a single file i need to fill SO MUCH
> information?
> including phone number, etc..
> and then it is sent "for approval"
>
> eh, opencores is really getting JUST ANNOYING!!
>
> Antti

wau, it started to work 3 minutes after sending email to opencores!

Antti

Article: 139689
Subject: The data cann't written into DDR2 when DMA burst > 64bytes at ML505
From: "murlary@gmail.com" <murlary@gmail.com>
Date: Thu, 9 Apr 2009 00:31:10 -0700 (PDT)
Links: << >> << T >> << A >>

It works fine when DMA burst=64bytes .it can be written into /read
from DDR2 SDRAM at ML505.The DMA file is from Xapp859
(dma_ddr2_if.v).The mig controller is 125MHz 2.3 version.



But,when i change the DMA burst length=128bytes,512 bytes. the data
cann't written into specify address(0x000~0x200),and it was written
into a offset address.(0x09c~0x029c)!!!



eg:The initial data(0x0~0x200) on DDR2 SDARM from ML5005 after power
on is the following



0000000: 65a9 52a6 bc86 5ca7 75a9 5bb6 3ca6 5c87
0000010: 6581 58a6 3c96 5c83 65a1 7ae7 a496 dde7
0000020: 65a9 5aa6 3c96 5c87 1928 f000 0b96 1140
0000030: 5da9 5aa6 fc96 548f 65b9 ca34 3c97 58c3
0000040: 65ad 5aa6 3c96 5c86 8904 19a6 2706 5005
0000050: e5a9 3aa6 7db2 5ec7 45a9 528e 3487 5487
0000060: 65a9 9aa6 bc96 1cc7 65a9 5ba6 3c9e 5cc7
0000070: 65a1 4aa6 3c96 1c87 65fd 5bce 3c97 d4a7
0000080: 64a9 5aa6 3c86 1cc7 71a9 58a4 3c96 5c05
0000090: 6489 0aa4 3c16 5c8d 6dad 5aee 1c96 7cd7
00000a0: eeee eeee eeee eeee 1111 1111 1111 1111
00000b0: 1111 1111 1111 1111 eeee eeee eeee eeee
00000c0: eeee eeee eeee eeee 1111 1111 1111 1111
00000d0: 1111 1111 1111 1111 eeee eeee eeee eeee
00000e0: 1800 2001 2004 8000 0d08 0000 0000 2004
00000f0: 1000 b280 2008 0200 1050 1100 0240 c840
0000100: 0000 0428 4000 0000 000b 0038 0014 8000
0000110: 0400 0022 0000 8000 1040 0140 60a2 22c1
0000120: 1000 1000 0000 0000 4087 6000 1ac5 9409
0000130: 0240 0000 0000 0040 4000 219f 2a00 208a
0000140: 0800 0000 8000 0108 3fa2 1153 9420 82d2
0000150: 0000 0401 0080 1000 0024 1801 8a05 0044
0000160: 0020 4020 0903 8000 0048 0100 0000 0800
0000170: 4300 0000 0090 00a0 0c55 0008 4112 a141
0000180: 0000 2000 2000 0800 0810 8248 0020 0100
0000190: 0888 0200 0010 0000 1405 2204 4208 4060
00001a0: 0010 0188 0020 0000 3585 528c 3e02 1c01
00001b0: 0008 0810 0008 0002 1628 ea00 0004 0100
00001c0: 0008 0400 4020 0000 cdbd d8b4 cc10 a2ba
00001d0: 0000 0000 c000 0800 0031 9848 0019 d000
00001e0: 0220 0822 48a0 0000 02a0 0000 4401 0071
00001f0: 8800 0100 0081 0010 0052 0014 1120 0000

after i write 512bytes,the data is the following.





0000000: 9c80 5ca7 7559 5bf7 34a7 7887 e597 10e6
0000010: 3c86 5c83 a5b1 7877 a43e fdef 65a9 5aa6
0000020: 3c96 5c87 1970 f001 0b86 1140 5da9 d2a0
0000030: fc96 558f 41bd c834 2887 59c1 65ad 0ea6
0000040: bc96 5c86 8904 39a2 2700 1205 e7a9 2aae
0000050: f932 1ec7 452d 518c 3487 54a3 a5e9 9aa2
0000060: b4de 1cc7 77ab 5fa6 3c8e 5cd7 65a0 6aa6
0000070: 3c96 1c85 25fd 5bcc bc97 f0e7 6429 5aa6
0000080: 3c86 9cc7 71a8 58a4 3c96 5945 6088 aaa4
0000090: b056 1c0d 4dad 5eef 1c9e 7cd1 0000 0000
00000a0: 0000 0000 0000 0000 0000 0000 0000 0000
00000b0: 0000 0000 0000 0000 0000 0000 0000 0000
00000c0: 0000 0000 0000 0000 0000 0000 0000 0000
00000d0: 0000 0000 0000 0000 0000 0000 0000 0000
00000e0: 0000 0000 0000 0000 0000 0000 0000 0000
00000f0: 0000 0000 0000 0000 0000 0000 0000 0000
0000100: 0000 0000 0000 0000 0000 0000 0000 0000
0000110: 0000 0000 0000 0000 0000 0000 0000 0000
0000120: 0000 0000 0000 0000 0000 0000 0000 0000
0000130: 0000 0000 0000 0000 0000 0000 0000 0000
0000140: 0000 0000 0000 0000 0000 0000 0000 0000
0000150: 0000 0000 0000 0000 0000 0000 0000 0000
0000160: 0000 0000 0000 0000 0000 0000 0000 0000
0000170: 0000 0000 0000 0000 0000 0000 0000 0000
0000180: 0000 0000 0000 0000 0000 0000 0000 0000
0000190: 0000 0000 0000 0000 0000 0000 0000 0000
00001a0: 0000 0000 0000 0000 0000 0000 0000 0000
00001b0: 0000 0000 0000 0000 0000 0000 0000 0000
00001c0: 0000 0000 0000 0000 0000 0000 0000 0000
00001d0: 0000 0000 0000 0000 0000 0000 0000 0000
00001e0: 0000 0000 0000 0000 0000 0000 0000 0000
00001f0: 0000 0000 0000 0000 0000 0000 0000 0000
0000200: 0000 0000 0000 0000 0000 0000 0000 0000
0000210: 0000 0000 0000 0000 0000 0000 0000 0000
0000220: 0000 0000 0000 0000 0000 0000 0000 0000
0000230: 0000 0000 0000 0000 0000 0000 0000 0000
0000240: 0000 0000 0000 0000 0000 0000 0000 0000
0000250: 0000 0000 0000 0000 0000 0001 0100 83fe
0000260: 3f1e 3f00 0000 2099 0700 0000 0000 0000
0000270: 0000 0000 0000 0000 0000 0000 0000 0000
0000280: 0000 0000 0000 0000 0000 0000 0000 0000
0000290: 0000 0000 0000 0000 0000 55aa 4200 8000

However,the correctly written data should be the following



0000000: 0000 0000 0000 0000 0000 0000 0000 0000
0000010: 0000 0000 0000 0000 0000 0000 0000 0000
0000020: 0000 0000 0000 0000 0000 0000 0000 0000
0000030: 0000 0000 0000 0000 0000 0000 0000 0000
0000040: 0000 0000 0000 0000 0000 0000 0000 0000
0000050: 0000 0000 0000 0000 0000 0000 0000 0000
0000060: 0000 0000 0000 0000 0000 0000 0000 0000
0000070: 0000 0000 0000 0000 0000 0000 0000 0000
0000080: 0000 0000 0000 0000 0000 0000 0000 0000
0000090: 0000 0000 0000 0000 0000 0000 0000 0000
00000a0: 0000 0000 0000 0000 0000 0000 0000 0000
00000b0: 0000 0000 0000 0000 0000 0000 0000 0000
00000c0: 0000 0000 0000 0000 0000 0000 0000 0000
00000d0: 0000 0000 0000 0000 0000 0000 0000 0000
00000e0: 0000 0000 0000 0000 0000 0000 0000 0000
00000f0: 0000 0000 0000 0000 0000 0000 0000 0000
0000100: 0000 0000 0000 0000 0000 0000 0000 0000
0000110: 0000 0000 0000 0000 0000 0000 0000 0000
0000120: 0000 0000 0000 0000 0000 0000 0000 0000
0000130: 0000 0000 0000 0000 0000 0000 0000 0000
0000140: 0000 0000 0000 0000 0000 0000 0000 0000
0000150: 0000 0000 0000 0000 0000 0000 0000 0000
0000160: 0000 0000 0000 0000 0000 0000 0000 0000
0000170: 0000 0000 0000 0000 0000 0000 0000 0000
0000180: 0000 0000 0000 0000 0000 0000 0000 0000
0000190: 0000 0000 0000 0000 0000 0000 0000 0000
00001a0: 0000 0000 0000 0000 0000 0000 0000 0000
00001b0: 0000 0000 0000 0000 0000 0001 0100 83fe
00001c0: 3f1e 3f00 0000 2099 0700 0000 0000 0000
00001d0: 0000 0000 0000 0000 0000 0000 0000 0000
00001e0: 0000 0000 0000 0000 0000 0000 0000 0000
00001f0: 0000 0000 0000 0000 0000 0000 0000 55aa









......why is the addr is offset when burst>64bytes?

Article: 139690
Subject: system C versus VHDL|verilog|specman ....
From: bknpk@hotmail.com
Date: Thu, 9 Apr 2009 01:51:34 -0700 (PDT)
Links: << >> << T >> << A >>

I would like to know if system C is used in the high tech industry as
main tool for sign-off during development of RTL and verification.

For me system C is a great, free and high performance hardware
simulator with the C++ as a verification engine.

As a pilot, I took a little design from a customer and converted its
RTL to system C. Since this DUT uses buses of greater than 64 bits,
free verilog to system C tools, did not deliver. I did the conversion
manually.
The results as well as the verification code and its description is
available free at:
http://bknpk.no-ip.biz/First_SCV/aisTB.html

Article: 139691
Subject: Re: Two stage synchroniser,how does it work?
From: News123 <news123@free.fr>
Date: Thu, 09 Apr 2009 10:56:01 +0200
Links: << >> << T >> << A >>

Here another attempt to explain.

clock domain crossing from D1 to D2

D1 -> Q1
Within the same clock domain Q1 would change very shortly after the
posedge of the clock to 0 or to 1

If you have a change of D1 ver close to the posedge of the clock several
things might happen.
Q1 follows D1, but with a very weak slope.
Q1 oscillates for quite some time before stabilizing.
combinatorial logic might capture Q1 either as 0 or as 1 or 'just'
consume mcuh more current while being in this meta state.
The BAD thing is that part of the combinatorial logic following Q1 might
read a 0 and the others read a 1.

Assume, that you had combinatorial logic being feed by Q1.

As the threshold for 0 / 1 values is not exactly the same for each cell
it might be, that parts of the following logic
might catch a 0 and other parts of the combinatorial logic might catch a
1. perhaps it's just one path through this combinatorial logic, which
will have a timing violation due to the bad slope of Q1.

Imagine for example, that you want to calculate A (another signal ) xor
D1 ( our metastable signal or our signal changing with a horrible bad slope)

Example:
--------
Imagine you had some logic (logic1), which would switch on a candle if
Q1 were 1
and another part of the logic (logic2) which would pour some petrol in a
 opened  tank if Q1 were 0

I a stable design you don't want to light candles while pouring petrol
into an open tank.

So it is not desirable to have logic1 and logic2 to behave different,
just because one logic samples the meta stable signal as 0 and the other
logic samples it as 1.

Therefore you just capture Q1 (== D2) with a flop (FF2)  to create Q2.
Bethween the FF which created Q1 and the next flip flop there is no
logic, just a wire, so a signal with a bad slope would have had enough
time to change to a value which will be clearly enough recognized as a 1
or a 0. If the signal D1 were oscillating the oscillation did hopefuly
settle down before FF2.
As pointed out earlier. This is 'just' a measure to drastically reduce
the probability to have flip flop outputs, which oscillate, have a bad
slope.
but at least your 1 bit signal will be a reliable input to a
combinatorial logic cloud.

as you know: retiming a data bus wider than one bit is a completely
different beast and requires other meaures.

bye

N

kadhiem_ayob wrote:
> Thanks Muzaffar,
> 
> I am not trying to achieve any practical problems. Thank goodness I have
> designed complete multiclock modulator systems for decades now.
> I am simply looking inside "my thoughts" and make sure I am not getting
> too old.
> I possibly understand data is either 0 or 1, the absolute value doesn't
> matter but the sequence does matter ofcourse and that a few clk latency is
> not an issue but the sequence of 0 and 1 from one clk must pass to second
> clk domain. Well it does in practice.
> The crux of my disorder lies in our thinking model: flip1 is at the mercy
> of its input and is thrown into chaos from time time. flip2 absorbs the
> impact, fair. Are we saying data sequence at Q1 correctly follows D1
> eventually despite the chaos? in that case no problem but literature says
> Q1 can be '0' or '1' or in between or oscilating or so then settle as '0'
> or '1'...
> if it does settle at D1 value then please ignore this post completely.
> It is simple primary math of vectors(ignoring latency):
> D1 => Q1
> Q1 is D2
> D2 => Q2
> 
> so if Q2 = D1 then Q1 = D1 
> Hence Q1 settles finally at end of clk period to D1(current or previous or
> next)
> 
> 
> 
> 
> 
> 
>

Article: 139692
Subject: Re: Two stage synchroniser,how does it work?
From: "kadhiem_ayob" <kadhiem_ayob@yahoo.co.uk>
Date: Thu, 09 Apr 2009 05:27:46 -0500
Links: << >> << T >> << A >>

Let me recap the possibilties of Q1 transition events:
1. Q1 => '1'
2. Q1 => '0'
3. Q1 => D1 but slowly, hesitantly...
4. Q1 => oscillates then => '1'
5. Q1 => oscillates then => '0'
6. Q1 => oscillates then => D1
7. Q1 => oscillates
8. Q1 => halfway then ...etc.

of these, practical field work indicates possibilty of 3 or 6 being high
enough that we can safely ignore the rest of events.

probabilty 6 is bizarre since the flip has no memory of D1 state at that
moment of change.

So shouldn't we now change our wording and concept and say that Q1 will
most likely follow D1 eventually in case of flip timing violation in
current technology?

Article: 139693
Subject: Re: Two stage synchroniser,how does it work?
From: Alan Fitch <alan.fitch@spamtrap.com>
Date: Thu, 09 Apr 2009 11:47:06 +0100
Links: << >> << T >> << A >>

NigelE wrote:
> On Apr 8, 8:51 am, "kadhiem_ayob" <kadhiem_a...@yahoo.co.uk> wrote:
>> I have no doubt that a two stage synchroniser works for crossing clk
>> domains
>> (or synchronising any asynchronous signal), however I have struggled for
>> years to get convinced with the theoretical explanations(including the ball
>> over the hill analogy).
>> Surely the first flip will get into wrong output due to timing violation.
>> This wrong output becomes the wrong input to second flip. So how does data
>> get through correctly?
>>
>> Any help appreciated...
>>
>> kadhiem
> 
> There's an online presentation that goes into the various effects off
> async clock domain crossing and the use of 2 x DFF synchronisers that
> you may find useful.
> 
> This is part of a verification seminar covering Mentor's 0-In CDC
> verification solution and can be found here:
> https://admin.na3.acrobat.com/_a781163502/vscdc/
> 
> Regards
> - Nigel
> Mentor Graphics

There's also some nice information at

http://www.fpga-faq.com/FAQ_Pages/0017_Tell_me_about_metastables.htm

including some pictures of the output of a meta-stable flip-flop,

regards
Alan



-- 
Alan Fitch
Senior Consultant

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Article: 139694
Subject: Re: @@@@@@@@About DSP48 used for 24bit * 18bit @@@@@@@@
From: bluesea.xjtu@gmail.com
Date: Thu, 9 Apr 2009 04:22:03 -0700 (PDT)
Links: << >> << T >> << A >>

On 4=D4=C29=C8=D5, =C9=CF=CE=E77=CA=B155=B7=D6, Brian Drummond <brian_drumm=
...@btconnect.com> wrote:
> On Wed, 8 Apr 2009 08:09:39 -0700 (PDT), bluesea.x...@gmail.com wrote:
> >I want to use DSP48A for a Semi-Parallel FIR filter. Since DSP48A is
> >18bit*18bit;so i need 2 slice of DSP48A for a multiplier. but how can
> >i utilize the 2 slice DSP48A's internal 48bit post Adder for the
> >Accumulation. or maybe it can only need the 3rd DSP48A for the
> >Accumulation?
>
> In which FPGA family?
>
> - Brian

spartan3ADSP 1800

Article: 139695
Subject: Re: About DSP48 used for 24bit * 18bit
From: rickman <gnuarm@gmail.com>
Date: Thu, 9 Apr 2009 04:59:10 -0700 (PDT)
Links: << >> << T >> << A >>

On Apr 9, 7:22 am, bluesea.x...@gmail.com wrote:
> On 4=D4=C29=C8=D5, =C9=CF=CE=E77=CA=B155=B7=D6, Brian Drummond <brian_dru=
mm...@btconnect.com> wrote:
>
> > On Wed, 8 Apr 2009 08:09:39 -0700 (PDT), bluesea.x...@gmail.com wrote:
> > >I want to use DSP48A for a Semi-Parallel FIR filter. Since DSP48A is
> > >18bit*18bit;so i need 2 slice of DSP48A for a multiplier. but how can
> > >i utilize the 2 slice DSP48A's internal 48bit post Adder for the
> > >Accumulation. or maybe it can only need the 3rd DSP48A for the
> > >Accumulation?
>
> > In which FPGA family?
>
> > - Brian
>
> spartan3ADSP 1800

Article: 139696
Subject: Re: Two stage synchroniser,how does it work?
From: rickman <gnuarm@gmail.com>
Date: Thu, 9 Apr 2009 05:18:54 -0700 (PDT)
Links: << >> << T >> << A >>

On Apr 9, 6:27 am, "kadhiem_ayob" <kadhiem_a...@yahoo.co.uk> wrote:
> Let me recap the possibilties of Q1 transition events:
> 1. Q1 => '1'
> 2. Q1 => '0'
> 3. Q1 => D1 but slowly, hesitantly...
> 4. Q1 => oscillates then => '1'
> 5. Q1 => oscillates then => '0'
> 6. Q1 => oscillates then => D1
> 7. Q1 => oscillates
> 8. Q1 => halfway then ...etc.
>
> of these, practical field work indicates possibilty of 3 or 6 being high
> enough that we can safely ignore the rest of events.
>
> probabilty 6 is bizarre since the flip has no memory of D1 state at that
> moment of change.
>
> So shouldn't we now change our wording and concept and say that Q1 will
> most likely follow D1 eventually in case of flip timing violation in
> current technology?

This seems to be what you are not grasping.  When you are talking
about a metastable event, by definition this is when D1 is changing
between states.  Or in other words, D1 is ***not*** in a defined state
of 0 or 1.  Remember that a digital signal is still *analog* in nature
and the digital state is just in the way we interpret the state.  So
if D1 is in transition between a 0 and a 1 when the clock edge
happens, the FF does not know what state D1 is in because it is
***not*** in a valid digital state.  So to say that Q1 follows D1 on a
metastable event would mean that Q1 stays at an indeterminate
voltage!!!

What really happens is that the FF has to decide whether to end up in
a 0 or a 1 state, not based on where the input is, but randomly.  But
that does not matter.  The input was in transition between the two
states, so it is perfectly valid to interpret that state as either a 0
or a 1.  If the clocking was a hair earlier it would be one value if
it was a hair later it would be the other value.  Consider this...

Clk  __-----_____-----_____-----_____-----_____---
D1   _________-------------_______________________
Q1   _____________----------xxxxxxx---____________
Q1'  _____________----------xxxxxxx_______________
Q1'' _____________----------______________________
Q1'''_____________--------------------____________
Q2   _______________________----------____________
Q2'  _______________________--------------------__

Which is the correct output, Q1 or Q1'?  The point is that
***either*** is correct logically.  The problem is that the settling
time is way beyond the specified output delay.  It is entirely
possible that you will get Q1'' or Q1''' as well.  Which of those is
correct?  Again, either is correct!  Likewise, either Q2 or Q2' is
correct.

So what do you mean when you refer to Q1 => D1???  What was D1 when
the clock edge occurred?

Rick

Article: 139697
Subject: Re: opencores again with problems?
From: rickman <gnuarm@gmail.com>
Date: Thu, 9 Apr 2009 05:52:05 -0700 (PDT)
Links: << >> << T >> << A >>

On Apr 9, 3:15 am, "Antti.Luk...@googlemail.com"
<Antti.Luk...@googlemail.com> wrote:
> On Apr 9, 9:48 am, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > account login claims wrong password
> > password reset works, but the new password is also not accepted
>
> > tried to create new account (as old account could not login)
> > but eh, just to download a single file i need to fill SO MUCH
> > information?
> > including phone number, etc..
> > and then it is sent "for approval"
>
> > eh, opencores is really getting JUST ANNOYING!!
>
> > Antti
>
> wau, it started to work 3 minutes after sending email to opencores!
>
> Antti

I think they have taken a large step sideways.  Opencores was never
about presentation.  It was about the content.  The only reason to
muck with the presentation is to attract advertisers which seems to be
what they are aiming for.  I guess that's fine, but in the process
they appear to be ignoring the reason why people visit their site.  I
have not used any of the cores there, but I spent a fair amount of
time researching the available CPU designs.  The big problem I found
was that there is no info presented at the high level view of
available cores and there is no summary of each design.  The
respective authors are free to document (or not document) their
designs as they see fit.  As a result the information available varies
from lots of documentation with a good summary on the initial page
(only a small number manage to do this) to literally no info since the
project was stillborn (or more appropriately, never really
conceived).

I think they would do themselves a world of good to provide some sort
of index that actually offers more than an abbreviated name list.  The
initial table shows the title of the project along with the least
amount of info possible.  In fact, they use a fixed width table which
does not fit in my browser window without panning while wasting a
portion of the page width with white space and often truncating the
titles to fit the table!

I just don't see where they have *added* anything to the utility of
the web pages and I can see some things that have been lost.

Rick

Article: 139698
Subject: Re: opencores again with problems?
From: "Symon" <symon_brewer@hotmail.com>
Date: Thu, 9 Apr 2009 14:04:32 +0100
Links: << >> << T >> << A >>


"rickman" <gnuarm@gmail.com> wrote in message 
news:422e8790-d992-4a8a-b51a-871688f231ca@v28g2000vbb.googlegroups.com...
>   I
> have not used any of the cores there, but I spent a fair amount of
> time researching the available CPU designs.
>
> Rick

In the spirit of FOSS, would you share the results of your research? Maybe 
offer it to the opencores website to help others.
Thanks, Symon.

Article: 139699
Subject: Re: How to insert Chipscope blocks directly in Xilinx Project Navigator
From: "maxascent" <maxascent@yahoo.co.uk>
Date: Thu, 09 Apr 2009 12:42:15 -0500
Links: << >> << T >> << A >>

If I recall correctly you should be able to just go to New on the ISE menu
and add a chipscope block. You can then just configure it to add the
signals that you need.

Jon

>Dear all,
>
>1. I want to insert Chipscope blocks (ICON, ILA) into my design in
>Xilinx project navigator.
>2. I generated blocks from Chipscope Core Generator (.edn, .vhd, .ncf)
>but I do not know how I can assign .edn file into project navigator.
>3. I always used Mentor Graphics HDL Designer for design entry and it
>was very easy in that. I also know how to use signal tap (for Altera)
>but never used Chipscope directly with Project Navigator.
>
>request for the some suggestions.
>Thanks
>Mukesh
>

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