Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On Apr 6, 9:03=A0am, "Dave Wilson" <d...@noaddress.net> wrote: > "Jonathan Bromley" <jonathan.brom...@MYCOMPANY.com> wrote in message > > news:4g4it4d9ah49jmotmo9btar8lmd8qoa3cm@4ax.com... > > > > > On Sun, 5 Apr 2009 21:55:21 +0200, "Xin Xiao" wrote: > > >>Thanks, but I have to do it with schematics..... > > > Oh dear. =A0Why? > > > Basic Metalwork course, Lab 1: > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > You are given a piece of steel approximately > > 5cm x 5cm x 5cm. =A0Your task is to construct > > a steel cylinder, of diameter 3cm and length > > 4cm, without using a lathe. =A0Marks will be > > deducted for any evidence that you borrowed > > your friend's CNC milling machine. =A0Extra > > credit is available for completing the task > > using tools made only from elk antlers. > > > -- > > Jonathan Bromley, Consultant > > > DOULOS - Developing Design Know-how > > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > > jonathan.brom...@MYCOMPANY.com > >http://www.MYCOMPANY.com > > > The contents of this message may contain personal views which > > are not the views of Doulos Ltd., unless specifically stated. > > ???? > If he was using Altera Quartus schematic then it would take less than 10 > seconds using the LPM_COUNTER wizard - about 100 times faster than using > crap VHDL. [sarcasm on] An we don't need to waste any time on that simulation stuff, either [sarcasm off] I don't know any reasonably sized companies that would hire a person that wasn't well versed in an HDL. There's a reason - using an HDL is far more productive, portable, and re-usable. AND... you can use off-the-shelf source code control systems with an HDL. I haven't drawn a schematic (other than for spice) in years. I don't miss schematics at all. John ProvidenzaArticle: 139601
On Apr 3, 7:02=A0pm, Mike Treseler <mtrese...@gmail.com> wrote: > > On Apr 3, 4:02 pm, gabor <ga...@alacron.com> wrote: > >> Have you tried instantiation to make sure what you want to do > >> is really possible and there isn't some other gotcha that > >> keeps synthesis from coming up with your preferred solution? > > I think this is quite likely. > > Either there is some non-obvious kludge > in the epic architecture, > or synthesis missed an optimization. > > Unless I were down to my last gate, > I wouldn't spend time worrying about > which one it is. This is a design that will be used repeatedly and will be used in tight quarters. So saving a LUT on every adder and counter can be quite useful. I found that a coding style difference saved 3 LUTs in an 8 bit adder with overflow detection. That's about a 30% savings. In the long run I expect to save about 25% to 30% overall in the design. I think that is significant. Yes, what I am trying to do is possible. It just seems like the tools want to add an inefficiency one way or the other. I wrote to Lattice and their suggestion is avoid using the synthesis tool and to instantiate my logic. Hmmm. Maybe Lattice shouldn't be my first choice in FPGAs. RickArticle: 139602
On Mar 16, 1:49=A0pm, gabor <ga...@alacron.com> wrote: > On Mar 13, 6:55=A0am, David Fejes <fej...@gmail.com> wrote: > > > Hello, > > > Maybe this is a bit offtopic but may I ask you what kind ofI2Cipcore > > do you use? I have to implement somei2cslave logic with some > > readable and writable registers in my next design and I'm curious > > about that.. > > > thank you in advance > > I wrote my own for a simple slave interface. =A0Look at this > thread on the Xilinx forums: > > http://forums.xilinx.com/xlnx/board/message?board.id=3DSpartan&message...= . Hi, I tried reducing the SCL frequency but I did not work out. I bought I2C EEPROM by Catalyst Semiconductor(CAT24C256) to replace Microchip I2C EEPROM(24AA256). Now I have totally different problem. I try to read from x0000 but the data from x6600 get displayed.I do not understand what is going on. Everything seems right in post route simulation but when it comes to hardware implementation, I have problems. Can any one please help? Thanks.Article: 139603
I need a program for Phase Locked Loop and its component like phase detector, VCO, Counter, Frequency divider and filter. the should run on Xilinx 7 version.Article: 139604
On Apr 7, 10:20=A0am, sheakeb...@gmail.com wrote: > I need a program for Phase Locked Loop and its component like phase > detector, VCO, Counter, Frequency divider and filter. the should run > on Xilinx 7 version. Virtex-7 you mean? or? AnttiArticle: 139605
sheakeb517@gmail.com wrote: > I need a program for Phase Locked Loop and its component like phase > detector, VCO, Counter, Frequency divider and filter. the should run > on Xilinx 7 version. I need $1 million. And I'd like to be a touch taller. -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 139606
On 6 Apr., 09:54, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Sun, 5 Apr 2009 23:42:12 -0700 (PDT), goo...@twinmail.de wrote: > >Ok, you get this warning about possible dangers arising from clock > >skew. > >This is definitly true, and would affect your design if you would play > >in the X- MHz league. > >But for your 10Hz design you probably could have 64bit combinatorical > >multipliers in your datapath without being bothered by clock skew > >problems. > > OUCH - dangerous myth... as Eilert knows well, I hope. > > Clock skew is likely to lead to hold time violations, > which break the design's functionality on EACH INDIVIDUAL > clock edge. =A0Hold problems are not related to the time > between clocks, and cannot be fixed by running the clock > more slowly. > > >(Actually, some logic between your FFs would be > >very useful in this case.) > > Yes; hold-time fixup. =A0Some FPGA tools already do this for you > to some extent. > > For a small, slow design, the message is clear: > USE CLOCK ENABLES. =A0Get your divide-by-10 circuit to > generate a synchronous pulse that is true for 1 cycle > of the 10Hz clock, and false for 9 cycles. =A0Use that > pulse as the clock enable for any logic that you want > to run at 1Hz. =A0Use the single, common 10Hz clock > as the clock input for every flip-flop in the design. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. Hi Jonathan, I wanted Xin to do some thinking for himself, but it's ok that you pointed out the details so we can talk about it some more. Truly, hold time violations can occur independent of the clock frequency. But if I remember it correctly Xilinx FPGA CLB-FFs are specified with a hold time of '0', so I wonder if and how this can be violated? If data changes before the clock edge, its a setup violation, and any time after the edge it's ok. So it's just the few ps of the rising clock itself that can lead to a fault, which is not impossible, but quite unlikely for the average design. Or is there something more to consider? ______ Good design practice is to use clock enables, no doubt about that. But sometimes the designer is forced to use normal routing ressources to clock some FFs. eg. DDR Data Strobe signals. A design can have lots of them and most likely on normal IOBs. This is a critical part of the design and needs careful investigation. The only thing that reduces timing violation risks a little is the fact that the strobe drives only a very limited number of clock inputs which should be placed close together, reducing the skew to a minimum. So, knowledge of good design practice is one side of the medal, but somtimes it is neccessary to take a look on the other side as well. Regards EilertArticle: 139607
<sheakeb517@gmail.com> wrote in message news:335c1a51-7f71-430b-b87f-4d882f9be26e@i28g2000prd.googlegroups.com... >I need a program for Phase Locked Loop and its component like phase > detector, VCO, Counter, Frequency divider and filter. the should run > on Xilinx 7 version. Can I play? I need a drink. And a magic doner kebab that makes me thinner. p.s. In case anyone is interested, this is a link to a description of a useful piece of free software from Analog Devices. http://www.analog.com/static/imported-files/eval_boards/adisimpll.pdf It's easy to use it for non-AD devices.Article: 139608
On Mon, 06 Apr 2009 17:47:03 +0100, Jonathan Bromley
<jonathan.bromley@MYCOMPANY.com> wrote:
>On Mon, 6 Apr 2009 17:03:28 +0100, "Dave Wilson" wrote:
>
>I guess we'll have to agree to differ, but I gave up
>serious use of schematics a decade ago and I don't miss
>them even a tiny little bit.
Entity EL34 is
generic (
V_Heater : Real := 6.3;
V_grid : Real := -10;
V_scr : Real := 225;
V_anode : Real := 450;
g_m : Real := 11 -- mA/V
)
port (
Anode : signal_type;
Suppressor : signal_type;
Screen : signal_type;
Grid : signal_type;
Cathode : signal_type;
Heater1 : heater_type;
Heater2 : heater_type
)
end entity EL34;
Hmmm, I do believe schematics have their place.
Just not here.
- Brian
Article: 139609On Tue, 07 Apr 2009 13:03:18 +0100, Brian Drummond wrote: >Entity EL34 is [...] > >Hmmm, I do believe schematics have their place. LOL! But shouldn't the heater ports be LINKAGE? :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 139610
On Apr 7, 3:53=A0am, goo...@twinmail.de wrote: > On 6 Apr., 09:54, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> > wrote: > > > > > On Sun, 5 Apr 2009 23:42:12 -0700 (PDT), goo...@twinmail.de wrote: > > >Ok, you get this warning about possible dangers arising from clock > > >skew. > > >This is definitly true, and would affect your design if you would play > > >in the X- MHz league. > > >But for your 10Hz design you probably could have 64bit combinatorical > > >multipliers in your datapath without being bothered by clock skew > > >problems. > > > OUCH - dangerous myth... as Eilert knows well, I hope. > > > Clock skew is likely to lead to hold time violations, > > which break the design's functionality on EACH INDIVIDUAL > > clock edge. =A0Hold problems are not related to the time > > between clocks, and cannot be fixed by running the clock > > more slowly. > > > >(Actually, some logic between your FFs would be > > >very useful in this case.) > > > Yes; hold-time fixup. =A0Some FPGA tools already do this for you > > to some extent. > > > For a small, slow design, the message is clear: > > USE CLOCK ENABLES. =A0Get your divide-by-10 circuit to > > generate a synchronous pulse that is true for 1 cycle > > of the 10Hz clock, and false for 9 cycles. =A0Use that > > pulse as the clock enable for any logic that you want > > to run at 1Hz. =A0Use the single, common 10Hz clock > > as the clock input for every flip-flop in the design. > > -- > > Jonathan Bromley, Consultant > > > DOULOS - Developing Design Know-how > > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > > The contents of this message may contain personal views which > > are not the views of Doulos Ltd., unless specifically stated. > > -- > > Jonathan Bromley, Consultant > > > DOULOS - Developing Design Know-how > > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > > The contents of this message may contain personal views which > > are not the views of Doulos Ltd., unless specifically stated. > > Hi Jonathan, > I wanted Xin to do some thinking for himself, but it's ok that you > pointed out the details so we can talk about it some more. > > Truly, =A0hold time violations can occur independent of the clock > frequency. > But if I remember it correctly Xilinx FPGA CLB-FFs are specified with > a hold time of '0', =A0so =A0I wonder if and how this can be violated? > If data changes before the clock edge, its a setup violation, and any > time after the edge it's ok. > So it's just the few ps of the rising clock itself that can lead to a > fault, which is not impossible, but quite unlikely for the average > design. > Or is there something more to consider? The obvious thing to consider is the routing delay. For a global clock net, where the delay is almost the same to every load, the zero hold time will prevent hold violations. If your clock uses ordinary fabric routing, it is very easy to get skews in the nanoseconds range, definitely large enough to exceed the data delay and cause hold violations, and as Jonathan pointed out, this has nothing to do with the clock frequency. > ______ > Good design practice is to use clock enables, no doubt about that. > But sometimes the designer is forced to use normal routing ressources > to clock some FFs. > eg. DDR Data Strobe signals. A design can have lots of them and most > likely on normal IOBs. > This is a critical part of the design and needs careful investigation. > The only thing that reduces timing violation risks a little is > the fact that the strobe drives only a very limited number of clock > inputs which should be placed close together, reducing the skew to a > minimum. > > So, knowledge of good design practice is one side of the medal, but > somtimes it is neccessary to take a look on the other side as well. > > Regards > =A0 Eilert In the Xilinx world, you can have local routing for clocks over a small area and there is a constraint that forces use of low skew routing. In the OP's case, even using synchronous design practices (the counter he pulled from the library is an example of a synchronous counter design), the circuit will not work unless the clock uses global routing. Even if he uses a clock enable. Period. When you design with schematics, I believe it is necessary to place the BUFG in your clock path. It does not get inserted automatically as it might in an HDL design where you could just use the pin name as your clock net. This is at least how it worked back in Foundation 4.1i, the last version with decent (Aldec) schematics and the last time I used schematics for any FPGA design. On those old designs I placed a pad symbol followed by an IBUFG (for a global clock input pad) followed by a BUFG. The BUFG output was the clock net. You could also place an inverter at the output of the BUFG and it would get absorbed into the clock loads (turn all those library elements into falling-edge versions). I hope we haven't scared away the OP with the annual schematic v. HDL war ;-) Regards, GaborArticle: 139611
Hi,
I have trying to get a microblaze design to work without success. I
created the design using Xilinx XPS software. The design contains the
microblaze core, block rams for instruction and data, debug_module, a
dcm for clock generation and the xps_gpio core.
After creating the hardware and compiling successfully, I created a
small code to light up an led. It seems the bitstream generated is
correct since I can use the hardware debugger in the sdk software to
look at the content of the microblaze once it has been downloaded to
the FPGA.
The problem is the led does not light up and I do not know what can be
the cause.
I would really appreciate some help here since i've been trying to
solve this issue for a while now.
Thanks a lot,
Amish
Here is the code
[CODE]
#include "xparameters.h"
#include "xgpio.h"
int main()
{
XGpio switchInput; // gpio used for switches
XGpio ledOutput; // gpio used for leds
u32 switchData; // Data obtained from the switches
// Initialize the gpios
XGpio_Initialize(&switchInput, XPAR_SWITCH_DEVICE_ID);
XGpio_SetDataDirection(&switchInput, 1, 0xffffffff);
XGpio_Initialize(&ledOutput, XPAR_LED_DEVICE_ID);
XGpio_SetDataDirection(&ledOutput, 1, 0x00000000);
while (1) {
XGpio_DiscreteWrite(&ledOutput, 1, 0xffffffff);
}
return 0;
}
[/CODE]
Here is the .mhs content :
#
##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 10.1.03 Build
EDK_K_SP3.6
# Thu Apr 02 16:06:15 2009
# Target Board: Custom
# Family: spartan3e
# Device: xc3s500e
# Package: fg320
# Speed Grade: -4
# Processor: microblaze_0
# System clock frequency: 62.50 MHz
# On Chip Memory : 16 KB
#
##############################################################################
PARAMETER VERSION = 2.1.0
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ =
50000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST
PORT switch_GPIO_in_pin = switch_GPIO_in, DIR = I, VEC = [0:2]
PORT led_GPIO_IO_pin = led_GPIO_IO, DIR = O, VEC = [0:2]
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER C_INTERCONNECT = 1
PARAMETER HW_VER = 7.10.d
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_AREA_OPTIMIZED = 1
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DPLB = mb_plb
BUS_INTERFACE DEBUG = microblaze_0_dbg
BUS_INTERFACE IPLB = mb_plb
PORT MB_RESET = mb_reset
END
BEGIN plb_v46
PARAMETER INSTANCE = mb_plb
PARAMETER HW_VER = 1.03.a
PORT PLB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 2.10.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00007FFF
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 2.10.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00007FFF
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END
BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER HW_VER = 2.01.a
PARAMETER C_EXT_RESET_HIGH = 1
PARAMETER C_CLKIN_FREQ = 50000000
PARAMETER C_CLKOUT0_FREQ = 62500000
PARAMETER C_CLKOUT0_BUF = TRUE
PARAMETER C_CLKOUT0_PHASE = 0
PARAMETER C_CLKOUT0_GROUP = NONE
PORT CLKOUT0 = sys_clk_s
PORT CLKIN = dcm_clk_s
PORT LOCKED = Dcm_all_locked
PORT RST = net_gnd
END
BEGIN mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 1.00.d
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0x84400000
PARAMETER C_HIGHADDR = 0x8440ffff
BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg
BUS_INTERFACE SPLB = mb_plb
PORT Debug_SYS_Rst = Debug_SYS_Rst
END
BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER HW_VER = 2.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PORT Slowest_sync_clk = sys_clk_s
PORT Dcm_locked = Dcm_all_locked
PORT Ext_Reset_In = sys_rst_s
PORT MB_Reset = mb_reset
PORT Bus_Struct_Reset = sys_bus_reset
PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
PORT Peripheral_Reset = sys_periph_reset
END
BEGIN xps_gpio
PARAMETER INSTANCE = switch
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x85000000
PARAMETER C_HIGHADDR = 0x8500FFFF
PARAMETER C_GPIO_WIDTH = 3
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_IS_BIDIR = 0
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_in = switch_GPIO_in
END
BEGIN xps_gpio
PARAMETER INSTANCE = led
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x86000000
PARAMETER C_HIGHADDR = 0x8600FFFF
PARAMETER C_GPIO_WIDTH = 3
PARAMETER C_IS_BIDIR = 0
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_IO = led_GPIO_IO
END
Here is the .mss content
PARAMETER VERSION = 2.2.0
BEGIN OS
PARAMETER OS_NAME = standalone
PARAMETER OS_VER = 2.00.a
PARAMETER PROC_INSTANCE = microblaze_0
END
BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu
PARAMETER DRIVER_VER = 1.11.b
PARAMETER HW_INSTANCE = microblaze_0
PARAMETER COMPILER = mb-gcc
PARAMETER ARCHIVER = mb-ar
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = dlmb_cntlr
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ilmb_cntlr
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = lmb_bram
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = clock_generator_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 1.13.a
PARAMETER HW_INSTANCE = debug_module
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = proc_sys_reset_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
PARAMETER DRIVER_VER = 2.12.a
PARAMETER HW_INSTANCE = switch
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
PARAMETER DRIVER_VER = 2.12.a
PARAMETER HW_INSTANCE = led
END
Here is the .ucf file. Pin locations are for a Spartan3E500 xilinx
Eval board:
http://www.xilinx.com/products/devkits/HW-SPAR3E-SK-US-G.htm
############################################################################
## This system.ucf file is generated by Base System Builder based on
the
## settings in the selected Xilinx Board Definition file. Please add
other
## user constraints to this file based on customer design
specifications.
############################################################################
Net sys_clk_pin LOC=C9 | IOSTANDARD = LVCMOS33;
Net sys_rst_pin LOC=L13 | IOSTANDARD = LVTTL | PULLUP;
## System level constraints
Net sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 20000 ps;
Net sys_rst_pin TIG;
## IO Devices constraints
#### Module RS232 constraints
#Net fpga_0_RS232_RX_pin LOC=R7 | IOSTANDARD = LVTTL ;
#Net fpga_0_RS232_TX_pin LOC=M14 | IOSTANDARD = LVTTL | DRIVE = 8 |
SLEW = SLOW ;
Net switch_GPIO_in_pin<0> LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
Net switch_GPIO_in_pin<1> LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
Net switch_GPIO_in_pin<2> LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;
Net led_GPIO_IO_pin<0> LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW
| DRIVE = 8 ;
Net led_GPIO_IO_pin<1> LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW |
DRIVE = 8 ;
Net led_GPIO_IO_pin<2> LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW |
DRIVE = 8 ;
Article: 139612I'm currently using an ILA and inserting it using 10.1 software, I'm not having any issues.Article: 139613
I am working on a project with a microblaze. I have added some custom peripherals and would like to debug the internal signals. I am able to debug the input and output ports via the EDK design by adding the supplied IPs. How can I insert a chipscope to debug the internal signals of my blocks?Article: 139614
When will Xilinx release V6 software and demo boards? I have been looking for more information on the web but cant find much. The data sheet is missing but I found a press release saying they are shipping parts? jsdArticle: 139615
Hi, Sdram signals are going out of my design to a SDR SDRAM. This SDR SDRAM requires a setup time of 3.8 ns. The clock to SDRAM is provided by the design which is generated from the DCM with the source clock at 40 Mhz. I tried to put output constraints on other SDRAM control signals with respect to the clock generated in the design(to meet the setup time of SDRAM). But it is showing error as we should not put a constraint with respect to a output signal. If I put the constraints with respect to the input clock to the design, the working of the sdram is depending on the placement of the design in FPGA. Like, If I add chipscope signals it is working and if i dont add chipscope signals it is not working. In both cases the signals are going out of the FPGA as required. This I think is because of not meeting the setup time required. So, how can I ensure that the other SDRAM control signals are shifted by 3.8ns with respect to the SDRAM clock.Article: 139616
jsd, Right now, S6 and V6 are under a controlled new product release process. If you sign up, and receive ES parts, you are allowed access to all the software and to all the documentation. The controlled release process allows us to fix software bugs, and track closely each customer experience. By doing this careful release process, we improve the customer experience when the general release is announced. Over the last 5 releases we continue to fine tune the process, and review each release, and how it went, and what the general feeling was for silicon and software. If you just want to "kick the tires" and take a test drive, I understand. However, we feel that a general release of software and samples is not the best business practice if done without a rigid discipline. Feel free to sign up for access, however. http://www.xilinx.com/products/v6s6.htm AustinArticle: 139617
On 7 Apr., 06:20, rickman <gnu...@gmail.com> wrote: > On Apr 3, 7:02=A0pm, Mike Treseler <mtrese...@gmail.com> wrote: > > > > On Apr 3, 4:02 pm, gabor <ga...@alacron.com> wrote: > > >> Have you tried instantiation to make sure what you want to do > > >> is really possible and there isn't some other gotcha that > > >> keeps synthesis from coming up with your preferred solution? > > > I think this is quite likely. > > > Either there is some non-obvious kludge > > in the epic architecture, > > or synthesis missed an optimization. > > > Unless I were down to my last gate, > > I wouldn't spend time worrying about > > which one it is. > > This is a design that will be used repeatedly and will be used in > tight quarters. =A0So saving a LUT on every adder and counter can be > quite useful. =A0I found that a coding style difference saved 3 LUTs in > an 8 bit adder with overflow detection. =A0That's about a 30% savings. > In the long run I expect to save about 25% to 30% overall in the > design. =A0I think that is significant. > > Yes, what I am trying to do is possible. =A0It just seems like the tools > want to add an inefficiency one way or the other. =A0I wrote to Lattice > and their suggestion is avoid using the synthesis tool and to > instantiate my logic. =A0Hmmm. =A0Maybe Lattice shouldn't be my first > choice in FPGAs. Could you fix it by simple post-processing of the netlists from synthesis? But Maybe it's a feature to avoid packing or routing problems.Article: 139618
On Apr 7, 5:46=A0pm, "jsd" <jsd3...@yahoo.com> wrote: > When will Xilinx release V6 software and demo boards? =A0I have been look= ing > for more information on the web but cant find much. =A0The data sheet is > missing but I found a press release saying they are shipping parts? > > jsd =A0 the release is targetted JUNE so be prepared to wait til that, or much longer if Xilinx is repeating its history with new device introduction. before that the samples and software is available for EA only, and chances to get onto EA list are equal to ZERO AnttiArticle: 139619
Hi http://groups.google.com/group/antti-brain/files?hl=en with a delay this month again :( the time is flying only faster.. but there are some new FPGA board photos included.. AnttiArticle: 139620
Hi all, I am using a 48-bit accumulator reference design from the XtremeDSP for Virtex-4 User's Guide (UG073). The static timing analysis tool assigns very long clock to out time for the output of this block - 2.361 ns for the 10 speed grade in V4FX60. Looking at the datasheet this time is more in line with the clock to out time from M register to P output. However, the M register is not used in the design and the P-register is present... The time analyzer designates this time as Tdspdck_opp while in the datasheet there are Tdspcko_pp and Tdspcko_pm... The former is much lower than what is being reported by the analyzer, and the latter is slightly bigger... Could someone shed some light on this? Thanks, /MikhailArticle: 139621
"Mark McDougall" <markm@vl.com.au> wrote in message news:49da9eed@dnews.tpgi.com.au... > Jonathan Bromley wrote: > >> I guess we'll have to agree to differ, but I gave up serious use of >> schematics a decade ago and I don't miss them even a tiny little bit. > >>>> Not to mention problems with re-use, Modules designed using schematics are just as portable and re-useable as those using an HDL >>>>portability to other vendors, That's the real joke - unless you design using primitives - you mean you DO? You cannot transfer across vendors without massive rework using an HDL so that often quoted fact is a farce. Personally I have never had to - you mean you have? and >>>> version control software issues (diff anyone?). Not a problem. each module has it's own version called from the top level > >>>>> Serious PL work just isn't done in schematics. You must be living in cloud cuckoo land - fancy a big bet?Article: 139622
<jprovidenza@yahoo.com> wrote in message news:a6510994-3caf-4584-b8a0-61422f3831f3@d25g2000prn.googlegroups.com... On Apr 6, 9:03 am, "Dave Wilson" <d...@noaddress.net> wrote: > "Jonathan Bromley" <jonathan.brom...@MYCOMPANY.com> wrote in message > > news:4g4it4d9ah49jmotmo9btar8lmd8qoa3cm@4ax.com... > > > > > On Sun, 5 Apr 2009 21:55:21 +0200, "Xin Xiao" wrote: > > >>Thanks, but I have to do it with schematics..... > > > Oh dear. Why? > > > Basic Metalwork course, Lab 1: > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > You are given a piece of steel approximately > > 5cm x 5cm x 5cm. Your task is to construct > > a steel cylinder, of diameter 3cm and length > > 4cm, without using a lathe. Marks will be > > deducted for any evidence that you borrowed > > your friend's CNC milling machine. Extra > > credit is available for completing the task > > using tools made only from elk antlers. > > > -- > > Jonathan Bromley, Consultant > > > DOULOS - Developing Design Know-how > > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > > jonathan.brom...@MYCOMPANY.com > >http://www.MYCOMPANY.com > > > The contents of this message may contain personal views which > > are not the views of Doulos Ltd., unless specifically stated. > > ???? > If he was using Altera Quartus schematic then it would take less than 10 > seconds using the LPM_COUNTER wizard - about 100 times faster than using > crap VHDL. >>>>[sarcasm on] >>>>[An we don't need to waste any time on that simulation stuff, either >>>>[[sarcasm off] Oh yes we do! - don't you? >>>>[I don't know any reasonably sized companies that would hire a person >>>>[that wasn't >>>>[well versed in an HDL. I work for one >>>>[There's a reason - using an HDL is far more >>>>[productive, Disagree - I can design /compile /simulate faster than you >>>>portable, you are joking!!!!! Not without extensive rework >>>>[and re-usable. I reuse code all the time >>>>[AND... you can use off-the-shelf source code control systems with an >>>>[HDL. Don't need to >>>>[I haven't drawn a schematic (other than for spice) in years. I don't >>>>[miss schematics >>>>[at all. I truly feel sorry for you - life must be exceedingly boring!Article: 139623
On Tue, 7 Apr 2009 17:21:27 +0100 "Dave Wilson" <dave@noaddress.net> wrote: > [positively about schematic entry] Dave, you seem to be the only guy out here defending schematic entry. Therefore, obviously, you're not using the horribly crippled Xilinx schematic tool, which seems to crash more and more with each revision. If I may ask, what schematic tool are you using, and what did it run you? Can it handle structured port types to talk to VHDL? -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 139624
On Apr 7, 7:36=A0pm, Rob Gaddi <rga...@technologyhighland.com> wrote: > On Tue, 7 Apr 2009 17:21:27 +0100 > > "Dave Wilson" <d...@noaddress.net> wrote: > > [positively about schematic entry] > > Dave, you seem to be the only guy out here defending schematic entry. > Therefore, obviously, you're not using the horribly crippled Xilinx > schematic tool, which seems to crash more and more with each revision. > > If I may ask, what schematic tool are you using, and what did it run > you? =A0Can it handle structured port types to talk to VHDL? > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order HDL Designer .
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z