Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On Thu, 14 May 2009 15:05:17 -0700 (PDT), -jg <Jim.Granville@gmail.com> wrote: >On May 14, 9:20 pm, Mike Harrison <m...@whitewing.co.uk> wrote: >> What I'm looking at is the cheapest way to drive a large number (potentially hundreds) of >> distributed TFT (PSP) displays with local SDRAM and/or NAND flash storage for a few tens to hundreds >> of frames, with a relatively a low bandwidth network of some sort to update content in non-realtime, >> and switch the display between stored frames realtime. The aim is to minimise the cost per node as >> much as possible. > >Ah, so you need many slaves, and the smarts can be elsewhere. > >I found some info on TFT(PSP), [9MHz, 8+8+8 Colour] and it seems the >simplest solution would be a 32 bit wide SDRAM >and a CPLD, and 128MC should be plenty. > - I don't see you need a line-ram in a SDRAM playback scheme (tho the >Qimonda SDRAM data I had was poor ). One possible solution I considered was SDRAM using page-reads, one per displayed line. However the page size means it would need 2x 8-wide SDRAMS as the x16 device page size on a 64M SDRAM is only 256 bytes ( I've decided that the difference between 16 bit 5:6:5 and 24 bit display is negligible - content can be pre-dithered if necessary). However although this would work OK for reads, writes to SDRAM would be limited to the vertical blanking interval (12 lines), so the sending of data would need to be synced to this, and bandwidth would be limited - without a local buffer you'd need high peak bandwidth which would be idle most of the time. Having a couple of 512-pixel buffers (one for read, one for write) means data can be read and written much more freely, as you can do a page read from SDRAM to the buffer at, say, twice the pixel clock, leaving 50% of RAM bandwidth available for writes, and no sync constraints on write data - the only constraint is the rate of data transmission, which is easily regulated. It would also remove the 1 line/1 page constraint so RAM use could be more efficient, although wasting 32 out of 512 words may be worthwhile to simplify the control logic. Given a suitably fast network link, updates at full-frame rate would be possible, and the whole system becomes a lot more flexible.Article: 140501
On May 13, 10:13=A0pm, bigca...@gmail.com wrote: > Dear All: > > I am thinking about my system, the picture is here: > > http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/ > > I want to transfer the raw/processed image sensor data to USB 2.0 or > dpram. > > Two choices: > > 1. ADC -> DSP, this means parallel ADC, then DSP processed data -> > USB, FPGA works as a coprocessor, use FPGA's DSP (difficult), FPGA- > > >DPRAM > > 2. ADC -> FPGA, this means serial ADC or whatever, then FPGA<---- > EMIF---->DSP processed data, data feedbacked from DSP to FPGA -> USB, > DSP works as a coprocessor. > In choice 2, the USB could also connect from DSP but this will > accelerate processed data transfer, decelerate the raw data transfer. > > Other questions: > > I also need to store raw data, thus the data saving path will be > different: > Choice 1: the raw data will be from ADC -> DSP -> FLASH > Choice 2: the raw data will be from ADC -> FPGA -> FLASH (Is Flash > good for fast data saving, or use EEPROM instead?) > > It will meet the same question when I save processed data on board. > > The last question is FIFO vs. DPRAM, FIFO could be implemented in > FPGA, could DPRAM be implemented in FPGA? the DPRAM has more > flexibility for sure. > > Thanks! It would be easier to interface your ADC channel(s) to the FPGA. You could then capture the data in your FPGA and store the samples or frames to an external memory like SDRAM/ZBT SRAM (to offer a larger storage capacity than FIFO/DPRAM). It would be relatively easy to implement your ADC control in the FPGA. Then your FPGA would be connected to the EMIF_A, and the DSP would access the FPGA like an external "memory device". You can have a look at the Xilinx application note XAPP753: http://www.xilinx.com/support/documentation/application_notes/xapp753.pdf Your DSP would ideally have a dedicated bank of SDRAM, and also be connected to the Flash memory that would be used to store your DSP bootloader, FPGA bitstream and even your application. This would allow you to have a standalone system if required and it may also be possible to store some user data in Flash. However, I would recommend to use a microSD socket/Flash if you wish to store some of your data, or directly use the external memory devices attached to the DSP and the FPGA since they may be faster and give you better performance. You could use a USB chip directly interface to the DSP, and then transfer data fast. But you may not reach more than 20-40MB/s using a USB. If your application requires a faster throughput ot the host, you may have to consider PCI/PCI-64 or similar systems. Such solutions exist off the shelf from COTS hardware vendors. I would recommend that you have a look at the exisiting solutions before starting such a design. - Sebatsien www.sundance.comArticle: 140502
On Thu, 14 May 2009 16:02:00 -0700 (PDT), Andy <jonesandy@comcast.net> wrote: > >As others have pointed out, a Synchronously Deasserted Asynchronous >Reset (SDAR) still allows the system to reset without a clock, but the >system cannot resume without a clock (the latter of which is identical >to synchronous resets). Therefore be extra careful when applying Reset to your clock generator (e.g. Xilinx DCM) Don't ask me how I know this. - BrianArticle: 140503
Another problem is that I want to configure the FPGA through an SPI Flash. Could FPGA be configured successfully before the PC powers up and enumerates the device?Article: 140504
Hi, Antti wrote: > hi > > can not find in the datasheets, i need to know if the RAM blocks are > known 0 filled at power up or not. > Actel docs only talk about methods of init, but do not seem to mention > the power up value of the ram cells I would make a simple test : make a design that simply dumps the SRAM. But I guess that the cells are more or less random. There is no /RESET input to the SRAM cells, only to the buffers. Don't count on a particular value at power-up :-/ If they change the SiO2 process or foundry, you're stuck. > Antti yg -- http://ygdes.com / http://yasep.orgArticle: 140505
Hi I have a design with two clocks from a DCM. A clk0 and clk90 running at 350MHz (2.85ns period). I have some logic in my design that has a flip flop clocked using clk0 then into another flip flop clocked using clk90. This seems to work ok when I simulate it but when I run it through Synplify it tries to time it across the two flipflops to a 1/4 of the period. I guess its looking at the period between the two clock edges. Is there some constraint I need to set or is this just bad design practice? Cheers JonArticle: 140506
> Which device are you using and which IOs are you trying to use? I'm to use the Virtex-5 LXT/SXT PCI Expres board the AES-XLX-V5SXT- PCIE95-G circuit. There are 4 clock signals and I'm using following pins (according to the board documentation): sys_clk_p - E4 sys_clk_n - D4 sys_clk_p - D8 sys_clk_n - C8 > Please explain how you understand the problem as you mentioned above Besides the VHDL code, Xilinx ISE needs an additional file in a proprietary format (UCF). I think the problem is I don't know how to specify all the necessary constraints in the file (lack of experience with Xilinx). MRArticle: 140507
Thanks Everybody. I am basically a verification person and I always had a doubt if the way I am modeling the reset has any impact on the design (basically masks any bugs) ... but now I know ... Regards, On May 15, 3:30 pm, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Thu, 14 May 2009 16:02:00 -0700 (PDT), Andy <jonesa...@comcast.net> wrote: > > >As others have pointed out, a Synchronously Deasserted Asynchronous > >Reset (SDAR) still allows the system to reset without a clock, but the > >system cannot resume without a clock (the latter of which is identical > >to synchronous resets). > > Therefore be extra careful when applying Reset to your clock generator > (e.g. Xilinx DCM) > > Don't ask me how I know this. > > - BrianArticle: 140508
On 2009-05-14, Poojan Wagh <poojanwagh@gmail.com> wrote: > Just curious if anyone out there has any recommendations for FPGA > conferences: Which ones provide the most insight into FPGA design > (latest verification, design, methodologies/techniques)? Where have > you learned the most that you can apply to your job? I have been quite satisfied with FPL the two times I've been there. The keynote speakers have always been interesting and during the normal sessions you can always find something which seems interesting. There are also lots of opportunities to discuss interesting things with other attendees. However, I should warn you that I'm in academia and may have other views on whether a conference is good or not than you do. (I'm guessing that you are not in academia.) My advice would be to read some of the papers from FPL before you decide to go there. /AndreasArticle: 140509
>Another problem is that I want to configure the FPGA through an SPI >Flash. Could FPGA be configured successfully before the PC powers up >and enumerates the device? > We've done a number of PCIe designs and take the conservative approach of using parallel FLASH to insure the FPGA configures under the PCI spec reset time. However, we've found that to be too conservative as the PC goes through many reset cycles when it powers up. The BIOS will bring it out of reset and configure the bus then the a PC will go thru another reset cycle before the OS comes up. Since BW is a concern in your design, you'll want to make sure you have a DMA engine on your endpoint device and make sure its supports scatter gather as both Windows and Linux may only provide small memory ranges for where to stuff your data on the PC side. DMA is required because transfers originating on the PC side will be broken into single cycle accesses. To do bursting of data, the transfers will need to originate in the endpoint. mike.ives@plexus.comArticle: 140510
On May 11, 1:02=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > it will be only short clip in local TV (estonian, kanal-2) in the DIY > show, but was still funny to look into the camera with FPGA board in the > hands. Is there a way to see this clip for non-estonians? Thanks, TommyArticle: 140511
On May 6, 8:55=A0am, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > http://members.at.infoseek.co.jp/x1resource/xilinx/ip/mr16/mr16.html As brilliant as this may be, everything is in japaneese, the pdfs can't be accessed and the project appears completely unmaintained. Still, in the interest of gauging how hard it would be to compile for, I would like to see an overview of the ISA. TommyArticle: 140512
On May 15, 5:29=A0am, "maxascent" <maxasc...@yahoo.co.uk> wrote: > Hi > > I have a design with two clocks from a DCM. A clk0 and clk90 running at > 350MHz (2.85ns period). I have some logic in my design that has a flip fl= op > clocked using clk0 then into another flip flop clocked using clk90. This > seems to work ok when I simulate it but when I run it through Synplify it > tries to time it across the two flipflops to a 1/4 of the period. I guess > its looking at the period between the two clock edges. Is there some > constraint I need to set or is this just bad design practice? > > Cheers > > Jon Why do you think that Synplify is timing the path between the two paths incorrectly? Hint: it isn't. - NathanArticle: 140513
I'm not saying that Synplify is wrong but its not what I want. Basically I want to resynch the output of the flipflop clocked using clk0 to the clk90. Synplify is trying to time it to 1/4 of the period (about 0.7ns) which I dont want and it cant achieve either. JonArticle: 140514
Hi all, I have a problem with Coolrunner II pld (http://www.xilinx.com/ products/devkits/SK-CRII-L-G.htm). I have written a program similar to the project counter given in the Xilinx handbook example. Full code is available on http://webs.hogent.be/~a00027gd/teller.txt In ISE the code compiles correctly except for one warning message. The handbook example gives the same error message so this cannot be the problem. I used PACE to assign pins and created the .jed-file as usual Programming the device with this .jed results in a dead board ? If I program with the .jed from the handbook example it runs fine ? I spend a couple of days on it and cannot find anything wrong. Could the problem be board specific (eg timing constraints, ...) or anything else In fact the basic question is: how can I bring the dead board to life with this code ? Thanks a lot for help GertArticle: 140515
On May 15, 10:53=A0am, "maxascent" <maxasc...@yahoo.co.uk> wrote: > I'm not saying that Synplify is wrong but its not what I want. Basically = I > want to resynch the output of the flipflop clocked using clk0 to the clk9= 0. > Synplify is trying to time it to 1/4 of the period (about 0.7ns) which I > dont want and it cant achieve either. > > Jon I'm still not sure why you say you don't want that. Synplify is doing exactly what you're telling it to do. The delay from the rising edge of clk0 to the rising edge of clk90 is 1/4 of a period. If you have two flip-flops clocked with those two clocks, you only have 1/4 of a period to make the transfer. What do you expect Synplify to do? There are a couple things you can do to change this: * If your clock is 50/50 duty cycle (or you use a DCM to make it one), you can transfer from the rising edge of clk0 to the falling edge of clk0 (1/2 period) to the rising edge of clk90 (3/4 period). * You can use a very small (say 4 element) asynchronous FIFO to transfer from one domain to the other. There's no possibility of overflow or underflow because the aggregate data rate is equal on both sides. * You can use a multicycle path constraint to transfer the data in 1.25 clocks instead of 0.25 clocks. I'd recommend against this, though, as it's a reasonably advanced technique and can get you in trouble if your timing analysis tool doesn't appropriately consider all PVT corners. More importantly, your RTL simulation will no longer match your produced gates. - NathanArticle: 140516
DH;476369 Wrote: > Hi, > > I'm trying to find an open source processor as a basis for a research, > preferably it is in VHDL and implements a 5-stage RISC pipeline with > bypassing (exceptions are not a concern), of course if you know of any > processor with a clean 5-stage pipeline with bypassing, please let me > know. It would be awesome if it implements the MIPS ISA. > > I've tried the open cores website, and have looked at 2 MIPS ISA > implementations: Plasma and miniMIPS. > Problem is Plasma does not deal with bypassing and is not a 5-stage > pipeline, and miniMIPS is rather weird, it process instructions every > other cycle, so it would process, then it would pause everything on > the next cycle. > > So I'm wondering maybe there would be someone out there on the > internets that know about this, please help me out :) Thanks! > > Regards, > David. Have you considered LEON. I used for some self learing projects: Improving The LEON2-XST PCI Interface 'VHDL, verilog, design, verification, scripts, ...' (http://bknpk.no-ip.biz/LEON/leon_1.html) I2C master connected and tested with LEON Processor 'VHDL, verilog, design, verification, scripts, ...' (http://bknpk.no-ip.biz/I2C/leon_2.html) ... -- pini_1234 ------------------------------------------------------------------------ pini_1234's Profile: http://www.fpgacentral.com/group/member.php?userid=86 View this thread: http://www.fpgacentral.com/group/showthread.php?t=90062Article: 140517
-jg wrote: > Perhaps in the downturn, ANY demand is good demand ! ;) > > Certainly 5V is not going away as many predicted, and in many sectors > is making > a comeback. (but perhaps not at the cutting edge of FPGA) > > -jg My designs are NOT, by any means, cutting edge. I have just moved up from 10 and 16 MHz clocks with the 5V Spartans to 40 MHz with the Spartan 2E. And I am using the 50 K gate size of that part, so no big FPGAs here. but, these do something I would never attempt with SSI/MSI chips. JonArticle: 140518
Poojan Wagh wrote:
> Just curious if anyone out there has any recommendations for FPGA
> conferences: Which ones provide the most insight into FPGA design
> (latest verification, design, methodologies/techniques)? Where have
> you learned the most that you can apply to your job?
Useful FPGA design ideas are available on the newsgroup archives
and on google. Real learning occurs by trial and error using
editors, simulators and vendor tools. The surviving conferences
are focused on academia and sales rather than practical design.
-- Mike Treseler
Article: 140519Hi, I am new to FPGA Programming stuff. i am looking for programming details of the FPGA. What portion of the jbc file actually goes in to the FPGA via JTAG. There are Data section, code section, Symbol Section, etc . Is it the whole contensts of the file goes to FPGA (Just like we program the EEPROM Boot Rom). Can you please throw me some light here Thank you -- timtim ------------------------------------------------------------------------ timtim's Profile: http://www.fpgacentral.com/group/member.php?userid=87 View this thread: http://www.fpgacentral.com/group/showthread.php?t=90145Article: 140520
"gert1999" <ggddbb@gmail.com> wrote in message news:88ff57c2-b9e8-4a34-8e56-6a7afd698641@e20g2000vbc.googlegroups.com... > Hi all, > > I have a problem with Coolrunner II pld (http://www.xilinx.com/ > products/devkits/SK-CRII-L-G.htm). > I have written a program similar to the project counter given in the > Xilinx handbook example. > Full code is available on http://webs.hogent.be/~a00027gd/teller.txt > In ISE the code compiles correctly except for one warning message. > The handbook example gives the same error message so this cannot be > the problem. I used PACE to assign pins and created the .jed-file as > usual I didn't look in any detail. How does it look in simulation? Is it counting? If it is, check the UCF for pin assignments, pull-up/-down attributes. Look especially at the reset line. If it doesn't count in simulation, check the reset sense, 1 or 0. Check the clock. ... ... ...Article: 140521
"MikeWhy" <boat042-nospam@yahoo.com> wrote in message news:NqkPl.26630$c45.6895@nlpi065.nbdc.sbc.com... > "gert1999" <ggddbb@gmail.com> wrote in message > news:88ff57c2-b9e8-4a34-8e56-6a7afd698641@e20g2000vbc.googlegroups.com... >> Hi all, >> >> I have a problem with Coolrunner II pld (http://www.xilinx.com/ >> products/devkits/SK-CRII-L-G.htm). >> I have written a program similar to the project counter given in the >> Xilinx handbook example. >> Full code is available on http://webs.hogent.be/~a00027gd/teller.txt >> In ISE the code compiles correctly except for one warning message. >> The handbook example gives the same error message so this cannot be >> the problem. I used PACE to assign pins and created the .jed-file as >> usual > > I didn't look in any detail. How does it look in simulation? Is it > counting? If it is, check the UCF for pin assignments, pull-up/-down > attributes. Look especially at the reset line. If it doesn't count in > simulation, check the reset sense, 1 or 0. Check the clock. ... ... ... [PS] Check the digit select, common cathode or anode on the 7-segment. Is it driven correctly? I didn't see that in the ports.Article: 140522
OK. This has now been resolved for me. To my understanding, SysGen doesn't include a mex interface for the c+ + API of LockableSharedMemory class. I was about to start writing my own when it occurred to me that I shouldn't. So I opted to redesign everything using unprotected shared memories and implement my own MUTEX using To/From Register objects. I poll on these at both sides (PC and FPGA) and all seems fine now. I don't know if performance is being hampered in anyway but all in all this meets my requirements. -MArticle: 140523
On May 14, 10:15=A0pm, r.frido...@gmx.de wrote: > In ISE 11.1 the license model has changed. > > 1.The restricted license model is in conflict with a long time > availability. > 2.It is a problem for users using reconfiguration. > 3.FPGAS are like hardware. Now with limited access. > > This license model makes no sence for XILINX and > =A0 =A0makes it more complicate and uncertain for there users. > > 1.The restricted license model is in conflict with a long time > availability. > > Until this ISE software was easy to install on different computers. > There was no admin account nessesary. > Run more than one installation on different computers was no problem. > After 15 years you could quite shure this works. > > Now when you change your computer you need a new license. > I need design's which need ISE 4. > In 10 years I will have design which need ISE 11. And then? > > 2. > This is hard for reconfiguration users. > They have systems that need design software, all the time of the > project livetime. > May be you must make a design modifikation(or new design) every week. > These hardcore user lost: > =A0The possibility to run more than one instance on different computers. > =A0 =A0This helps in more than one way. > =A0 =A0 =A0 =A01. Finding out bitstream patterns for partioal reconfigura= tion. > =A0 =A0 =A0 =A02. Find a good routing solution very quick. > > 3.FPGAS are like hardware. Now with limited access. > =A0The users trust on FPGA. > =A0But a strict license model makes the access to design software > uncertain. Xilinx has switched to using FlexLM for licensing as of ISE 11.1. I have been using multiple other software packages that use FlexLM for years, so I have some experience with the issues that it can cause. FlexLM is more restrictive than just giving you an activation ID, and I expect that they will be getting a lot of calls from customers about this. However, after evaluating how Xilinx has used FlexLM, I think that some of your issues above have been addressed in a reasonable fashion, and I think that some of their licensing terms have been made more favorable for the customer. First, the FlexLM license files that I have received for Xilinx software do not expire with respect to your right to use the software. They give you one year of updates, but the license file allows you to use the software released up to that point forever. Here are a few lines from one of my node locked license files: # This license is valid for permanent ( 0 days ) from Sun May 10 15:48:08 GMT+00:00 2009 INCREMENT System_Edition xilinxd 2010.04 permanent uncounted \ The 2010.04 means that I can run any version of ISE System_Edition that is release up to (through?) April of 2010. The permanent means that I can continue to use that forever. The uncounted means that I can run as many instances as it can handle on the machine that it is node locked to. FlexLM license files for IP cores may expire depending on the core. If they do expire, the permanent from above would be replaced with the expiration date. You also expressed concern about not being able to move the license to a new machine. I have had to do this several times in the past, and it was always a pain. If I was upgrading because the computer or the dongle failed, it also meant that I could not use the software for several days. In the past, I had to call the software vendor and explain why I wanted or needed to get a new license. If I was replacing a dongle, they would send me a new dongle with a temporary license file. When they received my old dongle back, I would get a new license file. Xilinx has set up their license web site so that the customer can regenerate new license files to rehost their software on a new machine themselves. You can do this at least three times before you need to talk to support by clicking on an online affidavit stating that you are generating the new license file to replace the old file, and that you will destroy the old license file. You can also choose what to lock the license to: a Macrovision dongle, an Ethernet MAC ID, or a hard drive serial number. I like to lock to Ethernet MAC IDs because of the ease of moving Ethernet to a new computer. While Xilinx states that they do not support it, I currently have USB Ethernet adapters that I use as dongles with other FlexLM licensed software. I think that you also are concerned that you lose the ability to run more than one installation on different computers at the same time for those tough place and route jobs. This is one of the areas that I believe that Xilinx has made the license more permissive. Under certain circumstances, it only takes one license to run multiple iterations of a job on multiple machines. I think that MPPR and ExploreAhead both allow this for Linux. I don't remember if the Windows version does, and it is Friday afternoon so I am not going to look it up now. I think that this used to require a license per machine. Node locked licenses will allow you to run as many iterations on a machine as it can handle, so if you have a multiprocessor computer with lots of memory, you are free to run multiple iterations at the same time. And finally, while I am a Xilinx Alliance Partner, and a Xilinx Authorized Training Provider, I do not speak for them. This is just my understanding of these issues. Regards, John McCaskill www.FasterTechnology.comArticle: 140524
"maxascent" <maxascent@yahoo.co.uk> wrote in message news:39-dnQRXb-mOMZDXnZ2dnUVZ_o2dnZ2d@giganews.com... > I'm not saying that Synplify is wrong but its not what I want. Basically I > want to resynch the output of the flipflop clocked using clk0 to the > clk90. > Synplify is trying to time it to 1/4 of the period (about 0.7ns) which I > dont want and it cant achieve either. > > Jon > To what time do you want to time it? Syms.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z