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On May 18, 8:36=A0pm, Andy Peters <goo...@latke.net> wrote: > On May 15, 4:00=A0pm, John McCaskill <jhmccask...@gmail.com> wrote: > > > Xilinx has switched to using FlexLM for licensing as of ISE 11.1. =A0I > > have been using multiple other software packages that use FlexLM for > > years, so I have some experience with the issues that it can cause. > > FlexLM is more restrictive than just giving you an activation ID, and > > I expect that they will be getting a lot of calls from customers about > > this. =A0However, after evaluating how Xilinx has used FlexLM, I think > > that some of your issues above have been addressed in a reasonable > > fashion, and I think that some of their licensing terms have been made > > more favorable for the customer. > > I've dealt with FlexLm in the past, and I've learned to curse its very > existence when the license server, typically in an inaccessible > location, goes down. This always happened on a weekend with a looming > Monday-morning deadline. > > But all that aside, after all these years, Xilinx still doesn't get > it. We use their software to develop applications FOR THEIR CHIPS. > There is no other use for it. Locking it down and otherwise making it > difficult to install and use is at cross purposes with Xilinx' > objectives: selling chips. > > Now I understand that there is a real cost for technical support. What > Xilinx needs to do is to uncouple tech support from the cost of the > tools. To wit: > > a) If you are a hobbyist and you want to play with a starter kit or > whatever, use the tools and use the various WWW resources for support. > You don't get a tech-support account and Xilinx won't answer your > phone calls. > > b) The professional user should be able to choose between per-incident > and blanket yearly tech-support options. Perhaps two tiers of support > should be available -- initial WebCase, and direct-to-smart-people > telephone support. The point is that if we are paying directly for the > support, we expect REAL results and not the usual web-case runarounds. > > c) In either case, any user (from the hobbyist to the pro) should be > able to report bugs and get updates on their resolutions. Xilinx > should not cut off a source of bug reports simply because the users > aren't paying for support. > > As it is now, users who buy ISE/EDK etc spend a lot of money and don't > get any real support, and this latest licensing nonsense is a kick in > the teeth. > > -a super yes! bravo for bringing out the IT, from the Xilinx latest move (a real bady move..) I have suggested the DROP BUG hotline email address before sometime people find bugs that ar not important for them but could be for Xilinx and others, but the webcase ist too much trouble in such cases and there is no way to submit without it AnttiArticle: 140576
Hi all
I am implementing the I2C Slave and I am using the I2C clock SCL for
detecting the start and stop condition . I am detecting the start and
stop successfully in simulation but i am not able to do the same in
the post synthesis scenario. More so I am getting a setup time
violation for the same in the timing analysis . I am running the I2C
at a very slow speed of 100KHz.
The code is below
process (SDA_IN, START_RST,rst)
begin
if rst ='1' then
STARTOP <='0';
-- elsif (START_RST = '1') then
-- STARTOP <= '0';
elsif (SDA_IN'event and SDA_IN = '0') then
STARTOP <= scl;
end if;
end process;
------------------------------------------------------------------------------
-- stop condition detection
process (RST, SCL, SDA_IN, STARTOP)
begin
if RST = '1' or SCL = '0' or STARTOP='1' then
STOPOP <= '0';
elsif SDA_IN = '1' and SDA_IN'event then
if SCL = '1' then
STOPOP <= '1';
end if ;
end if;
end process;
Can any one give me a reliable way to detect the start and stop
condition that the synthesis tool doesnot give any setup time
violation. I am not using a high clock for sampling as the requirement
is to use the SCL only. May be to save board resourse and space.
Help will be appreciated. I am using Altera max II CPLD and the
synthesis tool is quartus 9.0
Thanks
Vipul
Article: 140577On May 19, 4:04=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > Hi > > eh sometimes i just wanna shine, i guess :) > but well it was real nice seeing AVR code loaded and executed from SD > card > by bootstrap code in the 128 byte FlashROM of Actel FPGA > > the complete SD card bootstrap code takes 55 AVR instructions (from 64 > available) > ah, the SPI is FULL software bit bang, there is no SD related hardware > peripherals. > > well the AVR core in the FPGA is little modified > 1 ROM is mapped to RAM space both read write > 2 SBI/CBI are modified to be able to write Carry to IO port :) > > without [2] the code would be 56 instructions but still fit. > > this code bootstraps from file copied to FAT file system, using NoFAT > (tm) method, > SDHC is not supported > > I guess, without NoFAT, it might be possible to add SDHC support too, > but then initial > bootstrap would need to be in sector 0, what is possible but requires > special SD card > formatting tool > > Antti > PS and yes, this just one bootstrap for the FPGA-AVR module with Actel > PA3 Hi Antti So, does this support Pgm-Select loading, and perhaps even a more run-time dymamic loading ? Seems like you have some spare space, so it's not finished yet ;) -jgArticle: 140578
On May 15, 4:42=A0pm, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: # # I bet the flexLM will not at all work or be available in 10 years from # now, so chances using 11.1 in that time are nil Some vendors are able to run in Eval, or some restricted modes, in "FlexLM License no found" instances, so it would be relatively EASY for Xilinx to allow this. ie for product maintenance, allow the system to load and run, without the license. If they must, it could run at a deliberately slow speed (because in 10 years time, your new PC will be faster anyway...), or they could simply flip to Maintenance mode, after the useful life (perhaps 5 years for FPGA tools ? ) Annoyed customers do no one any good. -jgArticle: 140579
Andy Peters <google@latke.net> wrote: < I've dealt with FlexLm in the past, and I've learned to curse its very < existence when the license server, typically in an inaccessible < location, goes down. This always happened on a weekend with a looming < Monday-morning deadline. The one I remember occurs when the program or machine crash with a licence outstanding. There is no release of the license, and it continues to count against the number available. That was some years ago, so maybe it has been fixed by now. < But all that aside, after all these years, Xilinx still doesn't get < it. We use their software to develop applications FOR THEIR CHIPS. < There is no other use for it. Locking it down and otherwise making it < difficult to install and use is at cross purposes with Xilinx' < objectives: selling chips. Well, I for one appreciate the Xilinx (and other vendors) free versions of the tools. You don't get everything, but enough for a large fraction of the actual cases. I am not so sure which ones will run in the free mode when a license is not available. -- glenArticle: 140580
On Mon, 18 May 2009 10:39:26 -0700 (PDT), Andy Peters <google@latke.net> wrote: >On May 15, 3:30 am, Brian Drummond <brian_drumm...@btconnect.com> >wrote: >> On Thu, 14 May 2009 16:02:00 -0700 (PDT), Andy <jonesa...@comcast.net> wrote: >> >> >As others have pointed out, a Synchronously Deasserted Asynchronous >> >Reset (SDAR) still allows the system to reset without a clock, but the >> >system cannot resume without a clock (the latter of which is identical >> >to synchronous resets). >> >> Therefore be extra careful when applying Reset to your clock generator >> (e.g. Xilinx DCM) >> >> Don't ask me how I know this. > >I would imagine that you learned that lesson the same way I did ... > >-a Is it still ten minutes to five? - BrianArticle: 140581
Hi, thanks to everyone that replied to this post! I really appreciate it. To Antti: Thanks, the YARI processor looks like a good processor. To Jon: Thanks, I will look at it when I run out of VHDL options :) To Chris: The requirement is because I have done my analysis based on a 5 stage pipelined MIPS (by hand...), so I'm trying not to have to redo it for a different instruction set, and I understand its pipeline structure quite well from texts like Hennessy & Patterson. It is quite an arbitrary choice. Also I think I found a tool (CoWare) that will make life a lot simpler :) To pini_1234 & MikeWhy: Thanks. I looked at LEON before, but was turned off by the relatively complex project organisation (says about 90 files on wiki), it is certainly very good vehicle for experimentation if I have the time :) Update: After some discussion at school, I'm going to use the CoWare processor designer at school to make my processor now, it provides a reference 5 stage pipelined RISC core with bypassing done already, it's not MIPS, but there's compiler/assembler/ linker available. The best thing about this tool (though may be hard to do, we'll see) is that you can use it to generate the tool chain along with the processor RTL code. I will fall back to good old VHDL if this tool doesn't deliver, thanks to everyone that replied to this post!Article: 140582
You might want to take a look on a work I did once on I2c. I2C master connected and tested with LEON Processor This design uses the open core's I2C master. The core's CPU interface is modified from WISHBONE to AMBA/APB. The latter is done in order to test the core and its new APB interface with LEON processor. LEON is written in VHDL therefor the core's VHDL RTL design is tested. ... 'VHDL, verilog, design, verification, scripts, ...' (http://bknpk.no-ip.biz/I2C/leon_2.html) -- pini_1234 ------------------------------------------------------------------------ pini_1234's Profile: http://www.fpgacentral.com/group/member.php?userid=86 View this thread: http://www.fpgacentral.com/group/showthread.php?t=90219Article: 140583
glen herrmannsfeldt wrote: > The one I remember occurs when the program or machine crash with > a licence outstanding. There is no release of the license, and it > continues to count against the number available. That was some years > ago, so maybe it has been fixed by now. This can be fixed with "lmutil lmremove" command, google for the command or read the lmutil help text. --KimArticle: 140584
On May 19, 1:01=A0am, -jg <Jim.Granvi...@gmail.com> wrote: > On May 19, 4:04=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > Hi > > > eh sometimes i just wanna shine, i guess :) > > but well it was real nice seeing AVR code loaded and executed from SD > > card > > by bootstrap code in the 128 byte FlashROM of Actel FPGA > > > the complete SD card bootstrap code takes 55 AVR instructions (from 64 > > available) > > ah, the SPI is FULL software bit bang, there is no SD related hardware > > peripherals. > > > well the AVR core in the FPGA is little modified > > 1 ROM is mapped to RAM space both read write > > 2 SBI/CBI are modified to be able to write Carry to IO port :) > > > without [2] the code would be 56 instructions but still fit. > > > this code bootstraps from file copied to FAT file system, using NoFAT > > (tm) method, > > SDHC is not supported > > > I guess, without NoFAT, it might be possible to add SDHC support too, > > but then initial > > bootstrap would need to be in sector 0, what is possible but requires > > special SD card > > formatting tool > > > Antti > > PS and yes, this just one bootstrap for the FPGA-AVR module with Actel > > PA3 > > Hi Antti > So, does this support Pgm-Select loading, and perhaps even a more > run-time dymamic loading ? > > Seems like you have some spare space, so it's not finished yet ;) > > -jg Hi Jim the A3P060-AVR-FPGAMCU has 1Kbyte instruction ROM (RAM) directly read writeable so it could load half of the ROM from SD card sector at about 500K sec/second speed executing 500 different dynamically loaded routines per second PA3 is flash based and can not change its config so it is pretty much fixed setup Antti PS I forgot to mentio the 55 instr boostrap supports microSD cards, not only SD cards, SD cards are easier to support as SD spec says 2.1m thick cards should support CMD1, while microSD cards do not.Article: 140585
Today, Sigasi proudly announces the Public Beta program for Sigasi HDT, an Intelligent Development Environment (IDE) for VHDL (http:// www.sigasi.com/publicbeta). Sigasi HDT (Hardware Development Toolkit) is a powerful VHDL development tool that assists designers in reading, writing and modifying VHDL more accurately and faster. It differs from other development tools in that it contains an ultra-fast VHDL parser and compiler that runs transparently in the background (http:// www.sigasi.com/product). Through the Public Beta program, VHDL designers join a community that takes advantage of modern development techniques. To participate in the program, please visit http://www.sigasi.com/start.Article: 140586
Hi everybody, I use a script written a long time ago to play with the JTAG interface of a custom-made circuit (in FPGA). The JTAG interface is soft (i.e not the Altera's one but implemented using FPGA's logic). In the past I used the JAM/STAPL player and every thing was ok. Later I bought an Altera USB-Blaster cable. I was surprised to discover that the JAM player didn't support it. After some investigations I found quartus_jli.exe, which can play them on the new cable. The issue is that it seems that it doesn't support the FREQUENCY command. The problem is that my custom-made JTAG interface is very slow. Is there any other command or method to set the JTAG frequency? CheersArticle: 140587
On May 18, 10:47 pm, Kim Enkovaara <kim.enkova...@iki.fi> wrote: > glen herrmannsfeldt wrote: > > The one I remember occurs when the program or machine crash with > > a licence outstanding. There is no release of the license, and it > > continues to count against the number available. That was some years > > ago, so maybe it has been fixed by now. > > This can be fixed with "lmutil lmremove" command, google for the > command or read the lmutil help text. > > --Kim That command works only if you have administrative access on the license server. The situation Glen remembers still exists. ALArticle: 140588
Flexlm has a timeout where the server takes back a license that is not being actively used. Despite many tech support visits we never got it working and if the west coast left their blasted system on then us in Europe had to irritate our IS people to type "lmutil lmremove". These days we are running XILINX builds over night! ColinArticle: 140589
Hi, I'm trying to develop a code for implementation of simple MAC operation. I have almost finished with it. While doing this, i've used verilog memory and initialised it with the input i.e. array of integers. But i've done all these things in design block itself. But i need to give the inputs from outside the design block either from another module or from some file. For this purpose i can use $readmemh or $readmemb. But since this is not synthesizable, i can't proceed in this way. Is there any alternative? Pls guide me, how can i proceed...Article: 140590
Hi, I am using a small bootloader to boot a webserver application from spi flash. The trouble is I don't know how to load the MFS file directly into spi flash. iMPACT does not have an option to program an mfs file. The only way I can think of is to use XMD "dow" command to get the MFS file into DDR RAM. Then copy from DDR RAM into flash with coding. Though this method is not very practical. Is there a way to program the MFS file directly into spi flash? Thanks hvoArticle: 140591
On May 18, 9:48=A0am, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > I am starting to think the problem is the use of an enumerated value > rather than a string constant or a numerical constant. =A0I changed it > to an integer and it still does not work when using a constant name. > But if an integer value is used, it works ok. =A0It would seem that the > generic input function in XST does not work with symbols, only > values. Just in case it hasn't been considered: In the XST user guide for 10.1 on page 338 to 340 the use of -generics is mentioned. -- SvennArticle: 140592
On May 6, 10:39=A0pm, Svenn Are Bjerkem <svenn.bjer...@googlemail.com>
wrote:
> How would the generics setting be done using xflow from a Makefile?
Place a line in the .opt file ParamFile part:
"-generics {generic=3Dvalue}";
--
Svenn
Article: 140593How can I setup for running modelsim? Aiken On May 19, 6:33=A0am, philippe.f...@gmail.com wrote: > Today, Sigasi proudly announces the Public Beta program for Sigasi > HDT, an Intelligent Development Environment (IDE) for VHDL (http://www.si= gasi.com/publicbeta). > > Sigasi HDT (Hardware Development Toolkit) is a powerful VHDL > development tool that assists designers in reading, writing and > modifying VHDL more accurately and faster. It differs from other > development tools in that it contains an ultra-fast VHDL parser and > compiler that runs transparently in the background (http://www.sigasi.com= /product). > > Through the Public Beta program, VHDL designers join a community that > takes advantage of modern development techniques. To participate in > the program, please visithttp://www.sigasi.com/start.Article: 140594
Dear Vipul, Seems like you are always going to get some sort of timing issue since the rst signal and the SDA_IN signal are async. Propagating the STARTOP signal forward to the STOPOP reset circuitry also seems like a bad idea for some reason I can't quite articulate, except for an idea that the start and stop signals should be symetrical. If you have a system clock, I would suggest that you use registers at your SDA and SCL inputs right at the IOs. Then use old values of SDA and SCL to calculate your START and STOP signals: start_stop_proc:process(clk) begin if(clk'event and clk='1')then STARTOP<='0'; STOPOP<='0'; SDA_1<=SDA_IN; SDA_2<=SDA_1; SCL_1<=SCL_IN; if( SDA_1='0' and SDA_2='1' and SCL_1='1')then STARTOP<='1'; end if; if( SDA_1='1' and SDA_2='0' and SCL_1='1')then STOPOP<='1'; end if; end if; end process; This should be very clean as long as your system clock and timing is OK. And it give clean oneshot reset signals for your address and data registers. Now if you are trying to run this from the SCL clock, perhaps just taking the rst out of your process may work, or putting it in the synchonous part of the block may work, and clean up the code so that the both signals look symetrical: start_proc:process(SDA_IN) begin if(SDA_IN'event and SDA_IN='0')then if(rst='1')then STARTOP<='0'; elsif(scl='1')then STARTOP<='1'; else STARTOP<='0'; end if; end if; end process; stop_proc:process(SDA_IN) begin if(SDA_IN'event and SDA_IN='1')then if(rst='1')then STOPOP<='0'; elsif(scl='1')then STOPOP<='1'; else STOPOP<='0'; end if; end if; end process; Then these signals need to be synched with scl clock signal before you start messing with your data registers. And you have to look for their edges since the SDA signal can drop and not come up if it's sending a zero datum. Using a system clock is a lot easier. I haven't ever done a I2C slave so you might get better answers elsewhere. Good luck. Brad Smallridge AiVision "VIPS" <thevipulsinha@gmail.com> wrote in message news:35bbb41b-ce32-4cb6-868e-a459b10d05a7@s28g2000vbp.googlegroups.com... > Hi all > > I am implementing the I2C Slave and I am using the I2C clock SCL for > detecting the start and stop condition . I am detecting the start and > stop successfully in simulation but i am not able to do the same in > the post synthesis scenario. More so I am getting a setup time > violation for the same in the timing analysis . I am running the I2C > at a very slow speed of 100KHz. > > The code is below > > process (SDA_IN, START_RST,rst) > begin > if rst ='1' then > STARTOP <='0'; > -- elsif (START_RST = '1') then > -- STARTOP <= '0'; > elsif (SDA_IN'event and SDA_IN = '0') then > STARTOP <= scl; > end if; > end process; > ------------------------------------------------------------------------------ > -- stop condition detection > process (RST, SCL, SDA_IN, STARTOP) > begin > if RST = '1' or SCL = '0' or STARTOP='1' then > STOPOP <= '0'; > elsif SDA_IN = '1' and SDA_IN'event then > if SCL = '1' then > STOPOP <= '1'; > end if ; > > end if; > end process; > > Can any one give me a reliable way to detect the start and stop > condition that the synthesis tool doesnot give any setup time > violation. I am not using a high clock for sampling as the requirement > is to use the SCL only. May be to save board resourse and space. > > Help will be appreciated. I am using Altera max II CPLD and the > synthesis tool is quartus 9.0 > > Thanks > > VipulArticle: 140595
On May 19, 8:23 pm, Aiken <aikenp...@gmail.com> wrote: > How can I setup for running modelsim? > > Aiken Hi Aiken, To set up external tools, please check the user manual: "help->help contents" and then "Sigasi HDT -> User Manual -> External Tools" I suggest further support requests can be handled on the Sigasi website, in order not to overload this list with off-topic questions: http://www.sigasi.com/userforum kind regards PhilippeArticle: 140596
philippe.faes@gmail.com wrote:
> On May 19, 8:23 pm, Aiken <aikenp...@gmail.com> wrote:
>> How can I setup for running modelsim?
>>
>> Aiken
>
> Hi Aiken,
>
> To set up external tools, please check the user manual: "help->help
> contents" and then "Sigasi HDT -> User Manual -> External Tools"
The editor does seem to cover syntax checking without needing vcom.
-- Mike Treseler
Article: 140597> philippe.faes@gmail.com wrote: > >> On May 19, 8:23 pm, Aiken <aikenp...@gmail.com> wrote: >> >>> How can I setup for running modelsim? >>> >>> Aiken >>> >> Hi Aiken, >> >> To set up external tools, please check the user manual: "help->help >> contents" and then "Sigasi HDT -> User Manual -> External Tools" >> > The editor does seem to cover syntax checking without needing vcom. > > -- Mike Treseler > That's because they use their own VHDL front end. ---Matthew HicksArticle: 140598
Hi,
I have to use the BSCAN_SPARTAN3 (or BSCAN_VIRTEX???) in my design with both
capture and update functions.
Unfortunately these components do not provide the direct copy of the TCK
signal, which makes implementation of the state machine for my own chain
"a little" difficult (instead less functional DRCKx signals are provided).
Particularly: the DRCKx does not work when CAPTURE or UPDATE are active,
so I had to service them as asynchronous sets/resets.
Finally I have written and tested the following implementation (i use
the 18-bit data register, BTW - either BSCAN... or XPCU cable, or urJTAG
didn't work correctly for 17-bit long register, however I had no time to
isolate the problem):
PUBLIC DOMAIN code:
BSCAN_SPARTAN3_1 : BSCAN_SPARTAN3
port map (
CAPTURE => jt_CAPTURE,
DRCK1 => jt_DRCK1,
DRCK2 => jt_DRCK2,
RESET => jt_RESET,
SEL1 => jt_SEL1,
SEL2 => jt_SEL2,
SHIFT => jt_SHIFT,
TDI => jt_TDI,
UPDATE => jt_UPDATE,
TDO1 => jt_TDO1,
TDO2 => jt_TDO2);
-- Load and shift data
p1 : process (dr_cap, jt_capture, jt_drck1)
begin -- process
if jt_capture = '1' then
dr <= captured_data; -- I do not use SEL1 here
-- so data are captured also when USER2
-- is active! However it doesn't cause
-- any problem
elsif jt_drck1'event and jt_drck1 = '1' then
-- Shift the register
dr(17) <= jt_tdi;
for i in 0 to 16 loop
dr(i) <= dr(i+1);
end loop; -- i
end if;
end process p1;
-- drive TDO
-- The implementation is a little weird, however it
-- was the only way to send correctly the LSB
p2 : process (dr, jt_drck1, jt_shift)
begin -- process
if jt_shift = '0' then
jt_TDO1 <= dr(0);
elsif jt_drck1'event and jt_drck1 = '1' then
jt_TDO1 <= dr(1);
end if;
end process p2;
-- Update the internal data with received DR
p3 : process(jt_update)
begin -- process
if jt_update'event and jt_update = '1' then
if jt_sel1 = '1' then
my_writeable_data <= dr;
end if;
end if;
end process p3;
Certainly the above code does not include any synchronization elements,
needed to pass data between the JTAG clock domain and my system clock
domain.
I will appreciate any suggestions related to the possible problems or
improvements related to the above code. I've tested it, but I may have
missed something.
--
HTH & TIA & Regards,
Wojtek
PS.
I have also tried to collect some informations about the BSCAN_xxxx
components, as the description in Libraries Guide is very sparse.
1. http://www.holmea.demon.co.uk/Frac3/Main.htm
This page suggests, that using of BSCAN_SPARTAN3 may not be so easy, as
one could hope... And it was true... Unfortunately the author doesn't
use CAPTURE functionality
2. http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/spartan3e_hdl.pdf
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/spartan3_hdl.pdf
(Too) short description of the BSCAN_SPARTAN3. Interesting, that the
description of the DRCKx behaviour does not agree with the timing shown
in [4]. Well, meybe because [4] describes BSCAN_VIRTEX and
BSCAN_SPARTAN2?
3. http://www.xilinx.com/support/documentation/application_notes/xapp139.pdf
http://www.xilinx.com/support/documentation/application_notes/xapp188.pdf
Both application notes do not provide the sample HDL code (only
instantiation templates) but contain a nice "Figure 4" - which shows
schematic diagram of the implementation.
Well, may be I should just write the HDL (VHDL or Verilog) code
describing this circuit? However they use 2 shift registers, while my
implementation uses only one ;-)
4. http://www.xilinx.com/support/answers/10703.htm
Here are the nice timings, I've found this page right before I was going
to capture these timings myself with my old, good "fpgadbg" tool ;-)
( http://www.ise.pw.edu.pl/~wzab/fpgadbg ).
This diagram has shown me, that the DRCKx signal changes state not only
when SHIFT is high...
Article: 140599I would like to use a Spartan 3 DCM to divide a clock by 5. I don't care about skew and would prefer not to connect the CLK_FB. I do care very much about jitter. I'm actually using the FPGA to output a pulse-width-modulated signal, so I'm committing a total "no-no" by using it as an analogue component! I've read that the DCM DLL function is actually very clean as far as phase noise / spectral purity are concerned, as long as the DLL doesn't keep swapping taps. Does anyone know any sneaky non-standard tricks that would allow me to have my divide-by-5 with tap-swapping disabled? I could do the divide with CLBs; but I wonder if the DCM, with its dedicated routing to the global clock buffers, could actually be better? One caveat: I need the FPGA to be totally static at certain times, to completely eliminate digital switching noise. Does enabling a DCM activate any internal free-running oscillators? Finally, I must confess that my frequency is below the specified minimum; but I'm hoping the minimum doesn't apply if I'm only doing division. Am I in luck? TIA Andrew.
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