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In my design, I set the the memory module read enable forever. when I try to write the memory module, the models sim will generate a warning about the read output may not correct. Can I do something to "filter out" the warning?Article: 136776
Hi, I am trying to evaluate the PCI9656RDK-Lite board from PLX Technologies. The reference manual for the board provides board schematics which includes PQFP surface mounts to add FPGAs. I am planning to implement and test two things on the board - 1. Configure an FPGA on the board. 2. Transfer data to and from the FPGA over the PCI bus using the software drivers that come with the board. Has anybody worked with these boards before? PLX tech only supplies the board; mounting the FPGA and providing connections to it on the board need to be handled by the user. I have no experience in PCB design. Can anybody suggest how I could get this done? Thanks, PoonamArticle: 136777
Venkat wrote: > Hello all, > > I was wondering what is signified by the number suffix that comes with > each of Xilinx FPGAs along with their Family Names (v2p,v4,v5). For > example xc5vfx130t, I know t stands for Rocket IO Capability. > > Could anyone clarify me the number 130 suffixed to the name? 130 is the number of physical pins on the package. JonArticle: 136778
Giorgos_P wrote:
> On 4 ???, 16:55, Mike Treseler <mtrese...@gmail.com> wrote:
>> Giorgos_P wrote:
>>> Can Xilinx-ISE produce a report correlating the names of the signal o=
f
>>> the source code (VHDL) to the names of the nets after placement &
>>> routing or viseversa? If not how can I perform a back-annotated
>>> simulation without knowing the names of the signals I want to debug?
>> I do my debugging with source code.
>> A back-annotated gate sim is a double check
>> on synthesis and static timing, not functionality.
>>
>> -- Mike Treseler
>=20
> I agree, but if this double check fails, you need to go and see where
> it failed. You can't do this without knowing what the names of the
> nets correspond to (to the initial source code).
>=20
> Any ideas?
The only way I know to name an internal LUT is to instance it.
The problem is most likely
with the testbench or timing constraints or
asynchronous elements in the design.
When I suspect a synthesis error,
I slice up the design and test the pieces.
Good luck.
-- Mike Treseler
Article: 136779Hi there, I am using XUPV2P board... and wanted to use this CPU for understanding purpose... what i don't seem to understand is.... how would CPU find the instructions... I mean.., I understand different opcodes would be treated differently but how would those instructions be loaded in a RAM for CPU to read them.... :( or do I have to make changes into the program... and make it read the flash card and write the instructions in the flash card.... sounds complex... is there an easy way out.... Help would be appreciated...Article: 136780
On Dec 5, 7:06=A0am, Jon Elson <jmel...@wustl.edu> wrote: > Venkat wrote: > > Hello all, > > > I was wondering what is signified by the number suffix that comes with > > each of Xilinx FPGAs along with their Family Names (v2p,v4,v5). For > > example xc5vfx130t, I know t stands for Rocket IO Capability. > > > Could anyone clarify me the number 130 suffixed to the name? > > 130 is the number of physical pins on the package. > > Jon Thanks all for the responses. I was wondering if in some way the integer is linked to the number of system gates available on that particular FPGA which used to be the older notion. But I believe the integer signifies the number of logic cells (slices) which is more meaningful for an FPGA user. Venkat.Article: 136781
Hello all, Is there a way (even a rough approach) of finding an equivalent estimate of ASIC Gates for the design implemented in Xilinx FPGAs considering their definitions of Slices, DSPs and BRAMs? I know the approximate conversion ratio between ASIC and FPGA gates is 1:5, but way of identifying gates used in FPGA implementation is unknown (atleast for the latest families to be implemented on ISE 10.1). I am sure some of you would have had this practical experience and I will be glad if someone throws some light on my query. Thanks in advance. Venkat.Article: 136782
Venkat wrote: > Is there a way (even a rough approach) of finding an equivalent > estimate of ASIC Gates for the design implemented in Xilinx FPGAs > considering their definitions of Slices, DSPs and BRAMs? I know the > approximate conversion ratio between ASIC and FPGA gates is 1:5, but > way of identifying gates used in FPGA implementation is unknown > (atleast for the latest families to be implemented on ISE 10.1). There is no good way. For ASICs the usual way is to count the transistors and divide by the transistors in a two input NAND gate (four for CMOS). > I am sure some of you would have had this practical experience and I > will be glad if someone throws some light on my query. For FPGAs, Xilinx (and others) count DSPs and BRAMs as the appropriate number of gates, but you might not be able to use them in your design. For CLBs, you can use one for just one inverter, or an N input XOR gate (probably the most complicated gate). Designs will generally not fill up all the CLBs, though might come close. They all count toward the gate count. Routing takes up much of an FPGA, but, at least traditionally, doesn't count at all. Does that help? -- glenArticle: 136783
Hey guys, Ive been looking at XAPP485 for 7:1 deserialization on Spartan 3e/3a FPGAs, but I am bound to a Sprtan 3. Do you know if there is another relevant App Note, or at least which parts of the sample designs for 3E/3A will need to be modified? Cheers, GintsArticle: 136784
Has anyone out there sucessfully brought up a V5 download
chain ( LX50 w/SPI serial master, four LX30 slaves) over
JTAG using 10.1i SP3 ?
I'm bringing up my first V5 board design, and I'm seeing
issues that are reminiscent of older software and JTAG
startup bugs of years past; searching the Answer Records
didn't turn anything up specifically for V5.
The JTAG chain itself seems quite robust, I've buffered
things near the JTAG connector, and can run looped JTAG
ID tests all day long without any errors.
There seem to be some startup related issues, with devices
not quite completing configuration, and download order
dependent variations in supply current ( when loading
static test design files that just tie off all the I/Os ).
When downloading the bit files on-by-one through IMPACT,
the download completes to the point of DONE being released
by all devices in the chain, but the last slave device loaded
acts odd.
I've got other things to try tomorrow, just thought I'd ask
here to see if anyone had already banged into any of these:
1. Mode of Master/SPI interferes with V5 JTAG download???
2. JTAG download order dependent supply current
JTAG chain device programmed last draws ~1W extra current
and doesn't seem to have completed startup
3. indirect SPI flash programming not working
( M25P128 device ID reads wrong )
4. Note: 10.1i SP3 IMPACT no longer sets startup clock to
JTAG if the bit file being JTAG downloaded was originally
created for PROM download with CCLK as startup clock
More detail below.
thanks,
Brian
1. Mode selection of Master/SPI interferes with JTAG download???
I suspect this is the cause of some of my problems; I used
zero ohm R's to set the mode pins, my first change tomorrow
will be to switch the mode pins to JTAG.
2. JTAG download order dependent supply current
Whichever one of the Slaves ( JTAG chain 2-5 ) is
programmed last draws ~1W extra current and doesn't
seem to have completed startup.
The Master (also the first device in the JTAG chain) does
not exhibit this problem.
3. indirect SPI PROM programming not working
After downloading the indirect SPI core, IMPACT errors
out saying the M25P128 SPI flash device ID read back as zero.
(This may be related to #1)
4. Note: 10.1i SP3 IMPACT no longer sets startup clock to
JTAG if the bit file being JTAG downloaded was originally
created for PROM download with CCLK as startup clock
This is just a nuisance factor- IMPACT no longer pops up
the "changed startup clock to JTAG" box, you have to manually
generate a different bit file for JTAG or PROM download.
Article: 136785On 2008-12-05, Venkat <venkat.japan@gmail.com> wrote: > I am sure some of you would have had this practical experience and I > will be glad if someone throws some light on my query. As others have already said, this ratio is not going to be very accurate. Just a few data points to illustrate this: A 32 bit registered adder: * Synthesized for 130nm process, optimized for area: 2400 * Synthesized for 130nm process, optimized for speed: 11700 * Number of LUTs in a Virtex-4: 32 A 32-bit 16-to-1 registered mux: * Synthesized for 130nm process, optimized for area: 5600 * Synthesized for 130nm process, optimized for speed: 6700 * Number of LUTs in a Virtex-4: 256 An 8-bit 16 entry synchronuous register file memory (one port): * Synthesized for 130nm process, optimized for area: 7700 * Synthesized for 130nm process, optimized for speed: 8300 * Number of LUTs in a Virtex-4: 8 (Area figures in square micrometers) The conclusion from these values is that the ratio between Slices and ASIC area is going to vary wildly from design to design. Even if you try to make your algorithm clever by looking at the kind of structure (mux, adder, memory, etc) and figure out a gate count for that kind of structure in the FPGA, your figures will still vary wildly depending on if that particular component in the FPGA is a part of the critical path or not. And if you try to take that into account, well, you might as well synthesize your design with an ASIC synthesis tool and get much more accurate numbers. (Even so, the backend tool will probably add area to the estimates from the synthesis tool in my experience.) Anyway, as others have said, it is likely that memories will be your biggest cost in the ASIC. After memories, it is also likely that your I/O pads might be a big cost. Multipliers can also be quite costly. In one of the two ASICs I have been involved in (a research DSP for MP3 decoding), the area cost of the logic is probably about the same as for the I/O pads whereas the memories consume the major part of the silicon die. /AndreasArticle: 136786
Venkat wrote: > Is there a way (even a rough approach) of finding an equivalent > estimate of ASIC Gates for the design implemented in Xilinx FPGAs > considering their definitions of Slices, DSPs and BRAMs? I know the > approximate conversion ratio between ASIC and FPGA gates is 1:5, but > way of identifying gates used in FPGA implementation is unknown > (atleast for the latest families to be implemented on ISE 10.1). There is no easy way. First thing to figure out is that is your design gate of memory limited. If it is memory limited just estimate the silicon area of the memories. The process documentation gives estimates how many sq.mm each megabit of ram takes etc. Or use the memory generators to generate the memories for that process (use as big memories instances as possible to get more density etc.). The dies I have seen are usually almost full of memory, the logic is tiny part of the die, with 1Mgate/mm^2 it hard to fill the chip with logic. For the logic it might be easiest to just run the design trough Synopsys DC etc. to get rough estimate of the gate count. If that is not possible just multiply the LUT count by ~five and figure out some estimates for the multipliers if they are used in the DSP blocks. You should be near enough after that stage. You have to remember that hold fixing etc. can easily add 10% cells to the design during p&r etc. Also ASIC synthesis might create quite different structures, and that makes the comparison more difficult. In ASIC for example you might need much less replication because in comparable process ASIC is at least 3-5x faster. --KimArticle: 136787
> > I agree, but if this double check fails, you need to go and see where > it failed. You can't do this without knowing what the names of the > nets correspond to (to the initial source code). > > Any ideas? Actually the thing I do is follow up FFs. Although the names are changing in the PAR the generated FF's names are almost the same as in the source code. In modelsim you can find these FFs and add them to the wave window. But if we talk about LUTs it is a different story and not so easy to follow. Good luck. Enes.Article: 136788
I've read an introductory article into partial reconfiguration. It seems that FPGA devices have several limitations when using this technology. For example, the reconfigurable block has to cover whole height of device structure, and width is limited to several values. This means the whole design becomes overcomplicated if there's more then one changable block. I'll have to find another way. Perhaps some central router that would be connected to all other blocks, and smart enough to be reconfigured with control pins. Thanks to all for your responses Josip "Josip" <josip@yopmail.com> wrote in message news:gh5ue0$lr2$1@ss408.t-com.hr... >> Partial reconfiguration could do that. If it is only a small number >> of changes, it could be done with ordinary MUX logic, or even >> tristate logic (which is converted to MUX logic by the tools). >> >>> How hard would it be to do this, and what are alternative ways to >>> achieve something similar? >> >> There is literature on partial reconfiguration, so you can read that. >> >> Otherwise, how many different combinations do you have? You could >> just store the different configurations and load the appropriate one. >> >> -- glen >> > > Can you give me an insight how complicated it is to partially program FPGA > device to create a 16-bit link between two blocks? > Or to change select bits in mux? I'm familiar wih FPGA architecture, but I > don't know much about the process of programming the device. How open is > the process? Would I have to reverse engineer to find out what bits > correspond to a certian CLB? > > Thanks > Josip >Article: 136789
The 345th line of dma_ddr2_if.v file is: xfer_cnt <= xfer_cnt - 3'b10; why to substract 2,not 1? eg: read 64bytes data from SDRAM.it needs four times for 16bytes/xfer. But,it only reads two times because the counter substract 2. I only get 32bytes data,other 32bytes is lost. is ti a bug?Article: 136790
Sebastien Bourdeauducq schrieb: > Hello group, > > I'm trying to implement a simple design that uses partial > reconfiguration, and for testings I'm beginning with a modular > implementation that still has the bus macros. > > I use an AREA GROUP constraint to pack all the reconfigurable logic > into a rectangular region of the FPGA. This works for logic (the > constraint successfully moved the static design slices out of the > reconfigurable area), but apparently not with signals, as PAR routed a > static wire in the middle of my reconfigurable area (troublesome > signal is in red) : > http://lekernel.net/routing_problem.png > > The design is very simple, it is just supposed to blink two LEDs > (blinking enabled with DIP switches) with one controlled by the static > design and the other with a reconfigurable area. I am using the ML401 > board which has a Virtex 4. > > Top-level Verilog code is: > > module top(input clk, input en1, output led1, input en2, output led2); > blink_static static(.clk(clk), .en(en1), .blink(led1)); > wire led2_prr, en2_prr; > busmacro_xc4v_l2r_async_narrow busmacro_fromprr(.input0 > (led2_prr), .output0(led2)); > busmacro_xc4v_r2l_async_narrow busmacro_toprr(.input0(en2), .output0 > (en2_prr)); > blink_prm prr(.clk(clk), .en(en2_prr), .blink(led2_prr)); > endmodule > > The signal that causes the problem is named en2_IBUF in FPGA Editor. I > am using the following area constraints in the UCF file : > > INST "busmacro_fromprr" LOC=SLICE_X20Y122; > INST "busmacro_toprr" LOC=SLICE_X20Y124; > AREA_GROUP "AG_pr" RANGE = SLICE_X16Y98:SLICE_X21Y131; > AREA_GROUP "AG_pr" GROUP = CLOSED; > AREA_GROUP "AG_pr" PLACE = CLOSED; # tried with and without this one, > no change > INST "prr" AREA_GROUP="AG_pr"; > > How to prevent static signals from crossing my reconfigurable area ? > Perhaps I should not connect I/O signals directly to busmacros (but > why ?) ? Or did I misunderstand something and this signal is not going > to be a problem ? > > Thanks. > > Sebastien If you use the Early Access Parial Reconfiguration (EAPR Flow), static signals can be routed through your reconfigurable area. The tools will take care that the static signal is included in ALL partial bitstreams. The routing of the reconfigurable module is only constrained to the reconfigurable area if you set the AREA_GROUP to RECONFIG. -MarkusArticle: 136791
On 5 Dec, 00:51, Glen Herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > Venkat wrote: > > Is there a way (even a rough approach) of finding an equivalent > > estimate of ASIC Gates for the design implemented in Xilinx FPGAs > > considering their definitions of Slices, DSPs and BRAMs? I know the > > approximate conversion ratio between ASIC and FPGA gates is 1:5, but > > way of identifying gates used in FPGA implementation is unknown > > (atleast for the latest families to be implemented on ISE 10.1). > > There is no good way. =A0For ASICs the usual way is to count the > transistors and divide by the transistors in a two input NAND > gate (four for CMOS). Or, take the total cell area and divide by the area of a low drive strength two input NAND. JonArticle: 136792
Hi, > If you use the Early Access Parial Reconfiguration (EAPR Flow), static > signals can be routed through your reconfigurable area. The tools will take > care that the static signal is included in ALL partial bitstreams. Thanks for the answer. But aren't the static signals routed through a reconfigurable reguion going to be interrupted and/or glitched when the area is reconfigured ? Or are the tools clever enough to see that the signal was only going to the busmacro and therefore only affects the reconfigurable region ? SebastienArticle: 136793
On Dec 5, 10:15=A0am, Enes Erdin <eneser...@gmail.com> wrote: > > I agree, but if this double check fails, you need to go and see where > > it failed. You can't do this without knowing what the names of the > > nets correspond to (to the initial source code). > > > Any ideas? > > Actually the thing I do is follow up FFs. Although the names are > changing in the PAR the generated FF's names are almost the same as in > the source code. In modelsim you can find these FFs and add them to > the wave window. But if we talk about LUTs it is a different story and > not so easy to follow. > > Good luck. > > Enes. Thank you guys!Article: 136794
If cleaning up the project files doesn't work, you can then try using the .restore script in the project directory. I recently had a problem with ISE Simulator producing incorrect simulation results from a Project Navigator project, and the root cause was determined to be a corrupt .ise file. I opened a case with Xilinx, and they used the .restore script to fix it. The .restore file is text, so open it in a text editor and follow the instructions. Bryan On Dec 4, 12:55=A0pm, Gabor <ga...@alacron.com> wrote: > On Dec 4, 2:30=A0pm, "Brad Smallridge" <bradsmallri...@dslextreme.com> > wrote: > > > > When I try to add it ISE freezes and > > > I have to go to the task manager to shut it down. > > > Must be something in the VHDL file. > > Perhaps there is something that conflicts > > with the heirarchy? Like a module with the > > same name as your top module. > > > Brad Smallridge > > Ai Vision > > I've found that ISE 10.1 tries to be very smart about detecting the > hierarchy, and runs into trouble when there are errors in a source > file, sometimes ripping out entire sections of the design and asking > for a new top level module assignment when certain errors confuse it. > > There are also conflicts with other programs including some virus > scanners and backup software like Carbonite that cause confusion > with ISE's underlying database software. > > If ISE hasn't completely trashed the old project, you could try > "cleanup project files" before adding the new source. =A0It seems > that ISE is not good at cleaning up after itself. =A0This often > appears in things like .ucf file entries that don't go away > when you delete them from the file. =A0Sometimes you have to find > the temp folders under your main project directory with a name > containing the project name and delete everything in them. > > When all else fails, file a web case. =A0I know it's a headache > but otherwise how is Xilinx to know just how buggy their software > is? > > Regards, > GaborArticle: 136795
On 5 =D7=93=D7=A6=D7=9E=D7=91=D7=A8, 14:25, Jon Beniston <j...@beniston.com= > wrote: > On 5 Dec, 00:51, Glen Herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > > > Venkat wrote: > > > Is there a way (even a rough approach) of finding an equivalent > > > estimate of ASIC Gates for the design implemented in Xilinx FPGAs > > > considering their definitions of Slices, DSPs and BRAMs? I know the > > > approximate conversion ratio between ASIC and FPGA gates is 1:5, but > > > way of identifying gates used in FPGA implementation is unknown > > > (atleast for the latest families to be implemented on ISE 10.1). > > > There is no good way. For ASICs the usual way is to count the > > transistors and divide by the transistors in a two input NAND > > gate (four for CMOS). > > Or, take the total cell area and divide by the area of a low drive > strength two input NAND. > > Jon I would start with the xilinx map report: Design Summary: Logic Utilization: Number of Slice Flip Flops: 324 out of 21,504 1% Number of 4 input LUTs: 2,288 out of 21,504 10% .... Total equivalent gate count for design: 29,960 The example is atken from: http://bknpk.no-ip.biz/cpu_8051_ver/top.htmlArticle: 136796
On Dec 5, 3:37 am, "water9...@yahoo.com" <water9...@yahoo.com> wrote: > The 345th line of dma_ddr2_if.v file is: > > xfer_cnt <= xfer_cnt - 3'b10; > > why to subtract 2,not 1? eg: read 64bytes data from SDRAM.it needs > four times for 16bytes/xfer. But,it only reads two times because the > counter subtract 2. I only get 32bytes data,other 32bytes is lost. > > is it a bug? No. You subtract "2" because of the first "D" in "DDR".Article: 136797
On Dec 4, 5:41 pm, Venkat <venkat.ja...@gmail.com> wrote: > Hello all, > > Is there a way (even a rough approach) of finding an equivalent > estimate of ASIC Gates for the design implemented in Xilinx FPGAs > considering their definitions of Slices, DSPs and BRAMs? I know the > approximate conversion ratio between ASIC and FPGA gates is 1:5, but > way of identifying gates used in FPGA implementation is unknown > (at least for the latest families to be implemented on ISE 10.1). > > I am sure some of you would have had this practical experience and I > will be glad if someone throws some light on my query. > > Thanks in advance. > > Venkat. Only one way that will give you usable numbers: Send your files to your ASIC vendor and ask "About how many gates does this synthesize to?"Article: 136798
Venkat wrote: > On Dec 5, 7:06 am, Jon Elson <jmel...@wustl.edu> wrote: >> Venkat wrote: >>> Hello all, >>> I was wondering what is signified by the number suffix that comes with >>> each of Xilinx FPGAs along with their Family Names (v2p,v4,v5). For >>> example xc5vfx130t, I know t stands for Rocket IO Capability. >>> Could anyone clarify me the number 130 suffixed to the name? >> 130 is the number of physical pins on the package. >> >> Jon > > Thanks all for the responses. I was wondering if in some way the > integer is linked to > the number of system gates available on that particular FPGA which > used to be the > older notion. But I believe the integer signifies the number of logic > cells (slices) which > is more meaningful for an FPGA user. OK, then there should be two numbers in the full part number. The first is the "size" of the part, in some logic that only Xilinx understands, to equivalence the number of LUTs to "system gates". This magic formula is recomputed for each variant of the family, so that the number of LUTs in an XCS50 (5 V Spartan) is different that the number in an XC2S50E (1.8 V, I guess 3rd generation Spartan II). I had a design that fit nicely in an XCS30, I had to go to the XC2S50E to fit the same design. (Thanks much to someone on this group who warned me about this game!) Anyway, in these above-mentioned parts, the 50 refers to 50,000 equivalent gates, but the factor used to do the conversion varies by the family, so you can't compare directly between families. The 2nd number then is the lead count. JonArticle: 136799
Here is a presentation I prepared that summarizes the some of the SystemVerilog OOP and OVM v2.0 features. http://www.slideshare.net/akhailtash/ovm-features-summary-presentation/ Enjoy, -- Amal
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