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On Nov 14, 5:54 am, KJ <kkjenni...@sbcglobal.net> wrote: > On Nov 14, 2:14 am, axalay <axa...@gmail.com> wrote: > > > I have this problem. Use ISE 9.2 SP4. This problem is solved in ISE > > 10.1 SP1, but I whant solve this problem in 9.2. Help!!!! :) > > I'd suggest getting rid of at least one clock. > > KJ Or use ISE 10.1. Or both, or all 3! Build using 10.1. Notice which clocks are assigned to GCLKs. Find out which of the 9 clocks (from ISE 9.2) are NOT assigned to GCLKs. Manually assign the 8 favorite clocks to GCLKs. Disable the option to 'automatically promote to GCLK' or whatever it's called. It moves around from version to version. It looks like Xilinx finally addressed the issue where more nets would be promoted to GCLKs than there were GCLKs available. Previously, GCLK_max was set according to the family, and was not adjusted for the particular chip used. I had fun with this one when I did a XC2V4000 - > XC2V3000 migration. Where's Peter when we really need him? ;) PS: KJ has a very valid point. 9 clocks is a LOT of clocks, you can probably cut this number in half by using gated clocks where appropriate.Article: 136401
On Nov 14, 12:40=A0am, Andy Botterill <a...@plymouth2.demon.co.uk>
wrote:
> Gabor wrote:
> > On Nov 13, 4:32 pm, Andy Botterill <a...@plymouth2.demon.co.uk> wrote:
> >> Whilst trying to find out why my borrow out from a subtractor is
> >> behaving incorrectly I noticed that some of my subtractors are signed
> >> subtractors. This was shown by the ISE RTL schematic view. There are n=
o
> >> signed types in the verilog. So how could I have managed to do this?
>
> >> {COm, Rd_contents}=3DRn_contents - shifter_operand - BI;
>
> >> The synthesis report records the subtractors as 33 bits wide.
> >> shifter_operand, Rn_contents and Rd_contents are all 32 bits wide.
>
> >> So is there a template for a subtractor using borrow in and borrow out
> >> in verilog? e.g. I coded it wrongly.
>
> >> Can I change one the data types into unsigned to force XST to make it
> >> into an unsigned subtractor?
>
> >> Synthesis is verilog 2001. I can use verilog 95 if it would help.
>
> >> All suggestions gratefully listened to.
>
> >> I am still learning verilog so please be gentle. Thanks in advance And=
y.
>
> > Just to understand this better, you're saying that the carry (or
> > borrow)
> > out is being messed up in the implementation? =A0i.e. it looks like you=
r
> > inputs are being sign-extended before the subtraction?
>
> I'm not sure where the problem is yet. In my testbench I use this opcode
> 18 times. 2 times the borrow out (that would be a more obvious name than
> COm sorry) is wrong. The borrow out is in the wrong state compared to my
> pencil and paper calculations. The result (Rd_contents) is correct based
> on the input data.
>
> > Another thing that bothers me is the lack of parentheses in the
> > equation.
> > Subtraction is one of those operators where a- (b - c) is not the
> > same as (a - b) - c, and if you guess the operator order incorrectly
> > you can have errors in the output as well.
>
> The output side is correct it's the borrow out side that I can't understa=
nd.
>
> > Verilog 2001 does in fact have signed data types. =A0How did you
> > define your 32-bit numbers? =A0reg [31:0] foo? =A0integer foo?
>
> =A0 =A0 reg [31:0] Rn_contents;
> =A0 =A0 reg [31:0] Rd_contents;
> =A0 =A0 reg [31:0] shifter_operand;
> =A0 =A0 reg CO, COm, CI;
> =A0 =A0 (* KEEP=3D"TRUE" *) wire BI;
> =A0 =A0I only put the keep in there so that I can monitor the signal.
>
>
>
> > You can always force the correct behavior by zero-extending the
> > inputs yourself as in ({1'b0,a} - {1'b0,b}) - BI
>
> Rn_contents and shifter_operand_out are already the correct size. Do you
> really mean sign extend BI?
All of the arguments need to be extended to 33 bits for a proper
result.
The two registers I extended manually needed one more bit. You said
the result was correct which seems to imply that BI is handled
properly,
since a signed BI would actually add instead of subtract one.
>
> > You may want to post this on comp.lang.verilog to get the guru's
> > view.
>
> Let me do some checking before that. Thanks for the help.
>
>
>
> > Regards,
> > Gabor
Article: 136402Hi, We have Quartus II 7.2 subscription edition software. Although it is claimed that it supports Nios II cpu, I cannot generate downloadable .sof file for my first Nios project.The following message pop up at the last compiler process(EDA netlist generation). Could you tell me what is wrong here? Thanks. Error: Can't generate netlist output files because the file "C:/altera/ 72/qdesigns/sopc0/cpu.vhd" is an OpenCore Plus time-limited fileArticle: 136403
On Nov 14, 12:58=A0pm, fl <rxjw...@gmail.com> wrote: > Hi, > We have Quartus II 7.2 subscription edition software. Although it is > claimed that it supports Nios II cpu, I cannot > generate downloadable .sof file for my first Nios project.The > following message pop up at the last compiler process(EDA netlist > generation). Could you tell me what is wrong here? Thanks. > > Error: Can't generate netlist output files because the file "C:/altera/ > 72/qdesigns/sopc0/cpu.vhd" is an OpenCore Plus time-limited file I find at the Tool/Option/License Setup dialog box, no Nios II listed besides FIR Compiler, Numerically Controlled Oscillator, SDRAM. etc. Nios II support is separate sold? Thanks,Article: 136404
According to Altera's 2005 roadmap it was supposed to be available shortly after the Stratix IV and far earlier than Stratix IV GX and Hardcopy IV. PhilippArticle: 136405
"knight" <krsheshu@gmail.com> wrote in message news:6fa212ab-0906-4690-8732-bab276868e3d@a26g2000prf.googlegroups.com... > > Doesn't the PHY require to be configured through MDIO interface before > data transfer..? > How can this be possible..? I believe a default PHY configuration is good enough in many cases. If it is not good enough in your case you need to use MDIO and/or hardware settings. /MikhailArticle: 136406
It sounds as something happened to the cable's USB driver. Try unplugging the cable from your PC and plugging it back to a different USB port. This might trigger the driver's reinstallation. If it does be patient as depending on the software version it might have to install 2 or 3 drivers in a row before you can use it. Always tell it to install automatically (don't let it do any web search). The bottom line: wait for that green light on the adapter to appear before trying to do anything with the cable. /MikhailArticle: 136407
Philipp Klaus Krause wrote: > According to Altera's 2005 roadmap it was supposed to be available > shortly after the Stratix IV and far earlier than Stratix IV GX and > Hardcopy IV. Is that the same road-map that shows the MAX-III CPLD ;) -jgArticle: 136408
Gabor wrote:
> On Nov 14, 12:40 am, Andy Botterill <a...@plymouth2.demon.co.uk>
> wrote:
>> Gabor wrote:
I checked my arithmetic again. I got my subtraction wrong for the carry
bit. The result part was good. Please accept my humble apologies.
>>> You can always force the correct behavior by zero-extending the
>>> inputs yourself as in ({1'b0,a} - {1'b0,b}) - BI
My original verilog is good. If I move to another synthesis tool am I
likely to need to sign extend the arguments or not? I want to get into
good habits. Andy
>> Rn_contents and shifter_operand_out are already the correct size. Do you
>> really mean sign extend BI?
>
> All of the arguments need to be extended to 33 bits for a proper
> result.
> The two registers I extended manually needed one more bit. You said
> the result was correct which seems to imply that BI is handled
> properly,
> since a signed BI would actually add instead of subtract one.
>
>>> Regards,
>>> Gabor
Article: 136409"Andreas Ehliar": > Has anyone seen any other nice use case for MULTAND? Not tested: Let BX=0, F= -(f3 & f4). XB = (f1 & f2) & (f3 & f4) giving the option to route a partial, inverted and2, when using an and4, where the and4 can optionally be xored with lutG. BTW, I'm not sure about the polarity of Spartan3 F5MUX (from the FPGA-Editor, it isn't clear if it's sel-polarity can be chosen independent of the programmable BX inverter, and what the actual polarity chooses). Gruss Jan BrunsArticle: 136410
Guys and Girls You have all had a chance to look at our new low cost board Polmaddie1, http://www.enterpoint.co.uk/cpld_boards/polmaddie1.html, and lots of you have given the web stats I have been given. The eagle eyed of you may have even noticed the links to Polmaddie2 and Polmaddie3 and the fact that the Polmaddie2 is the first public showing of an Enterpoint board not based on Xilinx parts. What's even better is that US dollar and Euros pricing for this family is now benefiting countries using those currencies and these boards are even cheaper for those countries. The engineering of Polmaddie2 and Polmaddie3 was done this week and their availability is now only a matter when we fit them into our assembly facilities schedule. I expect them to be available some time before Christmas and the New Year. Our aim with this product range is produce a set of boards with the same 4 sets of traffic light LEDs, 60 I/O and FTDI USB solution but changing the central CPLD/FPGA to differing technologies and vendors. The result if all this will be a set of boards that can use common test labs allowing a comparison of the different devices and supporting software on a level-ish playing field and the question to all of you is what other devices would you like us to support in this family?? John Adair Enterpoint Ltd.- Home of Low Cost CPLD + FPGA Starter Kits.Article: 136411
need to know where to start to get RS232 comm's working, and the led's blinking. I was kinda hoping when I opened the box to my new XUPV2P: http://www.xilinx.com/products/devkits/XUPV2P.htm there would be some basic, hello world programs templates to play with, and a demo program so that I could have the board send and receive messages on the DB9 connector. I can't seem to locate anything of the sort. Does anybody have a good tutorial for my first program? TIA, JonArticle: 136412
On Nov 14, 1:40 pm, jleslie48 <j...@jonathanleslie.com> wrote: > need to know where to start to get RS232 comm's working, and the led's > blinking. > > I was kinda hoping when I opened the box to my new XUPV2P: > > http://www.xilinx.com/products/devkits/XUPV2P.htm > > there would be some basic, hello world programs templates to play > with, and a demo program so that > I could have the board send and receive messages on the DB9 > connector. I can't seem to locate anything of the sort. Does > anybody have a good tutorial for my first program? > > TIA, > > Jon Jon, On the page you list, there is a link "XUPV2P Documentation" - it's on the right hand side under "Documentation". Click on that link.Article: 136413
LittleAlex wrote: > On Nov 14, 5:54 am, KJ <kkjenni...@sbcglobal.net> wrote: >> On Nov 14, 2:14 am, axalay <axa...@gmail.com> wrote: >> >>> I have this problem. Use ISE 9.2 SP4. This problem is solved in ISE >>> 10.1 SP1, but I whant solve this problem in 9.2. Help!!!! :) >> I'd suggest getting rid of at least one clock. >> >> KJ > > Or use ISE 10.1. Or both, or all 3! > > Build using 10.1. Notice which clocks are assigned to GCLKs. Find > out which of the 9 clocks (from ISE 9.2) are NOT assigned to GCLKs. > > Manually assign the 8 favorite clocks to GCLKs. > > Disable the option to 'automatically promote to GCLK' or whatever it's > called. It moves around from version to version. > > It looks like Xilinx finally addressed the issue where more nets would > be promoted to GCLKs than there were GCLKs available. Previously, > GCLK_max was set according to the family, and was not adjusted for the > particular chip used. I had fun with this one when I did a XC2V4000 - >> XC2V3000 migration. > > Where's Peter when we really need him? ;) > > > PS: KJ has a very valid point. 9 clocks is a LOT of clocks, you can > probably cut this number in half by using gated clocks where > appropriate. Probably just a matter of semantics, but gated clocks shoud be avoided like the plague for synchronous designs. Presumably you meant using clock enables where appropriate.Article: 136414
Jan wrote: > Dear All, > > I can see in the documentation on the Sparton 3A that it has a FF placed > near the output pin. I would like to use this to ensure that the output > from a BUS is 100% in sync so routing don't affect the timing. > > Is there a ATTRIBUTE to give the signal or how do I tell the router to > use this last FF? > > I'm using ISE 10.1 > > Thank you in advance! > > Regards > Jan For any design where you need to insure that an IOB register (in or out) is used, check the Map Report File (.mrp extension). This is a text file, and section 6 (in ISE 9.2.03) is a table listing the properties of all of the IOBs in the design. Included in the table is a column name Reg(s). Also, there is pad file, which is another text file with the name, <designname>_pad.txt, that has a comprehensive list of all (used and unused) of the IOB properties. If you suddenly start having odd timing problems, check these files and insure that your IOB registers are still in place. HTHArticle: 136415
On Nov 14, 2:53 pm, Paul Urbanus <urbpub...@hotmail.com> wrote: > > Probably just a matter of semantics, but gated clocks should be avoided > like the plague for synchronous designs. Presumably you meant using > clock enables where appropriate. You are correct.Article: 136416
On Nov 15, 12:31=A0am, "MM" <mb...@yahoo.com> wrote: > It sounds as something happened to the cable's USB driver. Try unplugging > the cable from your PC and plugging it back to a different USB port. This > might trigger the driver's reinstallation. If it does be patient as > depending on the software version it might have to install 2 or 3 drivers= in > a row before you can use it. Yes I have done it, but still the problem persists. Always tell it to install automatically (don't > let it do any web search). The bottom line: wait for that green light on = the > adapter to appear before trying to do anything with the cable. > yeah, but the amber light has not turned green even when the target board= is powered up. > /MikhailArticle: 136417
On Nov 15, 1:20=A0pm, bish <bishes...@gmail.com> wrote: > On Nov 15, 12:31=A0am, "MM" <mb...@yahoo.com> wrote:> It sounds as someth= ing happened to thecable'sUSBdriver. Try unplugging > > thecablefrom your PC and plugging it back to a differentUSBport. This > > might trigger the driver's reinstallation. If it does be patient as > > depending on the software version it might have to install 2 or 3 drive= rs in > > a row before you can use it. > > Yes I have done it, but still theproblempersists. > > =A0Always tell it to install automatically (don't > > > > > let it do any web search). The bottom line: wait for thatgreenlight on = the > > adapter to appear before trying to do anything with thecable. > > yeah, but the amber light has not turnedgreeneven when the target board= is powered up. > > /Mikhail- Hide quoted text - > > - Show quoted text - Finally the problem is seems to be solved. I had ise9.2 and xilinx's user guide ug344 said it does not have driver file for model dlc10 and therefore needs to be downloaded from the xilinx's site. I did it and then the platform cable usb glowed with amber color much brighter than it did earlier when it did not worked. Then the much awaited green light lit up when connected to the board. Still I wonder how it had worked a month before when I used it for first few times with the ise9.2 and without downloading the new drivers for the cable from the web. As far as I can remember, I don't think I'd followed ug344 that time!! Anyway, it's working now!!Article: 136418
Jim Granville schrieb: > Philipp Klaus Krause wrote: >> According to Altera's 2005 roadmap it was supposed to be available >> shortly after the Stratix IV and far earlier than Stratix IV GX and >> Hardcopy IV. > > Is that the same road-map that shows the MAX-III CPLD ;) No, that one's from 2004. Though thinking about both of them not appearing it seems Altera is getting out of the low-cost programmable logic market. They continue to produce and sell what they have but don't design new products. There's probably a lot more money to be made in high-end programmable logic devices. PhilippArticle: 136419
On Nov 14, 5:44=A0pm, LittleAlex <alex.lo...@email.com> wrote: > On Nov 14, 1:40 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > > need to know where to start to get RS232 comm's working, and the led's > > blinking. > > > I was kinda hoping when I opened the box to my new XUPV2P: > > >http://www.xilinx.com/products/devkits/XUPV2P.htm > > > there would be some basic, hello world programs templates to play > > with, and a demo program so that > > I could have the board send and receive messages on the DB9 > > connector. =A0I can't seem to locate anything of the sort. =A0 Does > > anybody have a good tutorial for my first program? > > > TIA, > > > Jon > > Jon, > > On the page you list, there is a link "XUPV2P Documentation" - it's on > the right hand side under "Documentation". > > Click on that link. I have, I started going through the documentation, but I still can't find a hello world program.Article: 136420
"cms" <Michael.Tsvetkov@gmail.com> wrote in message news:94c10f19-554e-4e4f-8936-315ffc365847@g17g2000prg.googlegroups.com... On Nov 8, 10:23 am, "guestuser1" <guestus...@nowhere.net> wrote: > A year ago, I heard Synplicity's (RTL synth) Systemverilog support was > terrible. > > Altera Quartus-II 8.1 supports Systemverilog quite well (interfaces, > enums, typedefs, unique/priority case, always_comb/always_ff, etc.) > Not everything yet, but very usable. > > So how does the current version of Synplicity compare, in terms of > Systemverilog language support? > >Well, Synplicity had been acquised by Synopsys last year. Synopsys, in >opposite of Cadence and Mentor, >did't adopt SV in own products till to last time. While Cadence and >Mentor collaborated into SV support and moved forward with OVM >initiative, Synopsys concentrates into conventional HDL support only. No, that's completely wrong. Cadence was the *LAST* of the big EDA-vendors to support Systemverilog. Synopsys acquired Superlog about 5 years ago, which was the predecessor of the IEEE-standard Systemverilog. VCS has had Systemverilog support for at least that long, far in advance of either Mentor Modelsim or Cadence Incisive. Synopsys's other front-end design tools (Design Compiler, Formality, etc.) support Systemverilog quite well, and for some time, too. (Cadence's LEC also supports it quite well, but I couldn't try the others.) Cadence and Mentor partnered to produce a cross-vendor methodology, OVM, which is a good thing. It's nice to know that OVM will work in more than 1 simulator, and has *OFFICIAL* support from both. But they did it because both were FAR BEHIND Synopsys in terms of Systemverilog (functional simulation) marketshare, not because they 'were ahead of the curve.' Synopsys VMM had a de-facto standard until OVM emerged.Article: 136421
On Nov 13, 8:18=A0am, "lecroy7...@chek.com" <lecroy7...@chek.com> wrote: > Well, if your using ISIM I'm sure none of what I am about to write > will be anything new. > > I see three main problems with ISIM. > > It throws exceptions > It flat out will not simulate, almost like it lost the test bench > It runs out of memory > > All these appear to be random and not tied to the project. =A0It does > appear that it has something to do with me editing the waveforms but I > can't say 100%. =A0 =A0Once one of these errors happens, the error happen= s > every time I try to restart ISIM. =A0Restarting ISE and rebooting the PC > also have no effect. > > What I am finding is that if I blow away all of the temp files within > the project directory, and the documents and settings area, the > simulator once dead will not recover. =A0If I blow away the entire > project and restore it then just copy in my latest test bench, it > starts working again. =A0I have seen this no less than 20 times so far. > Its the fastest way I can seem to keep ISIM running. > > I decided to go ahead and put the tools on my newer PC. =A0Same install, > all the same patches. =A0No ISIM. =A0I does not even show up as an > option. =A0 Is anyone running ISIM on an XP Pro 64-bit =A0SP2 machine? > Maybe they don't support 64-bits with ISIM. > > I wish I could post some sort of test case to replicate the problem, > but it all appears random at this point. Hi, Sorry to hear about all the trouble you had with ISim lately. To make matters worse it does not help when you cant even open a case with Xilinx support directly. I would like to start by trying to answer one question at a time. While this forum is a great way to ask questions on any FPGA designs it is not as commonly monitored by anyone in Xilinx software groups. If you cant open a case and would like specific Xilinx only answers, please try the Xilinx forums in the future: http://forums.xilinx.com/xlnx/ As long as you register, you can use this. Now for the specific questions: > It throws exceptions > It flat out will not simulate, almost like it lost the test bench > It runs out of memory This is one of major items we are fixing in 11.1. A lot of this is already in 10.1 SP3. Now the exceptions you are seeing is due to another problem. Since ISim is integrated into Project Navigator what happens a lot is that the two are tied to the hip. This means that if PN crashes, then the ISim executable is still running in the background and it has not been killed. Each time you try to re-invoke that executable is always running and you get this exception. In 11.1 we will actually write a message that explains the true cause. You have another executable running and since PN always tries to write the same executable it crashes. What you can do to fix this is to open the process window and look for a .exe that has the name of the testbench. For example test_my_design.exe, kill this file manually and you wont have this problem. In 11.1, the error message will capture and tell you what to do. An AR is also being written on this as well. In 11.1 we will be offering our standalone version of ISim where you wont see this anymore as even if PN crashes for any reason, ISim can still run and if you close the ISim GUI it will kill the underlying .exe file. ISim is not supported on Windows 64 natively. Although the new installer should install both 32 and 64 bit automatically and you should still see ISIm running in the 32-bit mode. The Help for ISim is buried inside PN today and is hard to find. See AR - http://www.xilinx.com/support/answers/30942.htm. In 11.1 it will be have a self contained PDF file that is a lot easier to access. Also please take a look at the FAQ for ISim on our main product page - http://www.xilinx.com/ise/simulator Hope this helps Thanks DuthArticle: 136422
Philipp Klaus Krause wrote:
> Though thinking about both of them not appearing it seems Altera is
> getting out of the low-cost programmable logic market. They continue to
> produce and sell what they have but don't design new products.
But they are still in business...
> There's probably a lot more money to be made in high-end programmable
> logic devices.
.. and that may be why.
-- Mike Treseler
Article: 136423On Sat, 15 Nov 2008 11:45:02 -0800, "atass" wrote: >> While Cadence and >>Mentor collaborated into SV support and moved forward with OVM >>initiative, Synopsys concentrates into conventional HDL support only. > >No, that's completely wrong. Indeed it is; but your correction contains many misconceptions too. >Synopsys acquired Superlog about 5 years ago, which was the predecessor of >the IEEE-standard Systemverilog. Only of some parts of the language. Superlog was the progenitor of many of the design-related features, and of interfaces. Some of the OOP features of SV came out of Vera (another Synopsys product). But none of that matters any more; SV is a formal IEEE standard, over 3 years old now and still under active development (expect a significant revision in 2009). The history no longer matters very much. >Cadence and Mentor partnered to produce a cross-vendor methodology, OVM, >which is a good thing. It's nice to know that OVM will work in more than 1 >simulator, and has *OFFICIAL* support from both. Yes. You will find that the OVM library is written using entirely IEEE Std.1800-2005 compliant code, with the minor exception of pure virtual functions which are coded using the modified syntax from 1800-2009. The "official support" is in the sense that both vendors claim (correctly) that their tools will run OVM code, and therefore will support customers if they experience problems in trying to do so. > But they did it because >both were FAR BEHIND Synopsys in terms of Systemverilog (functional >simulation) marketshare, not because they 'were ahead of the curve.' Phrases like "far behind" represent value-judgements that are very hard to back up. >Synopsys VMM had a de-facto standard until OVM emerged. Neither OVM nor VMM are in any real sense de facto standards. They are both published, documented, supported class libraries, and happily both are now open-source. Both are changing and developing sufficiently fast that it would be foolish to describe either as a standard. All three big players in this space are working with Accellera to define interoperability standards for verification methodology, and that can only be a good thing for users. It is *not* a good thing for users when people spread the kind of half-truth and unsupportable opinion-dressed-as-fact that has been far too evident in this thread. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 136424
Philipp Klaus Krause wrote: > Jim Granville schrieb: > >>Philipp Klaus Krause wrote: >> >>>According to Altera's 2005 roadmap it was supposed to be available >>>shortly after the Stratix IV and far earlier than Stratix IV GX and >>>Hardcopy IV. >> >>Is that the same road-map that shows the MAX-III CPLD ;) > > > No, that one's from 2004. > > Though thinking about both of them not appearing it seems Altera is > getting out of the low-cost programmable logic market. They continue to > produce and sell what they have but don't design new products. > There's probably a lot more money to be made in high-end programmable > logic devices. True, Even the MAX 3000 is now hard to find on their web site, [Home.Products misses the MAX 3000, so you have to know it exists :) ] The MAX 7000 is further back still. Lattice and Atmel have the newest CPLD's available, and Actel seem to be pushing their smallest Flash FPGA devices down into the sub $1 region, with an 86MC-equivalent granular CPLD. Actel seem to be the most package-aware supplier. Xilinx meanwhile, seems content to 'ride out' their Coolrunner2 product line. -jg
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