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On 8 Sep., 18:59, "Symon" <symon_bre...@hotmail.com> wrote: > "woko" <wk...@gmx.net> wrote in message > > news:4d1085f3-8c9d-4f56-8966-976446092be8@x41g2000hsb.googlegroups.com... > > > HiFPGAspecialist, > > > we are would like to know if it is currently possible to implement > > high speedLVDSreceiver or transmitter in FPGAs. > > > Our next gerneration PCB board would have about 12LVDSreceiver > > (SN65LV1224B) , 6LVDS transmitter (SN65LV1023A) and anFPGA > > onboard. > > Please note that the LV1224 and LV1023 transmit thairLVDSin a single > > differential line, there is noLVDSclock pair necessary. The clock > > speed would be 48Mhz which would lead to aLVDSbandwidth of 576Mbs > > (12bit transmitting). > > It would save us money andFPGAIOs if we could get the serialization > > and deserialization in theFPGA. > > > I could find application notes aboutLVDSin a cyclone3, but I don't > > think that reception works without a clock pair. > > > Is anybody out there which as experience with this kind ofLVDSin a > >FPGA? > > We would be obliged for some practical hits... > > > Curious about your answers, > > Wolfgang Kopp > > Hi Wolfgang, > Data recovery without a clock is easy at 48Mbps. STW for XAPP224. > HTH., Syms. Hi Symon, I had a look at XAPP224 and XAPP250 (for a recovered clock). At this state I think we can not fully replace the LV1023A and LV1224B for the full speed. Because we transmit the signal over cable the input sensitivity could also be an issue. I read that the FPGA inputs have more input capacity than dedicated LVDS inputs. The transmitter at relative low speed (24Mhz clock; 288Mbs) would be possible, I think. Thanks for your answers! Best regards, WolfgangArticle: 135026
On Sep 10, 8:13=A0pm, Pablo <pbantu...@gmail.com> wrote: > Could anyone recommend me some method to Load an application stored in > External DDR Sdram without the use of XMD? > > PD: My board has not any Flash memory. When booting you NEED a non-volatile memory (e.g. FLASH) to copy a program from. You do not need XMD for it. If you only need to download the program to a programmed FPGA you definatelly need XMD or some other debugging tool to acccomplish that. Cheers, AlesArticle: 135027
"woko" <wkopp@gmx.net> wrote in message news:f5eda5fe-e895-4b72-8894-5a96007bdc58@d77g2000hsb.googlegroups.com... > On 8 Sep., 18:59, "Symon" <symon_bre...@hotmail.com> wrote: > > > Hi Symon, > I had a look at XAPP224 and XAPP250 (for a recovered clock). At this > state I think we can not fully replace the LV1023A and LV1224B for the > full speed. > Because we transmit the signal over cable the input sensitivity could > also be an issue. I read that the FPGA inputs have more input capacity > than dedicated LVDS inputs. > The transmitter at relative low speed (24Mhz clock; 288Mbs) would be > possible, I think. > > Thanks for your answers! > > Best regards, > > Wolfgang > Hi Wolfgang, Agreed, if your data rate is over 500Mbps, I think you need to use the external serdes solution or maybe RocketI/O as the other poster suggested.If you had double the LVDS channels, so half the rate, then you would probably be able to do it in the FPGA. Cheers, Syms.Article: 135028
leaver.andrew@gmail.com wrote: > On Sep 6, 9:53 pm, LittleAlex <alex.lo...@email.com> wrote: >> On Sep 6, 9:12 am, Paul Urbanus <urbpub...@hotmail.com> wrote: >> >> >> >>> Is there any reason I shouldn't compile the altera synthesis attributes >>> into my modelsim altera library. >>> Urb >> No. Just do it. > > The altera_syn_attributes package is included in the ModelSim AE > precompiled libraries starting with version 8.0, so you should no > longer have to compile the package manually when you upgrade to the > latest release. I'm using ModelSim DE (Designer) in PE mode. I don't think the libraries are compatible, but I may be wrong. To avoid any issues, I thought it best to just recompile under the simuluator that I am using.Article: 135029
On Sep 10, 10:13=A0am, aleksa <aleks...@gmail.com> wrote: > Are PROGRAM, CCLK, CS and DIN 5V tolerant, during configuration? > > The CS pin, according to the docs, should be connected to high logic > level. > > I have connected all VCCO to 3.3V. > > Anyone? Nobody knows? #%$&@#$*&@, I will place some resistors...Article: 135030
Hi, how can I install ISE simulator after use and deinstallation of ModelSim (other Mentor products are still installed)? After deinstallation of ModelSim i tried to reinstall "ISE 9.2i DVD - Xilinx Programmable Logic Design Tools" under Windows XP, SP2 on a Pentium 4 CPU @ 2,6 GHz. In the Project Navigator i created a testbench and set "Sources for: Behavioral Simulation". The entries in the "Processes for:"-window are: - Add Existing Source - Create New Source - ModelSim Simulator -- Simulate Beavioral Model How can i start the ISE Simulator instead of ModelSim? (We use a licensed ISE not the free Webpack) Thanks for any tip! Regards, TobiasArticle: 135031
On 11 Eyl=FCl, 05:19, Andreas H=F6lscher <andreas.hoelsc...@dsa-ac.de> wrote: > Hi, > how can I install ISE simulator after use and deinstallation of ModelSim > (other Mentor products are still installed)? > > After deinstallation of ModelSim i tried to reinstall "ISE 9.2i DVD - > Xilinx Programmable Logic Design Tools" under Windows XP, SP2 on a > Pentium 4 CPU @ 2,6 GHz. In the Project Navigator i created a testbench > and set "Sources for: Behavioral Simulation". The entries in the > "Processes for:"-window are: > > - Add Existing Source > - Create New Source > - ModelSim Simulator > =A0 -- Simulate Beavioral Model > > How can i start the ISE Simulator instead of ModelSim? (We use a > licensed ISE not the free Webpack) > > Thanks for any tip! > > Regards, > Tobias Under the project properties there is a part named simulator. Under this part select ise simulator. You can reach to project properties by "Source -> Properties".Article: 135032
On Sep 11, 4:12 am, Paul Urbanus <urbpub...@hotmail.com> wrote: > leaver.and...@gmail.com wrote: > > On Sep 6, 9:53 pm, LittleAlex <alex.lo...@email.com> wrote: > >> On Sep 6, 9:12 am, Paul Urbanus <urbpub...@hotmail.com> wrote: > > >>> Is there any reason I shouldn't compile the altera synthesis attributes > >>> into my modelsim altera library. > >>> Urb > >> No. Just do it. > > > The altera_syn_attributes package is included in the ModelSim AE > > precompiled libraries starting with version 8.0, so you should no > > longer have to compile the package manually when you upgrade to the > > latest release. > > I'm using ModelSim DE (Designer) in PE mode. I don't think the libraries > are compatible, but I may be wrong. To avoid any issues, I thought it > best to just recompile under the simulator that I am using. They libraries may be compatible, but I wouldn't assume so. It's not that tough to recompile the libraries, and it's a useful skill to have. For some strange reason, I rather enjoy the idea of doing a gate-level sim on a Cyclone-III using ModelSim_XE :)Article: 135033
On Sep 11, 7:19=A0am, aleksa <aleks...@gmail.com> wrote: > On Sep 10, 10:13=A0am, aleksa <aleks...@gmail.com> wrote: > > > Are PROGRAM, CCLK, CS and DIN 5V tolerant, during configuration? > > > The CS pin, according to the docs, should be connected to high logic > > level. > > > I have connected all VCCO to 3.3V. > > > Anyone? > > Nobody knows? > > #%$&@#$*&@, I will place some resistors... I don't understand your question. The subject line asks if the parts are 5 volt tolerant and then you say you are connecting them to 3.3 volts. I don't see where the problem is. I am pretty sure the data sheet clearly indicates that the parts are *not* 5 volt tolerant although I have not looked. I am basing this on the fact that Xilinx left 5 volt tolerance behind many years ago with the initial Spartan series with the Spartan II not being 5 volt tolerant, IIRC. But I won't swear to that. Check the maximum DC levels in the specs. Connecting to 3.3 volts should certainly be ok as long as you never want to drive the pins low again. If the trace and via to power are under the chip, you won't even be able to cut the trace easily. What exactly is your concern? RickArticle: 135034
"aleksa" <aleksaZR@gmail.com> schrieb im Newsbeitrag news:7ba65a41-e819-4d58-aefe-e4e01684f2df@25g2000hsx.googlegroups.com... > Are PROGRAM, CCLK, CS and DIN 5V tolerant, during configuration? > > The CS pin, according to the docs, should be connected to high logic > level. > > I have connected all VCCO to 3.3V. > > Anyone? Xilinx Spartan II has 5V tolerant inputs, see page 9@ http://www.xilinx.com/support/documentation/data_sheets/ds001.pdf "In a bank, inputs requiring VREF can be mixed with those that do not but only one VREF voltage may be used within a bank. Input buffers that use VREF are not 5V tolerant. LVTTL, LVCMOS2, and PCI are 5V tolerant. The VCCO and VREF pins for each bank appear in the device pinout tables. Also see page2@ http://www.xilinx.com/support/documentation/application_notes/xapp079.pdf Search for "tolerant" or "5V" in the Acrobat reader to get all relevant information concerning 5V tolerance. For SPARTAN II or VIRTEX only: 5V tolerance means, that FPGA I/O inputs (also configuration pins) can handle 5V levels (in LVTTL I/O Standard), but I/O outputs cannot drive to 5V, since VCCO must be below 4V. If vou pullup an Spartan-II I/O to 5V, with tristating output, you can measure 5V at the I/O pin. If you enable the tristate buffer for outputting a '1' at the I/O, the voltage goes down to the VCCO level of (mostly) 3,3V, driving VCCO with the current through the pullup. If your pullup to 5V is 0 Ohms, and you output a '1', the chip will be damaged. For configuration issues, see also XAPP 176: http://www.xilinx.com/support/documentation/application_notes/xapp176.pdf MIKE -- www.oho-elektronik.de OHO-Elektronik Michael Randelzhofer FPGA und CPLD Mini Module Klein aber oho ! Kontakt: Tel: 08131 339230 mr@oho-elektronik.de Usst.ID: DE130097310Article: 135035
i am working on orcad 9.1 in my schematics after design rules check i came 28 errors.1. net has fewer than two connections 2.no matching off page connectors. these are the major error. can any one one give suggestionsArticle: 135036
On 11 sep, 10:43, ales.gor...@gmail.com wrote: > On Sep 10, 8:13=A0pm, Pablo <pbantu...@gmail.com> wrote: > > > Could anyone recommend me some method to Load an application stored in > > External DDR Sdram without the use of XMD? > > > PD: My board has not any Flash memory. > > When booting you NEED a non-volatile memory (e.g. FLASH) to copy a > program from. You do not need XMD for it. > If you only need to download the program to a programmed FPGA you > definatelly need XMD or some other debugging tool to acccomplish that. > > Cheers, > > Ales So, I could download a bitstream.bit to a External DDR Sdram Memory (with Impact), but I necessary need XMD to Load (Execute) this application?Article: 135037
aleksa wrote: > On Sep 10, 10:13 am, aleksa <aleks...@gmail.com> wrote: >> Are PROGRAM, CCLK, CS and DIN 5V tolerant, during configuration? >> >> The CS pin, according to the docs, should be connected to high logic >> level. >> >> I have connected all VCCO to 3.3V. >> >> Anyone? > > Nobody knows? Surely the datasheet knows. What does it say? -JeffArticle: 135038
I recently built a screaming fast machine for doing my FPGA simulations and compiles. I just ran a design compile for purposes of comparison on my new Core2 Extreme Quad based machine and my old dual processor Xeon machine. ---------------------------------------------------------------------------------------- Here are the system specs for old machine: 2 Intel Xeon CPU model 4, stepping 3 at 3.2 GHz 4GB DDR PC2700 FSB speed 800 MHz. The motherboard is a Supermicro X6DAT-G ------------------------------------------------------------------------------------------ Here are the system specs for the new machine: Intel Core2 Extreme CPU QX9770 @3.2 GHz (quad core) OCZ Platinum 4GB (2 x 2GB) 240-Pin DDR3 SDRAM DDR3 2000 (PC3 16000) Dual Channel FSB speed 1600 MHz. The motherboard is a ASUS P5E3 PREMIUM/WIFI-AP @n LGA 775 The benchmark I used is a project that I am working on that utilizes most of the memory and LEs on a stratix I 60K LE device. Quartus took about 33 min to finish the compile on the older machine The new machine took 12 min to finish. I was not expecting a 3X speedup! I guess main memory speed is the major bottleneck for compilation.Article: 135039
"Pablo" <pbantunez@gmail.com> wrote in message news:80f9ebe9-b1c7-4276-b34a-d4e7ceb64c6c@c65g2000hsa.googlegroups.com... On 11 sep, 10:43, ales.gor...@gmail.com wrote: > On Sep 10, 8:13 pm, Pablo <pbantu...@gmail.com> wrote: > > > Could anyone recommend me some method to Load an application stored in > > External DDR Sdram without the use of XMD? > > > PD: My board has not any Flash memory. > > When booting you NEED a non-volatile memory (e.g. FLASH) to copy a > program from. You do not need XMD for it. > If you only need to download the program to a programmed FPGA you > definatelly need XMD or some other debugging tool to acccomplish that. > > Cheers, > > Ales So, I could download a bitstream.bit to a External DDR Sdram Memory (with Impact), ------- The simple answer is Impact can't and doesn't do that, and the unprogrammed device wouldn't be able to read its bitstream even if it did. (Why do we bother with MIG and MPMC otherwise?) Is this a Spartan3-AN device?Article: 135040
On Sep 11, 5:28=A0pm, "M.Randelzhofer" <techsel...@gmx.de> wrote: > "aleksa" <aleks...@gmail.com> schrieb im Newsbeitragnews:7ba65a41-e819-4d= 58-aefe-e4e01684f2df@25g2000hsx.googlegroups.com... > > > Are PROGRAM, CCLK, CS and DIN 5V tolerant, during configuration? > > > The CS pin, according to the docs, should be connected to high logic > > level. > > > I have connected all VCCO to 3.3V. > > > Anyone? > > Xilinx Spartan II has 5V tolerant inputs, see page 9@http://www.xilinx.co= m/support/documentation/data_sheets/ds001.pdf > > "In a bank, inputs requiring VREF can be mixed with those > > that do not but only one VREF voltage may be used within a > > bank. Input buffers that use VREF are not 5V tolerant. > > LVTTL, LVCMOS2, and PCI are 5V tolerant. The VCCO and > > VREF pins for each bank appear in the device pinout tables. > > Also see page2@ > > http://www.xilinx.com/support/documentation/application_notes/xapp079... > > Search for "tolerant" =A0or "5V" in the Acrobat reader to get all relevan= t > information concerning 5V tolerance. > > For SPARTAN II or VIRTEX only: > > 5V tolerance means, that FPGA I/O inputs (also configuration pins) can > handle 5V levels (in LVTTL I/O Standard), but I/O outputs cannot drive to > 5V, since VCCO must be below 4V. > > If vou pullup an Spartan-II I/O to 5V, with tristating output, you can > measure 5V at the I/O pin. If you enable the tristate buffer for outputti= ng > a '1' at the I/O, the voltage goes down to the VCCO level of (mostly) 3,3= V, > driving VCCO with the current through the pullup. =A0If your pullup to 5V= is 0 > Ohms, and you output a '1', the chip will be damaged. > > For configuration issues, see also XAPP 176: > > http://www.xilinx.com/support/documentation/application_notes/xapp176... > > MIKE > > --www.oho-elektronik.de > OHO-Elektronik > Michael Randelzhofer > FPGA und CPLD Mini Module > Klein aber oho ! > Kontakt: > Tel: 08131 339230 > m...@oho-elektronik.de > Usst.ID: DE130097310 I know all that, I did read the docs. Spartan-II does have 5V tolerant IOBs, but it doesn't clearly say that configuration pins are to be considered IOBs as well. http://www.retroleum.co.uk/fpga-config.html (paragraph 2) shows that people besides me have the same problem. > 5V tolerance means, that FPGA I/O inputs (also configuration pins) can > handle 5V levels (in LVTTL I/O Standard) That is what I was looking for! A confirmation that configuration pins are also 5V tolerant. Danke!Article: 135041
That is what I was looking for! A confirmation that configuration pins are also 5V tolerant. Danke! Bitte! Spartan-II is rather outdated, yet beeing an interesting solution together with 5V parts. I remember weekly that your question was answered years ago, but since google is used in Xilinx answer database, it's impossible to find rare requested information :-( If you search for e.g. a microblaze manual, you get the link to the oldest manuals, because these are requested mostly. But you look for the newest revision. This is BS. The datasheet really doesn't say anything about the special config pins concerning 5V tolerance. (The newer docs about Spartan3 etc. are really better in many ways !) If the configuration pins would not be 5V tolerant, Xilinx wouls say that clearly in the datasheet. MIKE -- www.oho-elektronik.de OHO-Elektronik Michael Randelzhofer FPGA und CPLD Mini Module Klein aber oho ! Kontakt: Tel: 08131 339230 mr@oho-elektronik.de Usst.ID: DE130097310Article: 135042
<sureshbabu.payauala@gmail.com> wrote in message news:16697b45-a499-4416-afb9-382e097471ad@n38g2000prl.googlegroups.com... > i am working on orcad 9.1 in my schematics after design rules check i > came 28 errors.1. net has fewer than two connections 2.no matching off > page connectors. these are the major error. can any one one give > suggestions Do you disagree with the assessment? Does/do the nets have only one connection? If deliberate, you can get this error by placing a wire on a pin and not connecting to another pin. If this is the case, remove the wire and place a NC (X) on the pin. -- GregArticle: 135043
Jon Elson wrote: > Hello, all, > > I just got a potential project thrown in my lap. I designed an > all-analog delay generator module, with 32 delays that trigger 32 pulse > widths. So, basically, 64 wide-range programmable one-shots on one > board. LVDS in, ECL out (for legacy gear). These one-shots can be > programmed from about 10 ns to 12 us in several ranges. > > Somebody asked, "Gee, couldn't you do that with an FPGA?" Well, a few > years ago, maybe not. So, could anyone suggest some fast FPGAs that can > handle clocks in the 500+ MHz range? I normally work with Xilinx, but > could look at some others, too. I suspect RAM-based FPGAs would be > desirable over one-time programmed. It would not be a problem to use > several smaller FPGAs to keep them from overheating at the high clock > rate. We have forced-air cooling in the equipment, but you lose that > when modules are put on extenders. > > The basic circuit would look like a 13-bit counter with a 13-bit preset > register, and a zero comparator. (It could also be a 13-bit counter > that starts at zero, and a preset register that sets the terminal > count.) So, 432 FFs would do 8 channels of this dual one-shot logic. > Half of the FFs would be clocked at the 500+ MHz rate, the other half > would be essentially static. > > Thanks in advance for any suggestions! > > Jon > The fabric in V4 will run at 500MHz as long as you don't use the carry chains. The memories and DSP48s are slower, with the -4 speed grade capable up to 400 Mhz, but even in that a careful design in the fabric has no problem running on a 500 MHz clock. You'd be better off though, bringing the data in and splitting it to a lower clock rate right away. You can do that pretty easily using DDR, which while easier in more recent devices, can also be done in older devices.Article: 135044
Andrew FPGA wrote: >>So, you think a 13-bit counter feeding a 13-bit identity comparator will >>work at 250 MHz? > > Others have said it may be possible but what they fail to acknowledge > is the large amount of extra design effort and care required to get > there. 250 MHz is really pushing the limits in spartan 3e in my > experience. You may have to work very hard to get there: for example I > have just finished a distributed arithmetic filter design, that has > only 1 LUT level between flops and after a lot of effort I got it to > run at 206 MHz in a sp3 1600e. I can see how to get to 220MHz, but > beyond that I don't know. The longest carry chain is 10 bits. > > I had to bypass synthesis and instantiate xilinx primitives directly > to gaurantee my logic was implemented in 1 LUT level. Then I had to > manually floorplan the design - placing each flop with the > corresponding LUT by hand( I uses RLOC's embedded in the VHDL source). > The automatic placer didn't always place the LUT with the FLOP so you > end up with 2 routes which kills the timing completely. > > >>Yeah, I really don't think we can handle $2000 IC's. This isn't a real >>production project, we might build 5 of them at a time, but we are still >>cost-sensitive. > > If its such low volumes just take the unit cost hit and move to a > Virtex part. How valuable is your time? I agree. 250 MHz is really pushing it in a Spartan3, especially if there are any carry chains involved. Unless you have the volume where material costs are going to swamp your development costs, move up to a V4 or V5. If the volume is low, just use one of the evaluation boards and save yourself a lot of board development effort.Article: 135045
On Sep 11, 8:01=A0pm, Pablo <pbantu...@gmail.com> wrote: > On 11 sep, 10:43, ales.gor...@gmail.com wrote: > > > On Sep 10, 8:13=A0pm, Pablo <pbantu...@gmail.com> wrote: > > > > Could anyone recommend me some method to Load an application stored i= n > > > External DDR Sdram without the use of XMD? > > > > PD: My board has not any Flash memory. > > > When booting you NEED a non-volatile memory (e.g. FLASH) to copy a > > program from. You do not need XMD for it. > > If you only need to download the program to a programmed FPGA you > > definatelly need XMD or some other debugging tool to acccomplish that. > > > Cheers, > > > Ales > > So, I could download a bitstream.bit to a External DDR Sdram Memory > (with Impact), but I necessary need XMD to Load (Execute) this > application? 1. You can download the whole bitstream (hw+sw) into a PROM with impact and boot it from there. But if your program is larger than available BRAM resources then this is out of the question 2. You can download the hw first using impact and then you load and execute the program (*.elf) with xmd. Since you do not have any flash on board you do not have any other option! If your executable (*.elf) does not fit BRAM you will not be able to boot the system at power up! Cheers, AlesArticle: 135046
- > The simple answer is Impact can't and doesn't do that, and the unprogrammed > device wouldn't be able to read its bitstream even if it did. (Why do we > bother with MIG and MPMC otherwise?) So, there is nothing to do. > Is this a Spartan3-AN device? It is a Custom Board with a VirtexIIPro and a Micron External Memory.Article: 135047
On Sep 11, 5:03=A0pm, wallge <wal...@gmail.com> wrote: > I recently built a screaming fast machine for doing my FPGA > simulations and compiles. > I just ran a design compile for purposes of comparison on my new Core2 > Extreme Quad =A0based machine > and my old dual processor Xeon machine. > > -------------------------------------------------------------------------= --------------- > Here are the system specs for old machine: > 2 Intel Xeon CPU model 4, stepping 3 at 3.2 GHz > 4GB DDR PC2700 > FSB speed 800 MHz. > The motherboard is a =A0Supermicro X6DAT-G > -------------------------------------------------------------------------= ----------------- > Here are the system specs for the new machine: > Intel Core2 Extreme CPU QX9770 @3.2 GHz (quad core) > OCZ Platinum 4GB (2 x 2GB) 240-Pin DDR3 SDRAM DDR3 2000 (PC3 16000) > Dual Channel > FSB speed 1600 MHz. > The motherboard is a =A0ASUS P5E3 PREMIUM/WIFI-AP @n LGA 775 > > ThebenchmarkI used is a project that I am working on that utilizes > most > of the memory and LEs on a stratix I 60K LE device. > > Quartus took about 33 min to finish the compile on the older machine > The new machine took 12 min to finish. > > I was not expecting a 3X speedup! > I guess main memory speed is the major bottleneck for compilation. Wow, that's quite an impressive speed-up. I wish I could convince my company to buy a beast like that. My current design takes about 45 minutes for the PAR, on a 3.0 GHz Core 2 Duo. -PatrickArticle: 135048
Hi all! For an actual project I'm looking for an ultra low power FPGA. The size is not so important, we probably don't need much more resources that an CPLD would provide but power is absolutely critical. I heard already about Siliconblue but does someone of you know of any other devices playing in the same league to get some overview? Siliconblue seams to be very new on the market and this means a certain risk. Some nonvolatile config memory also would be preferable. Thanks, MichaelArticle: 135049
On Wed, 10 Sep 2008 16:22:23 -0700 (PDT), bgong86@gmail.com wrote:
|
|> In ISE Webpack under Synthesize Properties under synthesis options is
|> bus delimiter. You can change it from the default <> to {},[] or ().
|
|Thanks, James, that's good to know. However, I'm still trying to
|figure out the correct RPM syntax for busses in Verilog. Changing the
|bus delimiter option didn't helped the RPM code to get used in the
|design. Anymore ideas?
|
|Brian
|
|--------------
Nope.
james
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