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Hi Farhan, My experience with this wrapper was not a good one. It won't bridge a memory controller for you, because it has an (undocumented) limit of only working in the address range 0x80000000-0x800000ff. It won't signal SI_ToutSup either, resulting in another hard-to-meet timing requirement on your memory controller. I tried to use the bridge to interface with a wishbone ATA host (also from opencores). It sort-of worked, but it was far from satisfying. Reading the OPB IPIF specs I realized that most signals map one-to-one with WB. It was a piece of cake to connect the wishbone peripherial directly to the OPB IPIF, without bridge. Faster, cheaper, better. Regards, MarcArticle: 118026
vlsi_learner wrote: > Hi all, > > My ASIC design requires dual port memories(one port R/W other port > only read) but there is a constraint on using it. > Instead I am planning to create this memory using single port RAM's. > > Writes to this memory take place at 60 Mhz while reads can occur at > freq varying from 5-30 Mhz. > > Is there some way out? > If you can allow waits on either port then you should be able to do this. You would need an arbitrator that can detect when the memory is in use from one port and hold off the other port until the pending transaction is finished. You'll need to be careful in your arbitrator design to make sure you don't have problems with requests coming in at the same time, and with your system design to make sure that the waits are OK. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/ Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" gives you just what it says. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 118027
Evnin' To make life easier when I decide to abandon an old Workstation to get a more powerful one... Can for example Quartus or ispLever use the MAC address of a Bluetooth or WLAN dongle so when I buy a new PC I just need to move the Bluetooth/WLAN dongle? thx in advance rickArticle: 118028
mmihai wrote: > I have noticed the timing after placement/routing is varying with > incremental changes; just changing an initial value could make the > timing to fail (I saw numbers like 47 and 45 MHz). The logic seems to > run on my board but that does not mean it will not fail on some other > board/fpga chip. That's a pretty common problem. > My guess is everything is caused by a difference in the placement; > from time to time the placer starts from the wrong place [seed?] and > the resulting design will fail timing. That's true. > Did you have similar experiences? What can one do to expect more > consistent results? What you need to do is put good timing exceptions into your constraints file so that PAR doesn't expend effort trying to optimize timing on paths that don't matter and can instead focus on the truly critical paths. I've found that identifying multi-cycle paths is a big help in getting more consistent PAR results. That said, If you're having trouble meeting timing with a 50MHz clock constraint you may have some seriously long paths in your design. Adding timing exceptions may not help and you might have some pipeline optimization to do. EricArticle: 118029
On Apr 15, 12:47 pm, "Bhanu Chandra" <vbh...@gmail.com> wrote: > Hi all, > > I am trying to make a peripheral attached to the OPB bus. This > peripheral has a BRAM block in it. The idea is to check how to read > and write to the simple BRAM block and later add some logic to the > controller. > > The data to be written to an address range is written to the BRAM > block and data is read when needed by the program (this is what we are > trying to implement). We would greatly appreciate any information as > to how to go about interpreting the signals on the OPB and also how to > write / read the data in the BRAM as per the requests on OPB. > > Thanks and Regards, > Bhanu There's an OPB peripheral creation wizard in EDK that should help you. Most of the advanced options you can disable. Once you have an ISE project generated you can make it infer bram with vhdl/verilog formatted as on this page: http://toolbox.xilinx.com/docsan/3_1i/data/fise/xst/chap02/xst02013.htm -wsaculArticle: 118030
Richard Klingler <richard_uclinux_net> wrote: > Evnin' > To make life easier when I decide to abandon an old > Workstation to get a more powerful one... > Can for example Quartus or ispLever use the MAC address > of a Bluetooth or WLAN dongle so when I buy a new PC > I just need to move the Bluetooth/WLAN dongle? At least for the WLAN dongle, there are chances that this will work. It depends on how the program tried to acquire the MAC address. If it uses the normal dlls, this can also be faked. There are also tools to fake the MAC address on many hardwares. To understand hwo the program acquire, install the application in wine, run with debug messeages anables and scroll throught tons of output. Any news from your Lattice board for the MICO32 development? Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 118031
Sebastien Bourdeauducq wrote: > Hi, > > I intend to wire up an Altera Cyclone 2 to a NET2272 USB controller. > The bus of the NET2272 is similar to that of a parallel RAM, with > address lines, bidirectional data bus, and read/write strobe signals. > > I'm concerned about the electrical safety of the bidirectional data > lines. If I mess up the FPGA program and assert the read strobe signal > while the data lines are set as outputs, this may damage (expensive) > parts, right ? Do you know of a simple way to avoid this ? Putting > resistors in series on the data lines ? Resistors is a fool-proof way of doing it as long as the necessary resistors are small enough not to have a significant effect on the data valid window in either direction. Another possibility would be to simply set the IOB slew rate to slow and output drive current to 4-8mA. Under these drive conditions, most FPGAs can survive indefinitely long shorts (to ground or Vccio) when cooled appropriately. Note: actual short-circuit currents will actually be higher than the current specified for the drive strength. There is a chart somewhere on Xilinx's site that specifies short-circuit currents as a function of drive strength settings. IIRC, the short-circuit currents for 8mA drive was something like 30mA.Article: 118032
Hi Uwe Gonna try that with Quartus and ispLever now with 2 Bluetooth dongles now as I have no WLAN dongles abvailable... Yes...Lattice Semiconductor finally sent me the Mico32DSP board together with Linux and Windows licenses for ispLever (o; Now just need to get SO-DIMM module and sart working on u-boot and later on uClinux for it (o; cheers rick On 2007-04-16 19:15:26 +0200, Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de> said: > Richard Klingler <richard_uclinux_net> wrote: >> Evnin' > > >> To make life easier when I decide to abandon an old >> Workstation to get a more powerful one... > >> Can for example Quartus or ispLever use the MAC address >> of a Bluetooth or WLAN dongle so when I buy a new PC >> I just need to move the Bluetooth/WLAN dongle? > > At least for the WLAN dongle, there are chances that this will work. It > depends on how the program tried to acquire the MAC address. If it uses the > normal dlls, this can also be faked. There are also tools to fake the MAC > address on many hardwares. To understand hwo the program acquire, install > the application in wine, run with debug messeages anables and scroll > throught tons of output. > > Any news from your Lattice board for the MICO32 development? > > ByeArticle: 118033
rohit2000s@yahoo.com wrote: > Hi, > > I was wondering how the number 166Mhz for DDR came up? Why not say... > 200MHz/250MHz DDR? I am sure there is some thought process behind > that, could someone help me walk through? > > Thanks in advance ! > -Rohit Why is PCI 33MHz? If you look at it from the PC angle, almost all clocks are multiples of ~33.3MHz and the reason for this is to have integer clock multipliers and dividers to simplify PLL and related circuitry design. PC2700 DDR-DIMMs operate at 166MHz, CPU FSBs of that time operated at 333/667MHz, PCI operated at 33MHz as always, AGP at 66MHz. So, the 166MHz figure is simply due to PC computing legacy. Within the next two years, after PCIe will have completely replaced PCI and AGP, we will see other system clocks shift from multiples of 33/66MHz to multiples of 125/250MHz... or multiples of 75/150MHz if Intel/AMD decide to reuse the SATA reference clock instead.Article: 118034
ghelbig@lycos.com wrote: > On Apr 15, 12:33 pm, rohit20...@yahoo.com wrote: >> Hi, >> >> I was wondering how the number 166Mhz for DDR came up? Why not say... >> 200MHz/250MHz DDR? I am sure there is some thought process behind >> that, could someone help me walk through? >> > Perhaps this number is how slow one can go, not how fast? If you're > not meeting timing with your FPGA, the low frequency number could be > important. > > DDR does have a minimum frequency... The minimum operating frequency for DDR DRAMs comes from the DLL circuitry used to capture data. My 166MHz Infineon DRAMs say the minimum operating frequency for its DLL is 100MHz. The maximum operating frequency is determined by how fast the DRAM is able to get data into or out of the active row (data) register and other control structures with the maximum amount of pipelining enabled. Since the high-K process used for DRAMs yields slow logic, latency cycles (intermediate registers) pile up really fast on high-speed DRAMs.Article: 118035
"vlsi_learner" <bajajk@gmail.com> writes: > My ASIC design requires dual port memories(one port R/W other port > only read) but there is a constraint on using it. > Instead I am planning to create this memory using single port RAM's. You an use two RAMs if you have enough RAM availabe in your ASIC. Simply write into both RAMs using the same address and data. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 118036
> > Did you have similar experiences? What can one do to expect more > consistent results? > Check out some of the new features in ISE 9 : http://www.xilinx.com/ise/marketing/index.htm#productivity One of the new features is smartcompile - it is intended to re-use previous place and route data as much as it possibly can - so critical paths will be retained. Run to run differences should be minimised (unless you are modifying your critical path logic). Hope this helps, JohnArticle: 118037
On 16 Apr., 17:51, "Benjamin Todd" <benjamin.toddREMOVEALLCAPIT...@cernREMOVEALLCAPITALS.ch> wrote: > > So what the f**k are you talking about? > > > Kolja Sulimma > > Pleasant! Errr. but I dont completely agree. > > DDR200 = PC1600 = 100MHz ... Well, both clock frequency and data rate are measured in Hertz. The OP did not say which 166MHz number he was talking about so it could have been both. AFAICT it could also be the number of alpha decays in the solder balls. KoljaArticle: 118038
On Apr 16, 1:13 pm, g.eckers...@ieee.org wrote: > It seems to work better (much better than 8.1), but seems to have a > few > issues that make it a bit hard to use. > > 1/ Sometimes it auto trims logic which is required - particularly > when it is associated with Jtag devices. This behaviour seems > unpredictable, and happens when completely unrelated logic is > moved around, or even when an identical logical expression > in vhdl is expressed differently. > 2/ Sometimes multiple contending tristate drivers are generated when > only > one exists. > This seems to depend on completely unrelated logic and also > seems to depend on the syntax level in vhdl where the driver is > declared. these are serious issues. You should open a webcase on xilinx.com and report them. I am often satisfied with their support. Be ready to submit your design, or even better just a small part of it showing the problems that you report.Article: 118039
On Apr 16, 4:34 am, "vlsi_learner" <baj...@gmail.com> wrote: > Hi all, > > My ASIC design requires dual port memories(one port R/W other port > only read) but there is a constraint on using it. > Instead I am planning to create this memory using single port RAM's. > > Writes to this memory take place at 60 Mhz while reads can occur at > freq varying from 5-30 Mhz. > > Is there some way out? At the very low write and read rates that you mention, just run the memory at 120 MHz cycles, and use every even numbered period to write, and the odd one to (potentially) read. This may need a little finesse if your reads are asynchronous, but would otherwise be simple and economical. Peter AlfkeArticle: 118040
On Apr 16, 10:02 am, Eric Brombaugh <ebrombaugh.inval...@earthlink.net> wrote: > That's true. I guess I could make it more consistent if I'll force only the location of BRAMs. However, a [good] timing driven placer should take care of that .... > What you need to do is put good timing exceptions into your constraints > file so that PAR doesn't expend effort trying to optimize timing on > paths that don't matter and can instead focus on the truly critical paths. > > I've found that identifying multi-cycle paths is a big help in getting > more consistent PAR results. Agreed. But in this design I don't have multi-cycle paths. > That said, If you're having trouble meeting timing with a 50MHz clock > constraint you may have some seriously long paths in your design. Adding > timing exceptions may not help and you might have some pipeline > optimization to do. To be honest, the design is using both edges of the clock so you can call it 100MHz if you want. The failing one is such a path, and it goes through [only] 4 levels of logic: [...] Requirement: 10.000ns Data Path Delay: 10.679ns (Levels of Logic = 4) Clock Path Skew: 0.000ns [...] Total 10.391ns (3.344ns logic, 7.047ns route) [...] --- mmihai http://www.delajii.net/consultingArticle: 118041
I had to implement a PLB master the other year for a project. To be
honest, it is actually easier if you just get the core connect spec and
write it your self.
In my case, I was only doing 64-bit transfers. The logic was actually
pretty simple. I spent a week with the IPIF and it never really worked
right. I told a co-worker that I did not think they ever tested the
IPIF master operation.
My own implementation only took a day or 2. Believe it or not the state
machine to do is pretty small.
LilacSkin wrote:
> Hi,
>
> I build a IPIF master with Create/Import Peripheral.
> I try the example write in the user_logic.vhd:
>
> -- Here's an example procedure in your software application to
> initiate a 4-byte
> -- write operation (single data beat) of this master model:
> -- 1. write 0x40 to the control register
> -- 2. write the source data address (local) to the ip2ip register
> -- 3. write the destination address (remote) to the ip2bus
> register
> -- - note: this address will be put on the target bus address
> line
> -- 4. write 0x0004 to the length register
> -- 5. write valid byte lane value to the be register
> -- - note: this value must be aligned with ip2bus address
> -- 6. write 0x0a to the go register, this will start the write
> operation
>
> My C:
>
> #include "xparameters.h"
> #include "xutil.h"
>
> int main (void) {
>
> volatile Xuint32* Data;
>
> Data=(Xuint32*) XPAR_IPIF_MASTER_0_BASEADDR;
>
> // contrôl register
> Data=(Xuint32*)(0x00+0x00);
> *(Data)=0x40;
>
> // source address
> Data=(Xuint32*)(0x00+0x04);
> *(Data)=XPAR_TEST_0_BASEADDR;
>
> //destination address
> Data=(Xuint32*)(0x00+0x04);
> *(Data)=XPAR_PLB_BRAM_IF_CNTLR_1_BASEADDR;
>
> // lengh register
> Data=(Xuint32*)(0x00+0x04);
> *(Data)=0x04;
>
> // BE register
> Data=(Xuint32*)(0x00+0x02);
> *(Data)=0xFF;
>
> // Go register
> Data=(Xuint32*)(0x00+0x01);
> *(Data)=0x0A;
>
> return 0;
> }
>
>
> I put one data in my TEST block, but nothing happened.
> I want to transfer the data from the TEST block to a BRAM with this
> IPIF, but i don't understand
> what address i need to put in my TEST block to access to my BRAM.
>
> Can you help me ????
> Thanks
>
Article: 118042Richard Klingler <richard_uclinux_net> writes: > Can for example Quartus or ispLever use the MAC address > of a Bluetooth or WLAN dongle so when I buy a new PC > I just need to move the Bluetooth/WLAN dongle? Altera and Lattice use flexlm. I have had difficulties in the past with machines with multiple NIC's to make flexlm select the correct one. I'm using a dedicated license server where the internal NIC is disabled and a separate PCI NIC. If the server breaks down I set up a new one and put the NIC into the new machine. PC's are much more likely to fail than NICs. Of course you need to have floating license for this type of setup. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 118043
On Apr 16, 6:43 am, "Paul" <pauljbenn...@gmail.com> wrote: > We're talking about the picoblaze here....the program space isn't > large > enough for ANYTHING to take weeks to write.... if it takes more than > two > hours to run out of program memory, you type too slow! Test and debug in a HLL on another platform is frequently a LOT faster than steping PB thru a simulator debugging your asm. ditto for long term maintainability by a broader spectrum of engineers.Article: 118044
I have put a debug monitor for the MPC5200 PPC processor for download (free for development purposes) at http://tgi-sci.com/tgi/download/m52.htm . Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------Article: 118045
On Apr 16, 1:39 pm, "mmihai" <iia...@yahoo.com> wrote: > [...] > Requirement: 10.000ns > Data Path Delay: 10.679ns (Levels of Logic = 4) > Clock Path Skew: 0.000ns > [...] > Total 10.391ns (3.344ns logic, > 7.047ns route) > [...] Inspired by a recent thread in this newsgroup (look for "Xilinx ISE 9.1 subject") I've tried "par" with different (default is 1) "cost table" values (-t option) and it seems this option helps in meeting the target timing. With "-t 2" I'm getting: Timing summary: --------------- Timing errors: 0 Score: 0 Constraints cover 70048 paths, 0 nets, and 5448 connections Design statistics: Minimum period: 19.892ns (Maximum frequency: 50.271MHz) Can anyone detail what "cost table" number is doing? Thanks, --- mmihai http://www.delajii.net/consultingArticle: 118046
A: Because I can read it 3 times faster. Especially when continually following a thread and when most people DON'T edit. Q: Why is TOP POSTING a GOOD thing. -- Greg "Petter Gustad" <newsmailcomp6@gustad.com> wrote in message news:7dodloghue.fsf@www.gratismegler.no... > A: Because it messes up the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing on usenet and in e-mail?Article: 118047
On Apr 17, 6:11 am, "tullio" <tullio.gra...@gmail.com> wrote: > On Apr 16, 1:13 pm, g.eckers...@ieee.org wrote: > > > It seems to work better (much better than 8.1), but seems to have a > > few > > issues that make it a bit hard to use. > > > 1/ Sometimes it auto trims logic which is required - particularly > > when it is associated with Jtag devices. This behaviour seems > > unpredictable, and happens when completely unrelated logic is > > moved around, or even when an identical logical expression > > in vhdl is expressed differently. > > 2/ Sometimes multiple contending tristate drivers are generated when > > only > > one exists. > > This seems to depend on completely unrelated logic and also > > seems to depend on the syntax level in vhdl where the driver is > > declared. > > these are serious issues. > You should open a webcase on xilinx.com and report them. I am often > satisfied with their support. > Be ready to submit your design, or even better just a small part of it > showing the problems that you report. Xilinx support has been excellent, and when I've submitted cases to them they have generally been resolved promply. I only submit cases when there does'nt seem to be a way around them. The issues I mention above would be known to Xilinx, as I have no doubt they do extensive benchmarking. Asking the user base for help on a net forum is often the best way to find tweaks to get around known problems. It would be good if Xilinx and other FPGA companies supported the development of open source tools for writing and programming. I have used only 2 devices, the xc2c64 cpld and the xc3s200 144 pin. Both have been excellent and the prices are low enough to make them well worth considering for low end applications. VHDL is a good tool for logic design. ISE produces good results, but is touchy, and its eccentricities add significant time to project development . Despite these issues I think FPGA's are a better choice than DSP's for many applications , and can save both development time and final cost now that the silicon has become much cheaper and better.Article: 118048
On Apr 16, 10:47 pm, Uwe Bonnes <b...@hertz.ikp.physik.tu- darmstadt.de> wrote: > B. Joshua Rosen <bjro...@polybuspleasedontspamme.com> wrote: > > > > > I've been trying to launch ISE (9.1SP3) and I get this error > > FATAL_ERROR:Portability:Port_ExecLoaderInit.c:117:1.4 - The executable > > </home/bjrosen/_pn> can't be found. The installation was not > > complete. > > Process will terminate. For more information on this error, please > > consult > > the Answers Database or open a WebCase with this project attached at > > http://www.xilinx.com/support. > > If I launch it from the $XILINX/bin/lin directory it works fine so it > > would appear to be some sort of search path problem but I've got > > everything in my paths, > > echo $PATH > > /usr/local/tools/Xilinx/bin/lin:/usr/local/tools/Xilinx/java/lin/jre/bin:/ > > usr/local/tools/Xilinx/chipscope/bin/lin:/usr/local/tools/Xilinx/bin/ > > lin64:.:/usr/local/tools/flexlm/bin:/usr/java/jre1.5.0_02/bin:/usr/local/ > > tools/hdlmaker_lib/i686/bin:/usr/local/tools/hdlmaker_lib/csh:/usr/local/ > > tools/jre1.5.0_10/bin:/usr/local/bin:/usr/bin:/sbin:/usr/sbin:/bin:/usr/ > > X11R6/bin:/usr/local/csh:/usr/local/sbin:/usr/local/tools/acrobat/bin:/ > > usr/local/tools/nc_sim/tools/bin > > echo $LD_LIBRARY_PATH > > /usr/local/tools/Xilinx/bin/lin:/usr/local/tools/Xilinx/java/lin/jre/lib:/ > > usr/local/tools/Xilinx/lib:/usr/local/tools/Xilinx/chipscope/bin/lin:/usr/ > > lib:/usr/local/lib:/usr/X11R6/lib:/usr/lib/xemacs:/usr/local/tools/ > > jre1.5.0_10/lib > > echo $XILINX > > /usr/local/tools/Xilinx > > Is there some missing variable that I need to set. > > I have following script in my nin directory: > #!/bin/bash > WEBROOT=/opt/web91 > sh $WEBROOT/settings.sh > $WEBROOT/bin/lin/ise > > And for impact: > #!/bin/bash > WEBROOT=/opt/web82 > sh $WEBROOT/settings.sh > LD_PRELOAD=/usr/local/lib/libusb-driver.so $WEBROOT/bin/lin/impact $@ > > The LD-PRELOAD is to get rid of this dammed windriver. > -- > Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- I've used both Debian and Ubuntu (as off installer CD). Both work fine. Yes , windriver sucks.Article: 118049
I want to define a type related to entity generics, like an array in
the following codes. But It seems I have no places to put those
subtype/type statements in the entity. I can not use package to define
those subtype/type since there are related to entity generics.
Any solution or idea?
Thanks a lot,
Z
04/16/07
===============
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity ir is
-- Here is not correct
-- subtype MY_UNSIGNED is unsigned(EL_SIZE-1 downto 0);
-- type MY_UNSIGNED_VECTOR is array(natural range<>) of
MY_UNSIGNED;
generic (
EL_SIZE : POSITIVE := 16;
EL_COUNT : POSITIVE := 8
);
-- Here is not correct either
-- subtype MY_UNSIGNED is unsigned(EL_SIZE-1 downto 0);
-- type MY_UNSIGNED_VECTOR is array(natural range<>) of
MY_UNSIGNED;
port (
val_b : out MY_UNSIGNED_VECTOR (0 to EL_COUNT-1);
clk_i : in std_logic
...
);
end ir;
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