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Eli Hughes wrote: > I had to implement a PLB master the other year for a project. To be > honest, it is actually easier if you just get the core connect spec and > write it your self. > > In my case, I was only doing 64-bit transfers. The logic was actually > pretty simple. I spent a week with the IPIF and it never really worked > right. I told a co-worker that I did not think they ever tested the > IPIF master operation. > > My own implementation only took a day or 2. Believe it or not the state > machine to do is pretty small. Eli, Just curious, did you debug it with HDL simulation or chipscope?Article: 118051
cpandya@yahoo.com wrote: > I would like to know if you have used the High speed FPGA Tranceivers > for source synchronous bus application. In my application, I have 20 > bit outgoing and 20 bit incoming bus. Is it possible to do bit to > forwarded clock alignement, I was thinking about using precision delay > element of 5 ns resolutoin with dynamic range of 3 ns. The data rate > I am trying to reach is 6.375 Gbps. Altera Stratix2 GX supports 20 > transceivers at 6.375 Gbps. > > I would like to get your feedback and share your experience > You might check out xilinx app notes xapp265, xapp622 among others. -JeffArticle: 118052
On Apr 11, 2:12 am, "Allen" <lphp...@gmail.com> wrote: > On Mar 29, 10:52 pm, "John McCaskill" <junkm...@fastertechnology.com> > wrote: > > > > > On Mar 29, 12:45 am, "Allen" <lphp...@gmail.com> wrote: > > > > On Mar 25, 8:39 pm, "John McCaskill" <junkm...@fastertechnology.com> > > > wrote: > > > > > On Mar 25, 12:32 am, "Allen" <lphp...@gmail.com> wrote: > > > > > > On Mar 23, 8:33 pm, Zara <me_z...@dea.spamcon.org> wrote: > > > > > > > On 23 Mar 2007 05:13:46 -0700, "Allen" <lphp...@gmail.com> wrote: > > > > > > > >hi all, > > > > > > > >first, i am sorry for my poor English. > > > > > > > >i use EDK 7.1i and ISE 7.1i. > > > > > > > >imported custom peripheral with PLB Master Interface ( not from IFIP ) > > > > > > >into my .xps project after overcame several problems. > > > > > > > >In the step " generate netlist " there has no error or warning. > > > > > > > >but in the step "Generate Bitstream",i got a error message "ERROR!! > > > > > > >NgdBuild:455 plb_M_ABUS<62> has multiple driver(s)": return code 2 > > > > > > >abort. > > > > > > > >already search this problem in xilix's answer database and tried > > > > > > >modify the parameter of C_BaseAddr, but it is still stuck here. > > > > > > > >does anyone meet this problem before? > > > > > > > >thanks in advance. > > > > > > > I always got that messaghe when I had some signal with two outputs > > > > > > connected to it. That seems your case, in your plb address bus, master > > > > > > interface. > > > > > > > Best regards, > > > > > > > Zara- Hide quoted text - > > > > > > > - Show quoted text - > > > > > > Thanks for your reply. > > > > > > so it might mean something wrong during import of custom peripheral? > > > > > > but in 64-bit PLB protocol, the address width is 32-bit. > > > > > > i already use (C_PLB_AWIDTH-1) to replace with constant "31" in my > > > > > port declaration. > > > > > > do anything i could try to solve this problem? > > > > > > thank you :-) > > > > > The PLB address width is 32 bits. However, the way that all the bus > > > > signals are connected to the PLB IP is that they are concatenated > > > > together. So if you look at the MPD file for the PLB you will see that > > > > it defines the bus width to be 32 bits times the number of masters: > > > > > PORT M_ABus = M_ABus, DIR = I, VEC = [0: > > > > (C_PLB_NUM_MASTERS*C_PLB_AWIDTH)-1] > > > > > So the signal plb_M_ABUS<62> is bit 30 of the second master. Look to > > > > see if your core has been assigned the second master slot on the PLB > > > > bus. Assuming that is the case, find what two sources are driving bit > > > > 30 of the address. > > > > > Assuming that you left the name of your EDK project as system.xmp, > > > > when you tell EDK to generate a netlist it will create a top level hdl > > > > file named either system.vhd or system.v depending on your tool > > > > settings. You can look at this file to see how EDK has connected the > > > > cores to the PLB. > > > > > It has been a while since I had to find a multi source signal, but I > > > > think that XST will produce a warning about it in its report and tell > > > > you what the multiple soures are. Look in the synthesis report file > > > > for the appropriate core and see if it tells you what the source of > > > > the problem is. > > > > > Since you are creating your own interface design instead of using the > > > > IPIF, are you using the bus functional models in your simulations? I > > > > use these, and they make the job much easier. I think it was not > > > > until EDK 8.1 that they were integrated into EDK itself, but I was > > > > able to use the CoreConnect tool kit directly from IBM in some of our > > > > early stuff. The bus monitors will tell you as soon as your core has > > > > done something wrong, so you do not have to track the source of the > > > > problem back from when the symptoms show up. > > > > > Regards, > > > > > John McCaskillwww.fastertechnology.com-Hidequotedtext - > > > > > - Show quoted text - > > > > Thanks for your reply. :-) > > > > Where i could see the second master is who( power pc or custom > > > peripheral ... etc)? > > > I don't know where to check this. > > > While there may be an easier way, you can just look at a PLB master > > signal that is not a vector. For example, if you look at plb_M_RNW in > > your system.vhd you will see that it is defined as: > > > signal plb_M_RNW : std_logic_vector(0 to 2) > > > The entire vector is an input to the plb_wrapper. plb_M_RNW(0) will go > > to PLB master 0, plb_M_RNW(1) will go to PLB master 1, etc. > > > > I opened the system.vhd to see who connect to the plb_M_Abus. > > > "PowerPC" have 2 ports and Custom peripheral has 1 port connect to the > > > plb_M_ABus. > > > Next step, I am going to find the XST report file to see who drive the > > > plb_M_ABUS<62>. > > > No offense intended, but with just the PowerPC, and your new custom > > peripheral on the PLB bus the odds are that your peripheral is the > > source of the problem. Take a look at the synthesis report for it. > > In EDK, in the "Project Information Area" pane, and the Project tab, > > expand the "Report Files" selection. Find the one for your peripheral > > and look through it. I think there should be a warning about multiple > > sources driving a destination at this point. If you do not see it > > there, try looking through the implementation/xflow.log file in the > > "Log Files" section. > > > > I didn't run the simulation of this platform. I heard the "bus > > > functional model" before, but I don't understand how to use it. Would > > > you like to give any information about this one? > > > Take a look at: > > >http://www.xilinx.com/ise/embedded/edk6_3docs/bfm_simulation.pdf > > > This link is for the EDK 6.3 version of the documentation, but you > > should have a more recent version in your EDK distribution at $EDK/doc/ > > bfm_simulation.pdf. > > > One of the main things that I like about using the bus functional > > models is that the bus monitors tell you when a error occurred in the > > simulation, and what the error was. This saves you the effort of > > having to search backwards from where the symptoms of the error show > > up to figure our what has gone wrong. > > > > In addition the error"NgdBuild 455", there are several warnings "SFF > > > Primitive", i didn't find this on the Xilinx answer database.. maybe > > > this warning has something to do with the error. > > > > Thank you very much~ > > > Regards, > > > John McCaskillwww.fastertechnology.com-Hide quoted text - > > > - Show quoted text - > > Thank in advance. > > I check the synthesis report and I found something in implementation/ > xflow.log file > > ERROR:NgdBuild:455 - logical net 'plb_M_ABus<62>' has multiple > driver(s): > pin G on block ppc405_0/XST_GND with type GND, > pin G on block dma_mci_top_0/XST_GND with type GND, > pin P on block ppc405_0/XST_VCC with type VCC, > pin G on block plb2opb/XST_GND with type GND, > pin O on block plb2opb/plb2opb/I_BGO_addrAck with type LUT4, > pin G on block plb_bram_if_cntlr_1/XST_GND with type GND, > pin P on block plb_bram_if_cntlr_1/XST_VCC with type VCC > > There are 7 driver to drive this node and the dma_mci_top is the > custom peripheral. > > I have no idea about this situation. how come does it? I only import > the custom peripheral and create a platform. > > Does it any problem happend at the process of "Import Custom > Peripheral" ? > 'cause, during the import procedure, I need to set some bus parameter, > like C_PLB_NUM_MASTER...etc. > I try to find document on the Xilinx website, but I didn't find any > tutorail about the Import procedure. > > Would you like to give me any hints for solving this problem. > > Thank you very much. I used the import wizard just a few times to see what it did, then I started creating all my peripherals by hand, so I do not remember how it works very well. But, C_PLB_NUM_MASTER is a parameter/generic that needs to be set by EDK when it creates all the wrapper files for the PLB peripherals. Did you set it to a numeric value? EDK includes the source code and support files for the cores that it comes with. Look through them for examples of how to create a PLB slave. If I remember correctly, the multi port memory controller reference design also has a PLB slave that is not based on the IPIF, and is simpler. Regards, John McCaskill www.fastertechnology.comArticle: 118053
Hi Petter, I was trying to do the same, using 2 SPRAM's & writing to both of them simultaneouly using same address & data. addr_0 = ~pa_rwb ? pa_wraddr : pa_rdaddr; (port A is R/W port) addr_1 = ~pa_rwb ? pa_wraddr : (pb_rwb ? pb_rdaddr : 8'b0); (port B is read only port) In this case , if there is a write from port A then we cannot read from the other port.Is this dual port functionality? Petter Gustad wrote: > "vlsi_learner" <bajajk@gmail.com> writes: > > > My ASIC design requires dual port memories(one port R/W other port > > only read) but there is a constraint on using it. > > Instead I am planning to create this memory using single port RAM's. > > You an use two RAMs if you have enough RAM availabe in your > ASIC. Simply write into both RAMs using the same address and data. > > Petter > -- > A: Because it messes up the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing on usenet and in e-mail?Article: 118054
In a dual-ported RAM, you have two independent access mechanism to the common data, so you can read while you are writing. (In a "true dual- ported RAM" you can also have two independent write, or two independent read opertions going on simultaneously) But you still have to avoid simultaneous read and write to the same location. (Contention) You avoid (almost) all these problem with Time-Division Multiplexing, as I mentioned in my previous post. Given your extremely slow speed, that's the way to go! Peter Alfke On Apr 16, 10:04 pm, vlsi_learner <baj...@gmail.com> wrote: > Hi Petter, > > I was trying to do the same, using 2 SPRAM's & writing to both of them > simultaneouly using same address & data. > > addr_0 = ~pa_rwb ? pa_wraddr : pa_rdaddr; (port A is R/W port) > > addr_1 = ~pa_rwb ? pa_wraddr : (pb_rwb ? pb_rdaddr : 8'b0); (port B > is read only port) > > In this case , if there is a write from port A then we cannot read > from the other port.Is this dual port > functionality? > > Petter Gustad wrote: > > "vlsi_learner" <baj...@gmail.com> writes: > > > > My ASIC design requires dual port memories(one port R/W other port > > > only read) but there is a constraint on using it. > > > Instead I am planning to create this memory using single port RAM's. > > > You an use two RAMs if you have enough RAM availabe in your > > ASIC. Simply write into both RAMs using the same address and data. > > > Petter > > -- > > A: Because it messes up the order in which people normally read text. > > Q: Why is top-posting such a bad thing? > > A: Top-posting. > > Q: What is the most annoying thing on usenet and in e-mail?Article: 118055
Hum, you had to write a plb arbiter ? Can you share your HDL code ? thanks a lot !Article: 118056
Hi, I am using the UP2 development board from Altera. I have programmed a simple ALU in it. I have done some hardware tests on it through its expansion slots but the results are inconsistent. To perform the tests, I connect the expansion slots with IDE cables to a verabod in which i have soldered many switches and LEDs. However the results were inconsistent, sometimes I couldn't load the the values into the bus at load at all. Other times when i load the upper bits, the lower bits get erased. Any inputs on this? I was also thinking of interfacing it with a control card made entirely of TTL chips. Power source is taken from the TTL control card. Any inputs on the potential problems I might face? Thanks! JalenArticle: 118057
Dear all, I am working with an ML405 and trying to put together a project of my own that uses the plb_tft_cntlr_ref IP from the example project. I tried to import the IP using the "Create or Import Peripheral" wizard but it complains that there are a bunch of signals missing that are needed by the PLB. I've taken a look at the source and it certainly appears to be the case (caveat: I'm very inexperienced with this and I don't pretend to understand the PLB). What do I need to do to get this IP up and running in my project in the exact same way it was in the example? What am I doing wrong? This is all in EDK 8.2i BTW. Thanks in advance, -- PeterArticle: 118058
On Apr 17, 11:23 am, John McCaskill <junkm...@fastertechnology.com> wrote: > On Apr 11, 2:12 am, "Allen" <lphp...@gmail.com> wrote: > > > > > > > On Mar 29, 10:52 pm, "John McCaskill" <junkm...@fastertechnology.com> > > wrote: > > > > On Mar 29, 12:45 am, "Allen" <lphp...@gmail.com> wrote: > > > > > On Mar 25, 8:39 pm, "John McCaskill" <junkm...@fastertechnology.com> > > > > wrote: > > > > > > On Mar 25, 12:32 am, "Allen" <lphp...@gmail.com> wrote: > > > > > > > On Mar 23, 8:33 pm, Zara <me_z...@dea.spamcon.org> wrote: > > > > > > > > On 23 Mar 2007 05:13:46 -0700, "Allen" <lphp...@gmail.com> wrote: > > > > > > > > >hi all, > > > > > > > > >first, i am sorry for my poor English. > > > > > > > > >i use EDK 7.1i and ISE 7.1i. > > > > > > > > >imported custom peripheral with PLB Master Interface ( not from IFIP ) > > > > > > > >into my .xps project after overcame several problems. > > > > > > > > >In the step " generate netlist " there has no error or warning. > > > > > > > > >but in the step "Generate Bitstream",i got a error message "ERROR!! > > > > > > > >NgdBuild:455 plb_M_ABUS<62> has multiple driver(s)": return code 2 > > > > > > > >abort. > > > > > > > > >already search this problem in xilix's answer database and tried > > > > > > > >modify the parameter of C_BaseAddr, but it is still stuck here. > > > > > > > > >does anyone meet this problem before? > > > > > > > > >thanks in advance. > > > > > > > > I always got that messaghe when I had some signal with two outputs > > > > > > > connected to it. That seems your case, in your plb address bus, master > > > > > > > interface. > > > > > > > > Best regards, > > > > > > > > Zara- Hide quoted text - > > > > > > > > - Show quoted text - > > > > > > > Thanks for your reply. > > > > > > > so it might mean something wrong during import of custom peripheral? > > > > > > > but in 64-bit PLB protocol, the address width is 32-bit. > > > > > > > i already use (C_PLB_AWIDTH-1) to replace with constant "31" in my > > > > > > port declaration. > > > > > > > do anything i could try to solve this problem? > > > > > > > thank you :-) > > > > > > The PLB address width is 32 bits. However, the way that all the bus > > > > > signals are connected to the PLB IP is that they are concatenated > > > > > together. So if you look at the MPD file for the PLB you will see that > > > > > it defines the bus width to be 32 bits times the number of masters: > > > > > > PORT M_ABus = M_ABus, DIR = I, VEC = [0: > > > > > (C_PLB_NUM_MASTERS*C_PLB_AWIDTH)-1] > > > > > > So the signal plb_M_ABUS<62> is bit 30 of the second master. Look to > > > > > see if your core has been assigned the second master slot on the PLB > > > > > bus. Assuming that is the case, find what two sources are driving bit > > > > > 30 of the address. > > > > > > Assuming that you left the name of your EDK project as system.xmp, > > > > > when you tell EDK to generate a netlist it will create a top level hdl > > > > > file named either system.vhd or system.v depending on your tool > > > > > settings. You can look at this file to see how EDK has connected the > > > > > cores to the PLB. > > > > > > It has been a while since I had to find a multi source signal, but I > > > > > think that XST will produce a warning about it in its report and tell > > > > > you what the multiple soures are. Look in the synthesis report file > > > > > for the appropriate core and see if it tells you what the source of > > > > > the problem is. > > > > > > Since you are creating your own interface design instead of using the > > > > > IPIF, are you using the bus functional models in your simulations? I > > > > > use these, and they make the job much easier. I think it was not > > > > > until EDK 8.1 that they were integrated into EDK itself, but I was > > > > > able to use the CoreConnect tool kit directly from IBM in some of our > > > > > early stuff. The bus monitors will tell you as soon as your core has > > > > > done something wrong, so you do not have to track the source of the > > > > > problem back from when the symptoms show up. > > > > > > Regards, > > > > > > John McCaskillwww.fastertechnology.com-Hidequotedtext- > > > > > > - Show quoted text - > > > > > Thanks for your reply. :-) > > > > > Where i could see the second master is who( power pc or custom > > > > peripheral ... etc)? > > > > I don't know where to check this. > > > > While there may be an easier way, you can just look at a PLB master > > > signal that is not a vector. For example, if you look at plb_M_RNW in > > > your system.vhd you will see that it is defined as: > > > > signal plb_M_RNW : std_logic_vector(0 to 2) > > > > The entire vector is an input to the plb_wrapper. plb_M_RNW(0) will go > > > to PLB master 0, plb_M_RNW(1) will go to PLB master 1, etc. > > > > > I opened the system.vhd to see who connect to the plb_M_Abus. > > > > "PowerPC" have 2 ports and Custom peripheral has 1 port connect to the > > > > plb_M_ABus. > > > > Next step, I am going to find the XST report file to see who drive the > > > > plb_M_ABUS<62>. > > > > No offense intended, but with just the PowerPC, and your new custom > > > peripheral on the PLB bus the odds are that your peripheral is the > > > source of the problem. Take a look at the synthesis report for it. > > > In EDK, in the "Project Information Area" pane, and the Project tab, > > > expand the "Report Files" selection. Find the one for your peripheral > > > and look through it. I think there should be a warning about multiple > > > sources driving a destination at this point. If you do not see it > > > there, try looking through the implementation/xflow.log file in the > > > "Log Files" section. > > > > > I didn't run the simulation of this platform. I heard the "bus > > > > functional model" before, but I don't understand how to use it. Would > > > > you like to give any information about this one? > > > > Take a look at: > > > >http://www.xilinx.com/ise/embedded/edk6_3docs/bfm_simulation.pdf > > > > This link is for the EDK 6.3 version of the documentation, but you > > > should have a more recent version in your EDK distribution at $EDK/doc/ > > > bfm_simulation.pdf. > > > > One of the main things that I like about using the bus functional > > > models is that the bus monitors tell you when a error occurred in the > > > simulation, and what the error was. This saves you the effort of > > > having to search backwards from where the symptoms of the error show > > > up to figure our what has gone wrong. > > > > > In addition the error"NgdBuild 455", there are several warnings "SFF > > > > Primitive", i didn't find this on the Xilinx answer database.. maybe > > > > this warning has something to do with the error. > > > > > Thank you very much~ > > > > Regards, > > > > John McCaskillwww.fastertechnology.com-Hidequoted text - > > > > - Show quoted text - > > > Thank in advance. > > > I check the synthesis report and I found something in implementation/ > > xflow.log file > > > ERROR:NgdBuild:455 - logical net 'plb_M_ABus<62>' has multiple > > driver(s): > > pin G on block ppc405_0/XST_GND with type GND, > > pin G on block dma_mci_top_0/XST_GND with type GND, > > pin P on block ppc405_0/XST_VCC with type VCC, > > pin G on block plb2opb/XST_GND with type GND, > > pin O on block plb2opb/plb2opb/I_BGO_addrAck with type LUT4, > > pin G on block plb_bram_if_cntlr_1/XST_GND with type GND, > > pin P on block plb_bram_if_cntlr_1/XST_VCC with type VCC > > > There are 7 driver to drive this node and the dma_mci_top is the > > custom peripheral. > > > I have no idea about this situation. how come does it? I only import > > the custom peripheral and create a platform. > > > Does it any problem happend at the process of "Import Custom > > Peripheral" ? > > 'cause, during the import procedure, I need to set some bus parameter, > > like C_PLB_NUM_MASTER...etc. > > I try to find document on the Xilinx website, but I didn't find any > > tutorail about the Import procedure. > > > Would you like to give me any hints for solving this problem. > > > Thank you very much. > > I used the import wizard just a few times to see what it did, then I > started creating all my peripherals by hand, so I do not remember how > it works very well. But, C_PLB_NUM_MASTER is a parameter/generic that > needs to be set by EDK when it creates all the wrapper files for the > PLB peripherals. Did you set it to a numeric value? > > EDK includes the source code and support files for the cores that it > comes with. Look through them for examples of how to create a PLB > slave. If I remember correctly, the multi port memory controller > reference design also has a PLB slave that is not based on the IPIF, > and is simpler. > > Regards, > > John McCaskillwww.fastertechnology.com- Hide quoted text - > > - Show quoted text - Thank you very much. I set C_PLB_NUM_MASTER=2 in the verilog design. Does EDK change this parameter during creating platform? I wil go to check the examples. Besides, I saw an example that the custom peripheral is imported inot EDK without bus interface. How could I do this? I search several document, I don't see something to do with it. Thanks again Sincerely.Article: 118059
To build my PLB master, I only need that ports ??? PLB Master n Interface PLB-to-Master N PLB_MnWrDAck PLB_MnRdAck PLB_MnAddrAck PLB_MnRearbitrate PLB_MnTimeout Master n-to-PLB Mn_request Mn_priority(0:1) Mn_RNW Mn_size(0:3) Mn_rdBurst Mn_abort Mn_wrBurst Mn_ABus(0:31) Mn_UABus(0:31) PLB Slave n Interfaces PLB-to-slave n PLB_RNW PLB_abort PLB_wrBurst PLB_rdBurst PLB_masterID(0:2) PLB_PAValid PLB_SAValid PLB_ABus(0:31) PLB_UABus(0:31) Slave n-to-PLB PLB Sln_wait Sln_AddrAck Sln_rearbitrate Sln_rdComp Sln_rdDAck Sln_wrComp Sln_wrDAck Where are the ports in the IBM datasheet ? PLB_pendpri PLB_penreq PLB_reqpri PLB_size PLB_type PLB_rdPrim PLB_abort PLB_buslocked PLB_masterID PLB_MSize PLB_compress PLB_guarded PLB_lockerrr PLB_MErr, PLB_MBusy.......Article: 118060
> You probably do not want to put the delays within your enable block... and
> like the write, you probably want one register level on the address. With
> both tweaks, the process should look like this:
>
> process (rd_clk)
> begin
> if (rd_clk'event and rd_clk = '1') then
> if (ce = '1') then
> rd_en1 <= rd_en;
> rd_addr1 <= rd_addr;
> else
> rd_en1 <= '0';
> end if;
>
> if (rd_en1 = '1') then
> dout2 <= mem_array(conv_integer('0' & rd_addr1));
> end if;
>
> dout1 <= dout2;
> dout <= dout1;
> end if;
> end process;
>
>
Hmm why in this case the
dout1 <= dout2;
dout <= dout1;
is being placed outside the enable block then? Because I do not want any
latency when retrieving data?
I hope this does not add on any timing delay, if not I could be keeping on
adding register level in vain.
> Since you are new to FPGAs, it is normal that you are not (yet) familiar
> with the fundamentals of working around common design issues... but most
> of these you should be able to deduce by reading your static timing
> analysis
> and thinking about the simplest ways to fix the problems it reveals.
Hmm yah, well I really still have alot to learn in the future. Well, really
happy now at least I have learnt something about adding register levels to
solve timing issue problems.
And really thanks alot for the code, it was spot on. I guess I could never
figured the part about the address and enable needing to be delayed myself.
Hmm come to think of it, it looks kind of stupid to do reassignment of
signals in the same block.
From there on, I found out that I need to select register balancing => Yes
in synthesis option.
After doing so, the timing code really dropped by more significant amounts.
Oh btw I have then tried to add on more register levels.
Have tried some structures, and I deduce this coding should be logical.
Wonder if there is anything wrong. The lowest I have brought the timing down
is a slack of about 1ns
architecture rtl of dp2_bram is
type mem_array_type is array (0 to (mem_size - 1)) of
std_logic_vector((data_width - 1) downto 0);
signal mem_array : mem_array_type;
attribute ram_style : string;
attribute ram_style of mem_array : signal is "pipe_distributed";
signal wr_en1 : std_logic;
signal wr_addr1 : std_logic_vector((LOG2_BASE(mem_size) - 1) downto 0);
signal din1 : std_logic_vector((data_width - 1) downto 0);
signal wr_en2 : std_logic;
signal wr_addr2 : std_logic_vector((LOG2_BASE(mem_size) - 1) downto 0);
signal din2 : std_logic_vector((data_width - 1) downto 0);
signal wr_en3 : std_logic;
signal wr_addr3 : std_logic_vector((LOG2_BASE(mem_size) - 1) downto 0);
signal din3 : std_logic_vector((data_width - 1) downto 0);
signal rd_en1 : std_logic;
signal rd_addr1 : std_logic_vector((LOG2_BASE(mem_size) - 1) downto 0);
signal rd_en2 : std_logic;
signal rd_addr2 : std_logic_vector((LOG2_BASE(mem_size) - 1) downto 0);
signal rd_en3 : std_logic;
signal rd_addr3 : std_logic_vector((LOG2_BASE(mem_size) - 1) downto 0);
signal dout2 : std_logic_vector((data_width - 1) downto 0);
signal dout1 : std_logic_vector((data_width - 1) downto 0);
signal dout3 : std_logic_vector((data_width - 1) downto 0);
signal ce2 : std_logic;
signal ce3 : std_logic;
begin
process (wr_clk)
begin
if (wr_clk'event and wr_clk = '1') then
if (ce = '1') then
ce2 <= '1';
wr_en1 <= wr_en;
wr_addr1 <= wr_addr;
din1 <= din;
else
ce2 <= '0';
end if;
if (ce2 = '1') then
ce3 <= '1';
wr_en2 <= wr_en1;
wr_addr2 <= wr_addr1;
din2 <= din1;
else
ce3 <= '0';
end if;
if (ce3 = '1') then
wr_en3 <= wr_en2;
wr_addr3 <= wr_addr2;
din3 <= din2;
else
wr_en3 <= '0';
end if;
if (wr_en3 = '1') then
mem_array(conv_integer('0' & wr_addr3)) <= din3;
end if;
end if;
end process;
process (rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if (ce = '1') then
ce2 <= '1';
rd_en1 <= rd_en;
rd_addr1 <= rd_addr;
else
ce2 <= '0';
end if;
if (ce2 = '1') then
ce3 <= '1';
rd_en2 <= rd_en1;
rd_addr2 <= rd_addr1;
else
ce3 <= '0';
end if;
if (ce3 = '1') then
rd_en3 <= rd_en2;
rd_addr3 <= rd_addr2;
else
rd_en3 <= '0';
end if;
if (rd_en3 = '1') then
dout3 <= mem_array(conv_integer('0' & rd_addr3));
end if;
dout2 <= dout3;
dout1 <= dout2;
dout <= dout1;
end if;
end process;
end rtl;
sorry a bit long to be posted though
Article: 118061Hi, I've a question about ISE9.1 Tcl scripts. Is it possible to include `define in Tcl project scripts to determine module to synthesize according to `ifdef... `endif placed in the verilog sources ? Thank you by advance, Bests regards. Michel.Article: 118062
On 2007-04-17, michel.talon@gmail.com <michel.talon@gmail.com> wrote: > Hi, > > I've a question about ISE9.1 Tcl scripts. Is it possible to include > `define in Tcl project scripts to determine module to synthesize > according to `ifdef... `endif placed in the verilog sources ? I don't think xst accepts anything like -DCLOCKED=1 (as you can do in the command line of most C-compilers). However, there are other ways to do it. Lets say that you have a file test.v which contains the following: `ifdef CLOCKED always @(posedge clk) b <= a; `else always @* b = a; `endif If you now want CLOCKED to be defined in test.v you can write a file defines.v that contains `define CLOCKED and make sure that xst reads it before any other file. CLOCKED will now be defined in all Verilog files that are read after defines.v. (Unless it is explicitly undefined.) Personally I think this behaviour of Verilog synthesizers is a bit non-intuitive but IIRC it is specified that way in the Verilog standard. You are going to have to think about how to keep your design and your simulation in sync if you are going to do something like this though. /AndreasArticle: 118063
zhangpei@gmail.com wrote:
> I want to define a type related to entity generics, like an array in
> the following codes. But It seems I have no places to put those
> subtype/type statements in the entity. I can not use package to define
> those subtype/type since there are related to entity generics.
>
> Any solution or idea?
>
> Thanks a lot,
>
> Z
> 04/16/07
>
> ===============
> library IEEE;
> use IEEE.std_logic_1164.all;
> use IEEE.std_logic_arith.all;
> use IEEE.std_logic_unsigned.all;
>
> entity ir is
> -- Here is not correct
> -- subtype MY_UNSIGNED is unsigned(EL_SIZE-1 downto 0);
> -- type MY_UNSIGNED_VECTOR is array(natural range<>) of
> MY_UNSIGNED;
> generic (
> EL_SIZE : POSITIVE := 16;
> EL_COUNT : POSITIVE := 8
> );
> -- Here is not correct either
> -- subtype MY_UNSIGNED is unsigned(EL_SIZE-1 downto 0);
> -- type MY_UNSIGNED_VECTOR is array(natural range<>) of
> MY_UNSIGNED;
> port (
> val_b : out MY_UNSIGNED_VECTOR (0 to EL_COUNT-1);
> clk_i : in std_logic
> ...
> );
> end ir;
>
Hi Z,
you must put the declarations in a package, e.g.
library ieee;
use ieee.std_logic_arith.all; -- prefer numeric_std, it's a standard
package mytypes is
subtype MY_UNSIGNED is unsigned(EL_SIZE-1 downto 0);
type MY_UNSIGNED_VECTOR is array(natural range<>) of MY_UNSIGNED;
end package mytypes;
Of course you then don't have access to the generic. So you need to
fix the generic size using a constant or the subtype itself, e.g.
package mytypes is
constant EL_SIZE : positive := 10;
subtype MY_UNSIGNED is unsigned(EL_SIZE-1 downto 0);
type MY_UNSIGNED_VECTOR is array(natural range<>) of MY_UNSIGNED;
end package mytypes;
You must make the package visible in front of the entity of course, e.g.
library mylib;
use mylib.mytypes.all;
library ieee;
...
entity...
assuming you compiled the package into library 'mytypes'
Does that help?
In Accellera VHDL2006 you can have package generics, which would be a
neater solution - but your tools must have 2006 support.
regards
Alan
--
Alan Fitch
Doulos
http://www.doulos.com
Article: 118064Ok, thanks :) But why is slew rate related to resistance to short-circuits ?Article: 118065
I had about the same experience with an OPB master peripheral - the IPIF implementation did not work properly so I build my own. The PLB SG/DMA IPIF implementation probably works, but you do not access it properly. Read SG/DMA datasheet for register definitions. At first you need a reliable read/writes to registers; I sugesst you use XIo_In32 and XIo_Out32 functions to manipulate with memory mapped peripherals to avoid any errors. You also consider disabling PPC cache to avoid reading cached data instead of RAM contents. If you consider building a PLB DMA peripheral you first need a slave pripheral (i prefer the simplest DCR bus) for register access. Then you add a PLB bus connection to incorporate your PLB DMA engine. If you want to succeed you better read througly the PLB specification: http://www-306.ibm.com/chips/techlib/techlib.nsf/techdocs/3BBB27E5BCC165BA87256A2B0064FFB4 To implement what you want and to remove all the bugs I think it is more than a 2 days job. Cheers, GuruArticle: 118066
"Sebastien Bourdeauducq" <sebastien.bourdeauducq@gmail.com> wrote in message news:1176730853.436614.116100@b75g2000hsg.googlegroups.com... > Hi, > > I intend to wire up an Altera Cyclone 2 to a NET2272 USB controller. > The bus of the NET2272 is similar to that of a parallel RAM, with > address lines, bidirectional data bus, and read/write strobe signals. > > I'm concerned about the electrical safety of the bidirectional data > lines. If I mess up the FPGA program and assert the read strobe signal > while the data lines are set as outputs, this may damage (expensive) > parts, right ? Do you know of a simple way to avoid this ? Putting > resistors in series on the data lines ? > > Regards, > > Sebastien > Hi Sebastien, Normally, contention will not break the part. AFAICR, I've never damaged a part this way in the (far too) many years I've been playing this game. The I/O pins can withstand a short to ground or short to Vdd, so contention isn't going to permanently damage anything, especially if you don't leave anything long enough to get too hot. Anyway, you'll have simulated everything first, so there'll be no problem, right? ;-) I'm not entirely convinced that Daniel's suggestion will make much difference to the reliability. The current drive is set by turning on more or fewer drive transistors. By setting the part to 4-8mA, most of the drive transistors are off, but the ones that are on will still be taking the same individual current as when they are all on, so are just as likely to locally overheat. In fact, setting the drive current to a high value may protect the FPGA better as the IC it's contending against might be the current limiting device and this current will be spread over more drive transistors. Of course, the other part will then be stressed more. OTOH, the FPGA will, overall, warm up more with more power being dissipated. All in all, you're very unlikely to break anything. Whatever, simulate your design, and avoid the situation altogether! HTH, Syms.Article: 118067
"Peter Mendham" <petermendham@NOCANNEDMEAT.computing.dundee.ac.uk> wrote in
message news:f01v8b$r5q$1@dux.dundee.ac.uk...
> Dear all,
>
> I am working with an ML405 and trying to put together a project of my own
> that uses the plb_tft_cntlr_ref IP from the example project. I tried to
> import the IP using the "Create or Import Peripheral" wizard but it
> complains that there are a bunch of signals missing that are needed by the
> PLB.
You don't need to do that. All you need to do is drop the plb_tft_cntlr_ref
pcore into the "pcores" directory in your project. Then (once you've closed
and re-opened the project so XPS re-reads the directory) you'll see it in
the peripheral repository and you can just add it to the project like any
other piece of IP in the library.
Cheers,
-Ben-
Article: 118068Hi peter, If I understand correctly, you are saying that I should use double clock rate & then time multiplex the ports i.e write on even clock into a single port RAM & read on the odd clock from the SPRAM. But what about reads at varying freq ( 5 - 30 Mhz) Peter Alfke wrote: > In a dual-ported RAM, you have two independent access mechanism to the > common data, so you can read while you are writing. (In a "true dual- > ported RAM" you can also have two independent write, or two > independent read opertions going on simultaneously) But you still have > to avoid simultaneous read and write to the same location. > (Contention) > You avoid (almost) all these problem with Time-Division Multiplexing, > as I mentioned in my previous post. > Given your extremely slow speed, that's the way to go! > Peter Alfke > > > On Apr 16, 10:04 pm, vlsi_learner <baj...@gmail.com> wrote: > > Hi Petter, > > > > I was trying to do the same, using 2 SPRAM's & writing to both of them > > simultaneouly using same address & data. > > > > addr_0 = ~pa_rwb ? pa_wraddr : pa_rdaddr; (port A is R/W port) > > > > addr_1 = ~pa_rwb ? pa_wraddr : (pb_rwb ? pb_rdaddr : 8'b0); (port B > > is read only port) > > > > In this case , if there is a write from port A then we cannot read > > from the other port.Is this dual port > > functionality? > > > > > Petter Gustad wrote: > > > "vlsi_learner" <baj...@gmail.com> writes: > > > > > > My ASIC design requires dual port memories(one port R/W other port > > > > only read) but there is a constraint on using it. > > > > Instead I am planning to create this memory using single port RAM's. > > > > > You an use two RAMs if you have enough RAM availabe in your > > > ASIC. Simply write into both RAMs using the same address and data. > > > > > Petter > > > -- > > > A: Because it messes up the order in which people normally read text. > > > Q: Why is top-posting such a bad thing? > > > A: Top-posting. > > > Q: What is the most annoying thing on usenet and in e-mail?Article: 118069
Hi Peter, Another thing, what if I dont have the double clock available in the design? Thanks in advance for your help vlsi_learner wrote: > Hi peter, > > If I understand correctly, you are saying that I should use double > clock rate & then time multiplex the ports i.e > write on even clock into a single port RAM & read on the odd clock > from the SPRAM. > But what about reads at varying freq ( 5 - 30 Mhz) > > Peter Alfke wrote: > > In a dual-ported RAM, you have two independent access mechanism to the > > common data, so you can read while you are writing. (In a "true dual- > > ported RAM" you can also have two independent write, or two > > independent read opertions going on simultaneously) But you still have > > to avoid simultaneous read and write to the same location. > > (Contention) > > You avoid (almost) all these problem with Time-Division Multiplexing, > > as I mentioned in my previous post. > > Given your extremely slow speed, that's the way to go! > > Peter Alfke > > > > > > On Apr 16, 10:04 pm, vlsi_learner <baj...@gmail.com> wrote: > > > Hi Petter, > > > > > > I was trying to do the same, using 2 SPRAM's & writing to both of them > > > simultaneouly using same address & data. > > > > > > addr_0 = ~pa_rwb ? pa_wraddr : pa_rdaddr; (port A is R/W port) > > > > > > addr_1 = ~pa_rwb ? pa_wraddr : (pb_rwb ? pb_rdaddr : 8'b0); (port B > > > is read only port) > > > > > > In this case , if there is a write from port A then we cannot read > > > from the other port.Is this dual port > > > functionality? > > > > > > > > Petter Gustad wrote: > > > > "vlsi_learner" <baj...@gmail.com> writes: > > > > > > > > My ASIC design requires dual port memories(one port R/W other port > > > > > only read) but there is a constraint on using it. > > > > > Instead I am planning to create this memory using single port RAM's. > > > > > > > You an use two RAMs if you have enough RAM availabe in your > > > > ASIC. Simply write into both RAMs using the same address and data. > > > > > > > Petter > > > > -- > > > > A: Because it messes up the order in which people normally read text. > > > > Q: Why is top-posting such a bad thing? > > > > A: Top-posting. > > > > Q: What is the most annoying thing on usenet and in e-mail?Article: 118070
Hi, What is the default state of the unused I/O pins for Xilinx FPGA (Spartan 3E)? For Altera FPGA, it can be set as input tri-stated or as output driving gnd, etc. Is there any counterpart operation in Xilinx ISE to set the unused I/O pins? Thanks, JJArticle: 118071
"Steve" <eejju@polyu.edu.hk> wrote in message news:1176808198.147633@nsserver1.polyu.edu.hk... > Hi, > > What is the default state of the unused I/O pins for Xilinx FPGA (Spartan > 3E)? For Altera FPGA, it can be set as input tri-stated or as output > driving gnd, etc. Is there any counterpart operation in Xilinx ISE to set > the unused I/O pins? > > Thanks, > JJ > Google this. unused I/O pins site:xilinx.com HTH, Syms.Article: 118072
On 16 Apr 2007 01:56:48 -0700, ashasravanthi@gmail.com wrote: >hi all, > can anyone tell me where i can get a free vpw/pwm controller >either in vhdl or verilog according to j1850 standards. Sounds like we don't know what "j1850" is. Could you point us at a reference somewhere? Generally, PWM or other pulse generators are so easy to write in HDLs that I build them afresh each time I need one, using a few standard arrangements that I've used in the past. Input register, counter, comparator, output register... -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 118073
On Apr 17, 3:27 am, Allen <lphp...@gmail.com> wrote: > On Apr 17, 11:23 am, John McCaskill <junkm...@fastertechnology.com> > wrote: > > > > > On Apr 11, 2:12 am, "Allen" <lphp...@gmail.com> wrote: > > > > On Mar 29, 10:52 pm, "John McCaskill" <junkm...@fastertechnology.com> > > > wrote: > > > > > On Mar 29, 12:45 am, "Allen" <lphp...@gmail.com> wrote: > > > > > > On Mar 25, 8:39 pm, "John McCaskill" <junkm...@fastertechnology.com> > > > > > wrote: > > > > > > > On Mar 25, 12:32 am, "Allen" <lphp...@gmail.com> wrote: > > > > > > > > On Mar 23, 8:33 pm, Zara <me_z...@dea.spamcon.org> wrote: > > > > > > > > > On 23 Mar 2007 05:13:46 -0700, "Allen" <lphp...@gmail.com> wrote: > > > > > > > > > >hi all, > > > > > > > > > >first, i am sorry for my poor English. > > > > > > > > > >i use EDK 7.1i and ISE 7.1i. > > > > > > > > > >imported custom peripheral with PLB Master Interface ( not from IFIP ) > > > > > > > > >into my .xps project after overcame several problems. > > > > > > > > > >In the step " generate netlist " there has no error or warning. > > > > > > > > > >but in the step "Generate Bitstream",i got a error message "ERROR!! > > > > > > > > >NgdBuild:455 plb_M_ABUS<62> has multiple driver(s)": return code 2 > > > > > > > > >abort. > > > > > > > > > >already search this problem in xilix's answer database and tried > > > > > > > > >modify the parameter of C_BaseAddr, but it is still stuck here. > > > > > > > > > >does anyone meet this problem before? > > > > > > > > > >thanks in advance. > > > > > > > > > I always got that messaghe when I had some signal with two outputs > > > > > > > > connected to it. That seems your case, in your plb address bus, master > > > > > > > > interface. > > > > > > > > > Best regards, > > > > > > > > > Zara- Hide quoted text - > > > > > > > > > - Show quoted text - > > > > > > > > Thanks for your reply. > > > > > > > > so it might mean something wrong during import of custom peripheral? > > > > > > > > but in 64-bit PLB protocol, the address width is 32-bit. > > > > > > > > i already use (C_PLB_AWIDTH-1) to replace with constant "31" in my > > > > > > > port declaration. > > > > > > > > do anything i could try to solve this problem? > > > > > > > > thank you :-) > > > > > > > The PLB address width is 32 bits. However, the way that all the bus > > > > > > signals are connected to the PLB IP is that they are concatenated > > > > > > together. So if you look at the MPD file for the PLB you will see that > > > > > > it defines the bus width to be 32 bits times the number of masters: > > > > > > > PORT M_ABus = M_ABus, DIR = I, VEC = [0: > > > > > > (C_PLB_NUM_MASTERS*C_PLB_AWIDTH)-1] > > > > > > > So the signal plb_M_ABUS<62> is bit 30 of the second master. Look to > > > > > > see if your core has been assigned the second master slot on the PLB > > > > > > bus. Assuming that is the case, find what two sources are driving bit > > > > > > 30 of the address. > > > > > > > Assuming that you left the name of your EDK project as system.xmp, > > > > > > when you tell EDK to generate a netlist it will create a top level hdl > > > > > > file named either system.vhd or system.v depending on your tool > > > > > > settings. You can look at this file to see how EDK has connected the > > > > > > cores to the PLB. > > > > > > > It has been a while since I had to find a multi source signal, but I > > > > > > think that XST will produce a warning about it in its report and tell > > > > > > you what the multiple soures are. Look in the synthesis report file > > > > > > for the appropriate core and see if it tells you what the source of > > > > > > the problem is. > > > > > > > Since you are creating your own interface design instead of using the > > > > > > IPIF, are you using the bus functional models in your simulations? I > > > > > > use these, and they make the job much easier. I think it was not > > > > > > until EDK 8.1 that they were integrated into EDK itself, but I was > > > > > > able to use the CoreConnect tool kit directly from IBM in some of our > > > > > > early stuff. The bus monitors will tell you as soon as your core has > > > > > > done something wrong, so you do not have to track the source of the > > > > > > problem back from when the symptoms show up. > > > > > > > Regards, > > > > > > > John McCaskillwww.fastertechnology.com-Hidequotedtext- > > > > > > > - Show quoted text - > > > > > > Thanks for your reply. :-) > > > > > > Where i could see the second master is who( power pc or custom > > > > > peripheral ... etc)? > > > > > I don't know where to check this. > > > > > While there may be an easier way, you can just look at a PLB master > > > > signal that is not a vector. For example, if you look at plb_M_RNW in > > > > your system.vhd you will see that it is defined as: > > > > > signal plb_M_RNW : std_logic_vector(0 to 2) > > > > > The entire vector is an input to the plb_wrapper. plb_M_RNW(0) will go > > > > to PLB master 0, plb_M_RNW(1) will go to PLB master 1, etc. > > > > > > I opened the system.vhd to see who connect to the plb_M_Abus. > > > > > "PowerPC" have 2 ports and Custom peripheral has 1 port connect to the > > > > > plb_M_ABus. > > > > > Next step, I am going to find the XST report file to see who drive the > > > > > plb_M_ABUS<62>. > > > > > No offense intended, but with just the PowerPC, and your new custom > > > > peripheral on the PLB bus the odds are that your peripheral is the > > > > source of the problem. Take a look at the synthesis report for it. > > > > In EDK, in the "Project Information Area" pane, and the Project tab, > > > > expand the "Report Files" selection. Find the one for your peripheral > > > > and look through it. I think there should be a warning about multiple > > > > sources driving a destination at this point. If you do not see it > > > > there, try looking through the implementation/xflow.log file in the > > > > "Log Files" section. > > > > > > I didn't run the simulation of this platform. I heard the "bus > > > > > functional model" before, but I don't understand how to use it. Would > > > > > you like to give any information about this one? > > > > > Take a look at: > > > > >http://www.xilinx.com/ise/embedded/edk6_3docs/bfm_simulation.pdf > > > > > This link is for the EDK 6.3 version of the documentation, but you > > > > should have a more recent version in your EDK distribution at $EDK/doc/ > > > > bfm_simulation.pdf. > > > > > One of the main things that I like about using the bus functional > > > > models is that the bus monitors tell you when a error occurred in the > > > > simulation, and what the error was. This saves you the effort of > > > > having to search backwards from where the symptoms of the error show > > > > up to figure our what has gone wrong. > > > > > > In addition the error"NgdBuild 455", there are several warnings "SFF > > > > > Primitive", i didn't find this on the Xilinx answer database.. maybe > > > > > this warning has something to do with the error. > > > > > > Thank you very much~ > > > > > Regards, > > > > > John McCaskillwww.fastertechnology.com-Hidequotedtext - > > > > > - Show quoted text - > > > > Thank in advance. > > > > I check the synthesis report and I found something in implementation/ > > > xflow.log file > > > > ERROR:NgdBuild:455 - logical net 'plb_M_ABus<62>' has multiple > > > driver(s): > > > pin G on block ppc405_0/XST_GND with type GND, > > > pin G on block dma_mci_top_0/XST_GND with type GND, > > > pin P on block ppc405_0/XST_VCC with type VCC, > > > pin G on block plb2opb/XST_GND with type GND, > > > pin O on block plb2opb/plb2opb/I_BGO_addrAck with type LUT4, > > > pin G on block plb_bram_if_cntlr_1/XST_GND with type GND, > > > pin P on block plb_bram_if_cntlr_1/XST_VCC with type VCC > > > > There are 7 driver to drive this node and the dma_mci_top is the > > > custom peripheral. > > > > I have no idea about this situation. how come does it? I only import > > > the custom peripheral and create a platform. > > > > Does it any problem happend at the process of "Import Custom > > > Peripheral" ? > > > 'cause, during the import procedure, I need to set some bus parameter, > > > like C_PLB_NUM_MASTER...etc. > > > I try to find document on the Xilinx website, but I didn't find any > > > tutorail about the Import procedure. > > > > Would you like to give me any hints for solving this problem. > > > > Thank you very much. > > > I used the import wizard just a few times to see what it did, then I > > started creating all my peripherals by hand, so I do not remember how > > it works very well. But, C_PLB_NUM_MASTER is a parameter/generic that > > needs to be set by EDK when it creates all the wrapper files for the > > PLB peripherals. Did you set it to a numeric value? > > > EDK includes the source code and support files for the cores that it > > comes with. Look through them for examples of how to create a PLB > > slave. If I remember correctly, the multi port memory controller > > reference design also has a PLB slave that is not based on the IPIF, > > and is simpler. > > > Regards, > > > John McCaskillwww.fastertechnology.com-Hide quoted text - > > > - Show quoted text - > > Thank you very much. > > I set C_PLB_NUM_MASTER=2 in the verilog design. Does EDK change this > parameter during creating platform? > > I wil go to check the examples. > > Besides, I saw an example that the custom peripheral is imported inot > EDK without bus interface. How could I do this? I search several > document, I don't see something to do with it. > > Thanks again > > Sincerely. EDK automatically sets the values of many parameters/generics when it creates the wrapper files. C_PLB_NUM_MASERS is one of the ones that EDK sets. I would recomend that you read the "Platform Specification Format Reference Manual" which defines the contents of the data files that describes pcores to EDK. It is located in the EDK install directory at $EDK/doc/psf_rm.pdf. These files are being created for you by the import wizard. While reading this, look at some of the cores in EDK for examples. The EDK cores are located at $EDK/hw/ XilinxProcessorIPLib/pcores for the hardware parts, and at $EDK/hw/ XilinxProcessorIPLib/drivers for the software parts. For what you are doing, you probably want to focus on examining the MPD file for your core. The MPD file contains the information that EDK uses to figure out how to connect a pcore to the rest of the system. It also defines the parameters/generics for a pcore. Regards, John McCaskill www.fastertechnology.comArticle: 118074
more than 2 days..... more than 2 years perhaps
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