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There is no difference between "expected" and "obtained". You got what you expected, except for one missing space after the colon.. Peter Alfke On Apr 10, 1:32 pm, Amine.Mi...@gmail.com wrote: > Hi everybody, > > i have a missunderstanding of the flip flop behavior: > usually the output of a flip flop is assigned its input of the > previous clock period (that's true for internal signal), but i > observed that when i connect the flip flop to an external input the > output of the flip flop is assigned to the input of the same clock > period: it works like an "asynchronous flip flop", an example of the > problem is described below. > > anyone of you can explain me the problem or the behavior of this flip > flop please? > thank you!!! > > clk : 01010101010101010101 > input : 00001111100000111111 > ouput : U0000111110000011111 (expected) > output:00000111110000011111 (obtaine) > > d=E9claration of the flip flop > > process (Reset_n, Clk) > begin > if (reset_n=3D'0') then > Output <=3D'0'; > elsif(clk'event and clk=3D'1') then > output <=3Dinput; > end if; > end process;Article: 117801
On Apr 10, 1:32 pm, Amine.Mi...@gmail.com wrote:
> i have a missunderstanding of the flip flop behavior:
> usually the output of a flip flop is assigned its input of the
> previous clock period (that's true for internal signal), but i
> observed that when i connect the flip flop to an external input the
> output of the flip flop is assigned to the input of the same clock
> period: it works like an "asynchronous flip flop", an example of the
> problem is described below.
The flip flop must behave in the same way whether it is connected to
an internal signal or an external signal (how can it know what it is
connected to?)
How have you observed this problem? In simulation? In hardware?
Just for fun, I simulated the following code with the XST simulator,
and it behaves as expected.
I was having fun trying to understand your post in French :-)
Alan Nishioka
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity goat is
port
(
Reset_n : in std_logic;
Clk : in std_logic;
Input : in std_logic;
Output : out std_logic
);
end goat;
architecture implementation of goat is
begin
process (Reset_n, Clk)
begin
if (reset_n='0') then
Output <='0';
elsif(clk'event and clk='1') then
output <=input;
end if;
end process;
end;
Article: 117802On Apr 10, 2:27 pm, "H. Peter Anvin" <h...@zytor.com> wrote: > Hi all, > > I have a potential (hobby) project, where I'm looking at needing, in > effect, a CPLD and a =B5C that can share memory. +5 V I/O tolerance is > necessary (for about 52 signals coming into the board), and I would like > to keep the power supply complexity to a minimum since I'm really a > software guy and don't particularly trust my board layout skills. > > Anyway, I was looking at using an Atmel FPSLIC part, but it looks like > the tools are prohibitively expensive. I was wondering if anyone knows > of a similar part that would be less expensive once the tools are > accounted for? The alternatives seem to be using a Cyclone or Spartan > big enough to integrate the whole design including =B5C, but they require > complex power supplies and external voltage converters, or cobble > something together from multiple parts. > > -hpa Dealing with the multiple power supplies can be easy if you use some of the DC-DC modules that are on the market. We use Tyco Lynx series converters to generate the voltages for a Virtex-4FX and a Spartan-3E. They just need a few external components. A resister to adjust their output voltage, and some bulk decoupling capacitors. You can get them as through hole SIP modules, and I think that Mouser sells them. There are multiple different ways of dealing with the 5V IO issues, it depends on what you are interfacing to. Regards, John McCaskill www.fastertechnology.comArticle: 117803
Well that's the digram that i get, as you can see the expected ouput
is shifted by one, the first one (in my previous message) includes a
blank space,
clk : 01010101010101010101
input : 00001111100000111111
ouput : u00000111110000011111 (expected)
output: 00000111110000011111 (obtaine)
what i get is during the presynthese simulation and post synthese
simulation.
Sure that the flip flop should behave the same either it s connected
to the internal or external signal and that s what i was expecting
unfortunatly it wasn't the case.
here the VHDL code, probably you will see some unusefull signals, it
is just for testing, can you see any problem in this code??????
(concerning my french message: when i posted it i realized to have
more coverage and answers it is better to send an english
version :)))))))) )
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.NUMERIC_BIT.all;
use ieee.STD_LOGIC_ARITH.all;
------------------------------------
-- entity declaration --
------------------------------------
entity FSM_load is
generic(n:integer:=6;
s:integer:=6);
PORT (
-- input
Reset_n : in
std_logic;
Clk : in
std_logic;
Start : in
std_logic;
Data_in : in std_logic;
Proc_Ready : in std_logic;
Length_q : in std_logic_vector(N-1 downto 0);
Output1 : out std_logic;
-- Output1 : out std_logic_vector (39 downto
0);
-- Output2 : out std_logic_vector (39 downto
0);
Output2 : out std_logic;
-- output
Reset_n_FSM_Stat : out std_logic;
Start_FSM_Stat : out std_logic;
Write_en : out std_logic;
Seq_element : out std_logic_vector(S-1 downto 0);
SRAM_addr : out std_logic_vector(N-1 downto 0)
);
end FSM_load;
------------------------------------
-- end if entity declaration --
------------------------------------
------------------------------------
-- archtecture declaration --
------------------------------------
architecture RTL of FSM_load is
-- type declaration
type state_fp_ce_type is (S_idle, S0, S1, S2, S3,S4, S5, S6, S7,
S8);
-- signal declaration
signal state_fp_ce : state_fp_ce_type;
signal state_fp_ce_2 : state_fp_ce_type;
signal Const : std_logic_vector (S-2 downto 0);
signal Shift_en : std_logic;
signal Shift_out_en : std_logic;
signal Load_en : std_logic;
signal Reset_n_local : std_logic;
signal Pre_load_reg : std_logic_vector(39 downto 0);
signal Load_reg : std_logic_vector(39 downto 0);
signal Data_out : std_logic_vector(39 downto 0);
signal Count : std_logic_vector(5 downto 0);
signal Count_2 : std_logic_vector(5 downto 0);
signal SRAM_addr_tmp : std_logic_vector(N-1 downto 0);
signal output_tmp : std_logic;
begin
process ( Reset_n , Clk, Start)
begin
if reset_n='0' then
count <= (others=>'0');
Shift_en <= '1';
Load_en <= '0';
state_fp_ce <= S_idle;
elsif clk'event and clk='1' then
case state_fp_ce is
when S_idle =>
if (Start = '1') then
Shift_en <= '1';
State_fp_ce <= S0;
else
State_fp_ce <= S_idle;
end if;
-- initialisation
when S0 =>
if (count=length_q-1) then
Load_en <= '1';
State_fp_ce <= S2;
Count <= (others=>'0');
else
Count <= Count + '1';
Shift_en <= '1';
State_fp_ce <= S0;
end if;
when S1 =>
state_fp_ce <= S2;
-- enabling global scan
when S2 =>
Count <= Count + '1';
Load_en <= '0';
state_fp_ce <= S0 ;
when others =>
state_fp_ce <= S_idle;
end case ;
end if ;
end process;
process ( Reset_n , Clk, Proc_Ready)
begin
if reset_n='0' then
Reset_n_local <= '0';
count_2 <= (others=>'0');
Shift_out_en <= '0';
SRAM_addr_tmp <= (others=>'0');
state_fp_ce_2 <= S_idle;
elsif clk'event and clk='1' then
case state_fp_ce_2 is
when S_idle =>
if (Proc_Ready = '1') then
Reset_n_local <= '1';
Shift_out_en <= '1';
Write_en <= '0';
State_fp_ce_2 <= S0;
else
State_fp_ce_2 <= S_idle;
end if;
-- initialisation
when S0 =>
if (count_2=length_q-'1') then
State_fp_ce_2 <= S2;
Write_en <= '1';
Shift_out_en <= '0';
SRAM_addr_tmp <=
(Others=>'0');
Count_2 <= (others=>'0');
else
Count_2 <= Count_2 + '1';
SRAM_addr_tmp <=
SRAM_addr_tmp + '1';
Shift_out_en <= '1';
State_fp_ce_2 <= S0;
end if;
when S1 =>
State_fp_ce_2 <= S2;
-- enabling global scan
when S2 =>
Reset_n_local <= '0';
State_fp_ce_2 <= S_idle ;
when others =>
State_fp_ce_2 <= S_idle;
end case ;
end if ;
end process;
Const <= (Others=>'0');
SRAM_addr <= SRAM_addr_tmp;
process (Reset_n, Clk,Shift_en)
begin
if (Reset_n='0') then
Pre_load_reg(39 downto 1) <= (Others=>'0');
elsif (Clk'event and Clk='1') then
if (Shift_en='1') then
Pre_load_reg (39 downto 1) <= Pre_load_reg (38 downto 0);
end if;
end if;
end process;
process (Reset_n, Clk,Shift_en)
begin
if (Reset_n='0') then
Pre_load_reg(0) <= '0';
elsif (Clk'event and Clk='1') then
if (Shift_en='1') then
Pre_load_reg (0) <= Data_in;
end if;
end if;
end process;
process (Reset_n, Clk)
begin
if (reset_n='0') then
output_tmp<='0';
elsif(clk'event and clk='1') then
output_tmp<=Data_in;
end if;
end process;
output1 <= output_tmp;
process (Reset_n, Clk)
begin
if (reset_n='0') then
Output2<='0';
elsif(clk'event and clk='1') then
output2<=output_tmp;
end if;
end process;
process (Reset_n, Clk,load_en)
begin
if (Reset_n='0') then
Load_reg <= (Others=>'0');
elsif (Clk'event and Clk='1') then
if load_en ='1' then
Load_reg <= Pre_load_reg;
end if;
end if;
end process;
-- output2 <= load_reg;
process (Reset_n_local, Clk,Shift_out_en,Load_reg)
begin
if (Reset_n_local='0') then
Data_out <= Load_reg;
elsif (Clk'event and Clk='1') then
if Shift_out_en ='1' then
Data_out(38 downto 0) <= Data_out(39 downto 1);
end if;
end if;
end process;
process (Reset_n, Clk,Shift_out_en)
begin
if (Reset_n='0') then
Seq_element <= (others=>'0');
elsif (Clk'event and clk='1') then
if (Shift_out_en='1') then
Seq_element <= Const&Data_out(0);
end if;
end if;
end process;
end RTL;
------------------------------------
--end of architecture declaration --
------------------------------------
Article: 117804Alan, Perhaps the confusion is between a (asynchronous) latch, and an edge triggered flip-flop (hence the reference to asynchronous vs. synchronous 'flip-flop' 'bascule' behavior)? The HDL code, when synthesized, gets implemented in whatever library of hardware is available, based on the instructions given. If there were no D type edge-triggered flip flops in the library, would the resulting synthesis create one? Or, would the resulting synthesis use a latch instead? How does one force a latch, or a DFF? [verilog] "always @(posedge CLK)" infers the synchronous DFF, so there is no latch possible. If you tried to make a shift-register from placing latches in series and clocking all the clocks at once, you would not get what you need! The synthesis needs to be able to recognize how to build the proper circuit. AustinArticle: 117805
On Apr 10, 4:27 pm, "H. Peter Anvin" <h...@zytor.com> wrote: > Hi all, > > I have a potential (hobby) project, where I'm looking at needing, in > effect, a CPLD and a =B5C that can share memory. +5 V I/O tolerance is > necessary (for about 52 signals coming into the board), and I would like > to keep the power supply complexity to a minimum since I'm really a > software guy and don't particularly trust my board layout skills. > > Anyway, I was looking at using an Atmel FPSLIC part, but it looks like > the tools are prohibitively expensive. I was wondering if anyone knows > of a similar part that would be less expensive once the tools are > accounted for? The alternatives seem to be using a Cyclone or Spartan > big enough to integrate the whole design including =B5C, but they require > complex power supplies and external voltage converters, or cobble > something together from multiple parts. > > -hpa Buy an evaluation board/development kit, probably that's the cheapest, and least effort. Some Xilinx options: Virtex-4 Mini modules (hard PowerPC core): $250 http://www.em.avnet.com/evk/home/0,1719,RID%253D0%2526CID%253D25726%2526CCD= %253DUSA%2526SID%253D32214%2526DID%253DDF2%2526LID%253D32232%2526BID%253DDF= 2%2526CTP%253DEVK,00.html Spartan-3 Starter kit (soft uBlaze core): $149 http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key= =3DHW-SPAR3-SK-UNI-G Regards, ZoltanArticle: 117806
On 10 Apr 2007 08:54:24 -0700, fancier.fpga@googlemail.com wrote: > >I understand that the inventor of the FPGA was a Ross Freeman, who >died >aged 45, tragically just 5 years after he co-counded Xilinx. > >Does anyone have more details of him? > >Best regards. I only got to see Ross Freeman speak once, but it was a memorable event. Back in the late 80's, when I was putting in my time at AMD, the company was second-sourcing some of the Xilinx product line. One year, Freeman was booked as a Field Applications Engineering conference speaker. Many of the FAEs were upset by the fact that Xilinx was selling new part types well before AMD was able to, and they were out for blood. AMD FAEs were no wallflowers, and from the way some of them were talking, Freeman's presentation was going to turn into a roast. The time arrived, and Freeman gave an interesting, upbeat talk about what was going on at Xilinx, then asked for questions. One of the FAEs asked why they were being denied the right to sell new Xilinx parts as soon as Xilinx released them. Freeman, in as calm and polite a way as you could possibly imagine, said (and I'm paraphrasing through the filter of almost 20 years), "Of course we're selling them first. We invented them, we sweated bullets making them, and it's only right that we get first crack at the sales." Silence. There was not a single follow-up question on the subject. The guy sounded so darned *reasonable* that you would have felt like a dope arguing the point. Many people will remember Ross Freeman as a brilliant technical innovator. He was certainly that. But I'll remember him as an engineer who knew how to talk to people--warmly, politely, yet with utter conviction. Bob Perlman Cambrian Design Works http://www.cambriandesign.comArticle: 117807
hi, thank you all, for your answers and comments, I simulated the VHDL code of Alan (may be i did some mistake that i can't see :) in the flip flop declaration) and the output of the flip- flop is exactly equal to its input, but usually what's expected from a flip-flop is an output swhich is equal to the input signal shifted by one clock period (assuming that there is no enabling signal), again the problem is faced inly with external signal not with internal signal, i know that there is no difference between internal and external in that case but after simulation (pre and post synthese) there is! personnally i can t find any explanation for that problem, Regards!!Article: 117808
Hi Pablo, Pablo wrote: > Does anybody use Setjmp.h for Microblaze?. I have to use this library > but something is wrong, so I have decided to open smtjmp.h and I have > seen that there is no definition for Microblaze. Does anyone use this > library?Does I must define some flag to compile? I've not used/seen a version of setjmp for standalone MicroBlaze code. It was implemented in uClibc for MicroBlaze as part of the Embedded Linux support. You can browse it here: http://developer.petalogix.com/browser/software/petalinux-dist/uClibc/libc/sysdeps/linux/microblaze Regards, JohnArticle: 117809
zcsizmadia@gmail.com wrote: > > Buy an evaluation board/development kit, probably that's the cheapest, > and least effort. Some Xilinx options: > Not an option, I'm afraid (otherwise it would by far be the easiest.) Unfortunately, the board needs to fit into a legacy system, which means a specific form factor, connector, and power supply (and the need to interface to 5 V TTL logic -- I think the system is actually old enough that it's real LSTTL buffers on the other side, not HCMOS.) -hpaArticle: 117810
I think that i found the problem! The problem wasn't in the flip flop declaration but in the testbench, in fact in my testbench the input is changing excatly at the clock edge, in that case the simulator consider the input value : the value excatly after the clock edge, and it is explains why the flip flop has a different behaviour with internal Vs. external, with external i mean input signal generated by user. In the case of internal signal it looks like the simulator considers some delay and .... The solution is to make the input signal changing before or after the clock edge, This solution doesn t solve my problem because my input signal is changing on the clock edge but it is an interpretation of the problem, so the real behaviour will be get with hardware simulation using digital analyser! ( Probably it is the limit of the simulator tools :)) it s just a simulator ) Thank you all for your comments AmineArticle: 117811
On Apr 10, 6:32 pm, "H. Peter Anvin" <h...@zytor.com> wrote: > zcsizma...@gmail.com wrote: > > > Buy an evaluation board/development kit, probably that's the cheapest, > > and least effort. Some Xilinx options: > > Not an option, I'm afraid (otherwise it would by far be the easiest.) > Unfortunately, the board needs to fit into a legacy system, which means > a specific form factor, connector, and power supply (and the need to > interface to 5 V TTL logic -- I think the system is actually old enough > that it's real LSTTL buffers on the other side, not HCMOS.) > > -hpa How big is your form factor? I think it is still easier to make a motherboard for the Virtex-4 Mini module, and add a 5V TTL logic converter and the power supplies vs. designing a new board. I wouldn't worry about power supplies. That should be your smallest problem. Other option is to put a small Spartan II and a uC (with external data bus support, e.g. Atmega), and use the dual-port ram inside Spartan to share memory between uC and Spartan.Article: 117812
PeterK wrote: > My very first project is a PWM in Quartus II 7.0. I've drawn up a > block diagram with a 17 bit lpm_counter going into a 5 bit > lpm_compare. All I want is the top five bits of the counter to go > into the comparator. After several days of trying I still have no > idea how to split the 17 bits to just use the top five bits. With a > normal bus connection it compiles with a Width mismatch error. Prediction: One day you'll be *sooooo* sick of trying to maintain schematics that you'll bite the bullet and start to learn VHDL/Verilog... Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 117813
I have a webcase open since 3/20. Though I have been given decent support I find that I get one and only one email from Xilinx per day...at most. Even if it is a simple response, there is no communications for at least 24 hours. For instance, this morning I received an email from my support worker. Since I wanted some more explanation/other options, I immediately replied. I have not heard anything since. This is pretty much how all the cases I have opened have proceeded. I understand that these guys are probably overloaded with cases, but my company has an XPA which supposedly gives us better support options. I was just wondering if this is the way thigs always work? Maybe all emails are parsed through some type of system that queues things such that the workers don't see them immediately. I don't know...Article: 117814
On Apr 10, 12:12 pm, "eejw" <wilder_j...@hotmail.com> wrote: > Sorry...typo > > 16-bit word (not "16-byte word") in passing data from MB -> pcore. > > On Apr 10, 11:07 am, "eejw" <wilder_j...@hotmail.com> wrote: > > > > > Hello all: > > > I have a question regarding using SysGen to create a co-processor > > that's used in a microblaze design. I'm using EDK v9.1 through the > > base system builder wizard to create a design used on a Xilinx ML401 > > dev. board. > > > I've already generated a simple pcore and connected that to the > > microblaze proc. in EDK. Data are being passed from MB -> pcore and > > pcore -> MB through shared memory (using the "from register" and "to > > register" in SysGen). > > > Using the provided function calls for communicating from MB -> pcore, > > I do the following: > > > findavg_sm_0_Write(FINDAVG_SM_0_D0,FINDAVG_SM_0_D0_DIN, datasamp[0]); > > findavg_sm_0_Write(FINDAVG_SM_0_D1,FINDAVG_SM_0_D1_DIN, datasamp[1]); > > findavg_sm_0_Write(FINDAVG_SM_0_D2,FINDAVG_SM_0_D2_DIN, datasamp[2]); > > etc. > > > To check performance, I start timer, do function call to write shared > > memory, then read value from timer. > > > So it's just: > > > //start timer > > findavg_sm_0_Write(FINDAVG_SM_0_D0,FINDAVG_SM_0_D0_DIN, datasamp[0]); > > //read count register > > > I'm seeing that it takes 28 clock cycles to pass a 16-byte word from > > MB -> pcore in this way. This seems *way* too long. > > > To improve performance, the API documents that were generated when I > > created the pcore suggest to remove this line in the xparameters.h > > file: > > > #define FINDAVG_SM_0_SG_ENABLE_FSL_ERROR_CHECK > > > I did that, but it doesn't help. > > > I didn't do anything special regarding connecting my pcore to the MB. > > Just added it through the Hardware -> Configure coprocessor... tool in > > EDK which connects the pcore to MB through an FSL. > > > Has anyone investigated this and can share any words of wisdom? > > > thanks, > > Joel- Hide quoted text - > > - Show quoted text - > could start timer do 4 writes to different locations then read the elapsed value divide value by 4 manually it would be interesting to see if the value is still 28 clocks does MB have a cache? chipscope or simulation would highlight what's going on NewmanArticle: 117815
On Apr 10, 11:34 pm, "Newman" <newman5...@yahoo.com> wrote: > On Apr 10, 12:12 pm, "eejw" <wilder_j...@hotmail.com> wrote: > > > > > > > Sorry...typo > > > 16-bit word (not "16-byte word") in passing data from MB -> pcore. > > > On Apr 10, 11:07 am, "eejw" <wilder_j...@hotmail.com> wrote: > > > > Hello all: > > > > I have a question regarding using SysGen to create a co-processor > > > that's used in a microblaze design. I'm using EDK v9.1 through the > > > base system builder wizard to create a design used on a Xilinx ML401 > > > dev. board. > > > > I've already generated a simple pcore and connected that to the > > > microblaze proc. in EDK. Data are being passed from MB -> pcore and > > > pcore -> MB through shared memory (using the "from register" and "to > > > register" in SysGen). > > > > Using the provided function calls for communicating from MB -> pcore, > > > I do the following: > > > > findavg_sm_0_Write(FINDAVG_SM_0_D0,FINDAVG_SM_0_D0_DIN, datasamp[0]); > > > findavg_sm_0_Write(FINDAVG_SM_0_D1,FINDAVG_SM_0_D1_DIN, datasamp[1]); > > > findavg_sm_0_Write(FINDAVG_SM_0_D2,FINDAVG_SM_0_D2_DIN, datasamp[2]); > > > etc. > > > > To check performance, I start timer, do function call to write shared > > > memory, then read value from timer. > > > > So it's just: > > > > //start timer > > > findavg_sm_0_Write(FINDAVG_SM_0_D0,FINDAVG_SM_0_D0_DIN, datasamp[0]); > > > //read count register > > > > I'm seeing that it takes 28 clock cycles to pass a 16-byte word from > > > MB -> pcore in this way. This seems *way* too long. > > > > To improve performance, the API documents that were generated when I > > > created the pcore suggest to remove this line in the xparameters.h > > > file: > > > > #define FINDAVG_SM_0_SG_ENABLE_FSL_ERROR_CHECK > > > > I did that, but it doesn't help. > > > > I didn't do anything special regarding connecting my pcore to the MB. > > > Just added it through the Hardware -> Configure coprocessor... tool in > > > EDK which connects the pcore to MB through an FSL. > > > > Has anyone investigated this and can share any words of wisdom? > > > > thanks, > > > Joel- Hide quoted text - > > > - Show quoted text - > > could start timer > do 4 writes to different locations > then read the elapsed value > divide value by 4 manually > > it would be interesting to see if the value is still 28 clocks > does MB have a cache? > chipscope or simulation would highlight what's going on > > Newman- Hide quoted text - > > - Show quoted text - > findavg_sm_0_Write(FINDAVG_SM_0_D0,FINDAVG_SM_0_D0_DIN, datasamp[0]); also, disassemble the write function to see how efficiently it compiled the instruction I would think that it should be around 1 assembly opArticle: 117816
Hello, I am working with the ML410 board and the V4FX60 FPGA. For the past week and a half, I've been having problems meeting timing and I just can't figure out why. In my design, I need to use DDR2 and the APU controller as well as the FPU core. I also need two OPB peripherals: the RS232 and the SystemACE. These are the clocking requirements for my design: CPU: 266 MHz PLB: 100 MHz OPB: 100 MHz DDR2: 100 MHz controller (on PLB), 200 MHz memory (DDR2-400) FCB: 266 MHz (fabric co-processor bus) FPU: 133 MHz (on FCB) All of these are within the documented limits for the cores and this speed grade FPGA (-11). These are the steps I follow to get to this design: 1. Start with BSB wizard and generate a 300 MHz CPU / 100 MHz PLB design with all the above mentioned IPs, except the FCB and the FPU. 2. This design does synthesize, map, place and route, although PAR complains that timing constraints are not met for the DDR2 clocks. I talked with Xilinx about this and they assured me this is OK (they know about this issue). Everything works fine at this point, although I am not too happy with Xilinx's lack of explanation for this timing issue. 3. Next, I modify the design to generate a CLKFX from one of the two DCMs to make the 266 MHz CPU clock. I also uncheck the CPMC405SYNCBYPASS option in the PPC405 configuration so that non- integer CPU-PLB ratios are allowed. I update the frequency in the software settings. 4. Finally, I bring in the FCB and the APU-FPU cores. I tie the FCB to the processor clock, and use a CLKFX output on one of the DCMs to generate the 133 MHz clock for the APU-FPU core. I enable APU support in the PPC405 processor core. 5. When I build this system, I get 3 timing constraints not met: 1 for the DDR2 (as seen previously, but according to Xilinx not to worry about, and 2 new ones). The 2 new failing constraints are the CPU 266 MHZ clock and the FPU 133 MHZ clock. I tried executing my software on this faulty hardware and it works sometimes, but not always. I do get DCM lock though. This is how I have my two DCMs configured: dcm_0 (DFS low, DLL low) -------------------------------------- RST: net_gnd CLKIN: dcm_clk_s (from sys_clk_pin, 100 MHz) CLKFB: sys_clk_s (100 MHz) CLK0: sys_clk_s (PLB and OPB clock, 100 MHz, BUFG) CLKDV: ddr2_cal_clk (50 MHz, BUFG) CLK2X: dcm_0CLK2X (cascade to next DCM, 200 MHz, BUFG) CLKFX: apu_fpu_clk_s (FPU clock, 133 MHz, BUFG) LOCKED: dcm_0_lock (to next DCM) dcm_1 (DFS high, DLL high) -------------------------------------- RST: dcm_0_lock (from previous DCM) CLKIN: dcm_0CLK2X (from previous DCM, 200 MHz) CLKFB: clk_200mhz_s (200 MHz) CLK0: clk_200mhz_s (DDR2 clock, 200 MHz, BUFG) CLK90: ddr2_dev_clk_90_s (DDR2 clock, 200 MHz, BUFG) CLKFX: proc_clk_s (CPU clock, 266 MHz, BUFG) LOCKED: dcm_1_lock (to reset_block) Like I said, I can't think of why this would not meet timing! Is it harder to route a 266 MHz CPU clock than a 300 Mhz design? What can I do to mitigate this? I tried various options in synthesis, map, PAR, and the Xplorer script. But I think it probably is something in my configuration of the DCMs, because it should work as I am not asking for a very high frequency. Any help would be very greatly appreciated (I would hate to go back to a working 200 MHz design because of this). Thanks Dmitriy BekkerArticle: 117817
zcsizmadia@gmail.com wrote: > > How big is your form factor? I think it is still easier to make a > motherboard for the Virtex-4 Mini module, and add a 5V TTL logic > converter and the power supplies vs. designing a new board. > I wouldn't worry about power supplies. That should be your smallest > problem. > > Other option is to put a small Spartan II and a uC (with external data > bus support, e.g. Atmega), and use the dual-port ram inside Spartan to > share memory between uC and Spartan. > The form factor is quite big -- 100x160 mm (Eurocard), so space is largely plentiful. The Virtex-4 mini module is quite expensive, though ($250), which is okay for a one-off but may be too much for an actual production run -- I would have to do the math on that. I didn't realize that Spartan II was 5 V tolerant. I'm going to have to see if that is practical to combine with a microcontroller. Still needs dual power supplies, though If not, a 200,000-gate Spartan II apparently retails for $26 these days; that FPGA should be large enough to fit an 8- or 16-bit microcontroller core plus all the logic. Anyone has any kind of idea how long Spartan II is likely to remain on the market? -hpaArticle: 117818
"osr" <pra.vlsi@gmail.com> writes: > Can anyone plz tell me the theory behind 32bit parallel CRC? i m not You can use the serial form and make a parallel version symbolically. Here is one example: http://groups.google.com/group/comp.lang.vhdl/msg/5027ed63d0cee083 Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 117819
Hi,
Can anyone plz tell me the theory behind 32bit parallel CRC? i m not
getting the basis on which the 32 bit CRC is being calculated in the
code below.This code is generated from the CRC tool of wesite www.easics.com.I
refered many ieee papers even then i couldnt get the idea.Plz help me
its urgent.
library IEEE;
use IEEE.std_logic_1164.all;
package PCK_CRC32_D8 is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial data bit is D(7)
function nextCRC32_D8
( Data: std_logic_vector(7 downto 0);
CRC: std_logic_vector(31 downto 0) )
return std_logic_vector;
end PCK_CRC32_D8;
library IEEE;
use IEEE.std_logic_1164.all;
package body PCK_CRC32_D8 is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial data bit is D(7)
function nextCRC32_D8
( Data: std_logic_vector(7 downto 0);
CRC: std_logic_vector(31 downto 0) )
return std_logic_vector is
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(31 downto 0);
variable NewCRC: std_logic_vector(31 downto 0);
begin
D := Data;
C := CRC;
NewCRC(0) := D(6) xor D(0) xor C(24) xor C(30);
NewCRC(1) := D(7) xor D(6) xor D(1) xor D(0) xor C(24) xor C(25)
xor
C(30) xor C(31);
NewCRC(2) := D(7) xor D(6) xor D(2) xor D(1) xor D(0) xor C(24)
xor
C(25) xor C(26) xor C(30) xor C(31);
NewCRC(3) := D(7) xor D(3) xor D(2) xor D(1) xor C(25) xor C(26)
xor
C(27) xor C(31);
NewCRC(4) := D(6) xor D(4) xor D(3) xor D(2) xor D(0) xor C(24)
xor
C(26) xor C(27) xor C(28) xor C(30);
NewCRC(5) := D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor D(1) xor
D(0) xor C(24) xor C(25) xor C(27) xor C(28) xor
C(29)
xor
C(30) xor C(31);
NewCRC(6) := D(7) xor D(6) xor D(5) xor D(4) xor D(2) xor D(1) xor
C(25) xor C(26) xor C(28) xor C(29) xor C(30) xor
C(31);
NewCRC(7) := D(7) xor D(5) xor D(3) xor D(2) xor D(0) xor C(24)
xor
C(26) xor C(27) xor C(29) xor C(31);
NewCRC(8) := D(4) xor D(3) xor D(1) xor D(0) xor C(0) xor C(24)
xor
C(25) xor C(27) xor C(28);
NewCRC(9) := D(5) xor D(4) xor D(2) xor D(1) xor C(1) xor C(25)
xor
C(26) xor C(28) xor C(29);
NewCRC(10) := D(5) xor D(3) xor D(2) xor D(0) xor C(2) xor C(24)
xor
C(26) xor C(27) xor C(29);
NewCRC(11) := D(4) xor D(3) xor D(1) xor D(0) xor C(3) xor C(24)
xor
C(25) xor C(27) xor C(28);
NewCRC(12) := D(6) xor D(5) xor D(4) xor D(2) xor D(1) xor D(0)
xor
C(4) xor C(24) xor C(25) xor C(26) xor C(28) xor
C(29) xor
C(30);
NewCRC(13) := D(7) xor D(6) xor D(5) xor D(3) xor D(2) xor D(1)
xor
C(5) xor C(25) xor C(26) xor C(27) xor C(29) xor
C(30) xor
C(31);
NewCRC(14) := D(7) xor D(6) xor D(4) xor D(3) xor D(2) xor C(6)
xor
C(26) xor C(27) xor C(28) xor C(30) xor C(31);
NewCRC(15) := D(7) xor D(5) xor D(4) xor D(3) xor C(7) xor C(27)
xor
C(28) xor C(29) xor C(31);
NewCRC(16) := D(5) xor D(4) xor D(0) xor C(8) xor C(24) xor C(28)
xor
C(29);
NewCRC(17) := D(6) xor D(5) xor D(1) xor C(9) xor C(25) xor C(29)
xor
C(30);
NewCRC(18) := D(7) xor D(6) xor D(2) xor C(10) xor C(26) xor C(30)
xor
C(31);
NewCRC(19) := D(7) xor D(3) xor C(11) xor C(27) xor C(31);
NewCRC(20) := D(4) xor C(12) xor C(28);
NewCRC(21) := D(5) xor C(13) xor C(29);
NewCRC(22) := D(0) xor C(14) xor C(24);
NewCRC(23) := D(6) xor D(1) xor D(0) xor C(15) xor C(24) xor C(25)
xor
C(30);
NewCRC(24) := D(7) xor D(2) xor D(1) xor C(16) xor C(25) xor C(26)
xor
C(31);
NewCRC(25) := D(3) xor D(2) xor C(17) xor C(26) xor C(27);
NewCRC(26) := D(6) xor D(4) xor D(3) xor D(0) xor C(18) xor C(24)
xor
C(27) xor C(28) xor C(30);
NewCRC(27) := D(7) xor D(5) xor D(4) xor D(1) xor C(19) xor C(25)
xor
C(28) xor C(29) xor C(31);
NewCRC(28) := D(6) xor D(5) xor D(2) xor C(20) xor C(26) xor C(29)
xor
C(30);
NewCRC(29) := D(7) xor D(6) xor D(3) xor C(21) xor C(27) xor C(30)
xor
C(31);
NewCRC(30) := D(7) xor D(4) xor C(22) xor C(28) xor C(31);
NewCRC(31) := D(5) xor C(23) xor C(29);
return NewCRC;
end nextCRC32_D8;
end PCK_CRC32_D8;
Thanks
Article: 117820
Hi all, I'm designing a small project which uses the primitive FIFO_16
of virtex 4. The problem is:
This FIFO uses an asynchronous reset, which resets all flags and
internal registers of FIFO. Reset signal doesn't reset data in and
data out. In my design, I have a synchronous reset and when it occurs
I need to do not have an output data from FIFO. Is it enough to add
some code lines, for example in the top module:
if (RST)
data_out_top_module<=0;
else
data_out_top_module<=data-out-fifo;
Or there exist another solution?
Thanks
Article: 117821i need a efficent FIR Polyphase second - order interpolator code i want to use it on Cyclone II .Plese help me ,Thank you!!!!!Article: 117822
Hi, On 10 Apr., 22:32, Amine.Mi...@gmail.com wrote: > anyone of you can explain me the problem or the behavior of this flip > flop please? The FF is right. The problem is what I would call clock skew. For VHDL- Simulations your FF will get the value it has at the input during the rising edge of clk. This is the first delta tick when clk='1'. If your "external" signal change is faster than your clock distribution, you will see the new value. e.g.: process (clk_ext) sig_ext <= new_value; end process; clk_i <= clk_ext; clk <= clk_i; process (clk) sig_i <= sig_ext; end process; This will lead to a race condition between data with respect to clock not in terms of ns, but in terms of simulation deltas. You won't see the difference in a simulator, as sig_i and clk changes in the same ns (ps,fs) but in different deltas. It is always a good idea to introduce a slight delay between clk and data in simulations (eg by using the after-clause). This delays should be large enough to be observable, but of course << than one clock periode. bye ThomasArticle: 117823
> Macro Statistics > # Block RAMs : 17 > 256x16-bit dual-port block RAM : 1 > 256x72-bit dual-port block RAM : 4 > 512x32-bit dual-port block RAM : 8 > 512x64-bit dual-port block RAM : 4 > > Macro statistics allow me to easily find out the size of all the memories > present in my design so I can cross-check with the final report to > determine whether or not the synthesis tools have mapped everything as > expected... and here, I do not remember what the 256x16 RAM is for so I'll > have to investigate where it came from next time I work on the project I > pasted this from. > Yup I saw this # RAMs : 24 16x64-bit dual-port distributed RAM : 6 1920x12-bit dual-port block RAM : 9 1920x12-bit registered dual-port distributed RAM : 3 4096x36-bit dual-port block RAM : 1 4096x9-bit dual-port block RAM : 2 8x64-bit dual-port distributed RAM : 3 Since then I have been playing around with my codes, and I can identify which instances in the codes are using which kind of RAM. > It takes forever because Map/PAR is unable to complete routing when all > memory gets forced into LUT memory. Remove (comment) this attribute > altogether to let synthesis tools decide which memories should be dumped in > BRAMs and which ones should use distributed memory. Alternatively, you > could add a generic port to the template to specify block or distributed on > a per-instance basis. > > Note: large distributed memories will become slow unless you add multiple > pipelining registers on their output so you should be careful when using these. > Currently I have tried to change some of the instances to use distributed ram, but forcing the constraint RAM_STYLE to be pipe_distributed And, going down the list of instances that uses the block ram, when I change it for for my 6 horizontal and 3 vertical coeffcient instances, viola, it immediately dropped down to 39 out of 36 block rams! Hmm, strange, it dropped so much. Anyway, next i try to work on some instances to change to use distributed rams. However, I have to be careful to have a balance of not overshooting the LUTs i have together with the block rams as well. Then I worked with some line buffer modules under my top modules and well after synthesis, everything was well under the resources limit. However, the problem came i tried to implement it. The user constraint file that belong trial synthesis had a timing constraint and my design timing was twice over this constraint. Then i used the timing analyzer and cross probe the problem and could see the path looked to be quite long. So now, i tried to work on this problem by using some of the optimization options in the ISE Under the map properties, I selected map option level as high. The runtime took really long, in the end, i got this message. The router has detected a very high timing score (5245937) for this design. It is extremely unlikely the router will be able to meet your timing requirements. To prevent excessive run time the router will change strategy. The router will now work to completely route this design but not to improve timing. This behavior will allow you to use the Static Timing Report and FPGA Editor to isolate the paths with timing problems. The cause of this behavior is either overly difficult constraints, or issues with the implementation or synthesis of logic in the critical timing path. If you would prefer the router continue trying to meet timing and you are willing to accept a long run time set the option "-xe c" to override the present behavior. I thinking of just trying to meet the timing. but when do or can I set the option "-xe c". I dont see any dos command line for me anywhere...Article: 117824
On Apr 5, 3:49 pm, zeli...@gmail.com wrote: > These are my experience from XilinxISEWebpack. > System: > Thinkpad R60 (Intel Core 2 duo) > Xubuntu 6.20 Edgy eft, 32bit > (Large extra SW installed: Eclipse, Openoffice, some other KDE apps) > > Tried software:ISEWebpack 9.1i I have now spent some time with ISE and I have some more experiences to share. ISE === ISE seems to work OK. Implemented some examples, ok. Simulator ======== Had lots of trouble with ISE Simulator, always resulting with error: "Simulator:607 - ISE Simulator is unable to elaborate this design due to specific coding constructs used in the design." No matter what I did, how simple the design was (just a counter with a simple testbench), always the same error. Today when I booted up my laptop after hibernating, ISE terminated (crashed?) so I started it again. Now simulation works! When the simulator is active, the simulator will steal 100% of one CPU. It still works though. Floorplan ========= bin/lin/floorplanner: error while loading shared libraries: libXm.so. 3: cannot open shared object file: No such file or directory This issue have been discussed earlier. (Motif library(?))
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