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"Brian Davis" <brimdavis@aol.com> wrote in message news:1180632225.125517.204220@h2g2000hsg.googlegroups.com... > Austin wrote: >> >> No, I am tied of the ranting. >> > And I am tired of your marketing misdirections. > >> >> Also, there were some customers that had really bad experiences trying >> to make their boards work. >> >> Far be it from me to suggest that these folks did something wrong, >> but I have to wonder why other customers have this working. >> > My boards work great, because I know when and how to be cautious > when driving FPGA inputs from fast logic. > Right, you beat me to it! This is the reason that I post on CAF; to share my experiences(whether good or bad). It seems to me that we all know _why_ the pins have high capacitance. It's because the chips are a compromise to work with many different I/O standards. Some of these standards require big FETs with high capacitance. That's fair enough, I'm sure FPGA vendors spend a lot of time and effort on marketing research and know that this is the best mix. However, I share Brian's frustration when it's implied that the Cpin is a 'good thing' because, for example, "cross talk is reduced". Not powering the part is another way to reduce crosstalk, and only a little less practical. Why not just say why the Cpin is 10pF, when this matters, and how to deal with the (hopefully few) cases where it may be a problem? IMO, this would be better than denying the problem exists at all. Indeed, this is the approach of this guy, who I believe consults for Xilinx. http://sigcon.com/Pubs/edn/TerminatorOne.htm (Look at the figure, is he timing 8ns with an egg timer? :-) http://sigcon.com/Pubs/edn/TerminatorTwo.htm http://sigcon.com/Pubs/edn/TerminatorThree.htm In summary, nobody expects FPGA parts to be the best at everything, and it's important to be careful when designing at the limits of performance. Best regards, Symon. p.s. God only knows what the OP thinks of this thread! I hope we haven't scared him off for good! :-)Article: 120051
Thank you guys for the suggrstions. I must transfer data for about 20cm in an almost continuous way. Guru have you tried the OPI_SPI with an off-chip master? Reading the datasheet it seems that Xilinx doesn't *guarantee* that with an off-chip Matster the OBP_SPI works but it seems (I hope) that sometime a missynchronization may occour... If you read the XAPP265 you can see that the peripheral they realize is *very* similar to an SPI... It doesn't seem that there are problems even at the high rate stated in the application note (840 Mb/s if i remember well...) Now I'm working on another project so I can't try to use OBP_SPI with off-chip master, but does anybody tried an OPB_SPI with an off-chip mater ? Let me know... Cheers, AndreaArticle: 120052
I'm simulating a DCM using Aldec Active-HDL 7.2 with Xilinx ISE 8.2i SP3 simulation libraries and I'm seeing LOCKED getting asserted at exactly the same time my CLKDV, CLKFX, and CLKFX180 output begin toggling. According to the Virtex-4 User Guide, the DCM output clocks are invalid until LOCKED is asserted. However, this is not what I'm seeing in simulation. Does this sound like a simulation model error or is this the actual behavior I will see in the hardware. I want to use the inverse of LOCKED as a reset for the upstream logic to guarantee it is held in reset until all the clocks are valid.Article: 120053
I am trying to use area_group in my constraints file, but I keep getting the error ERROR:NgdBuild:753 - "constraints.ucf" Line 5: Could not find instance(s) 'gclockInst' in the design. To suppress this error specify the correct instance name or remove the constraint. ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. ERROR:NgdBuild:19 - Errors found while parsing constraint file "constraints.ucf". I have tried this with several of the instances in my design, but I am having no success. I am running ISE Webpack 9.1.03i The instance is present and is not getting optimized away. I can see it in the floorplanner. Any suggestions on what I may be doing wrong?Article: 120054
Brian, I do SI simulations almost daily. I review PCB designs almost weekly. All boards get built. That is ~ 50 pcbs a year. Many of them for people like C****, A******-L*****, N*****, F******, N**, S***. They ask my shop to confirm that they will have a working pcb when they get it back, and I am happy to help them out. That way, the parts go on, the next order is received, and we sail into qualification, testing, and production release. I just love big orders for parts. I also get to see every pcb that fails SI, for any reason. And, I am often required to find the solution to fix it (which as you know can be impossible once the board is fabricated to fix anything). Customers are not shy when it comes to complaining when something doesn't work. When I go to Xilinx, we had 0 SI experts working for us. We now have SI people on the hotline, SI people in the applications group, SI people in the packaging group, SI people in the IO group, SI people in the field offices, SI FAE's, the RocketLabs facilities. Who do you think planned this all out, and created the system? I am bored by SI challenges, and I made sure there were trained experts who enjoyed SI challenges for customer support, so I can move on to things that are more fun (like the cases they couldn't solve). There are numerous pcbs that Xilinx makes for characterization, testing, SEU, signal integrity package validation, etc. I have to do the SI on them with my team, which also has a top notch SI engineer on it. My pcb designer did microwave radios for years and years. He solves wave equations in his head naturally (it is scary!). Do I qualify per your criteria? Does having (and using) my undergraduate degree in E&M theory enable me to say something? Is 31 years designing real products that people buy, mean anything to you? Just agree to disagree, and drop it. OK? Or, you agree that we are both a**h****, and just move on? Either is fine with me. AustinArticle: 120055
Symon wrote: > However, I share Brian's frustration when it's implied that the Cpin is a > 'good thing' because, for example, "cross talk is reduced". Not powering the > part is another way to reduce crosstalk, and only a little less practical. :) > > http://sigcon.com/Pubs/edn/TerminatorOne.htm (Look at the figure, is he > timing 8ns with an egg timer? :-) Yup, the original 'silicon chips' timer ;) -jgArticle: 120056
Just to put it in perspective: Amsterdam to Eindhoven is 120 km or 75 miles, barely an hour's drive. But 6 hours by bicycle, the favorite mode of transportation. Nice, flat country... :-) (I grew up just on the other side of that border, and rode my bike all over the Netherlands, long time ago.) Peter Nico Coesel wrote: > Peter Alfke <peter@xilinx.com> wrote: > >> Avnet picked Eindhoven as the preferred site in the Netherlands. > > They probably didn't want to drive too far themselves. Eindhoven is a > bit of a technology hotspot due to Philips but it is in the east part > of the country. Most people and companies are located in the west part > of the country. Most major events are therefore either located in > Amsterdam or Utrecht. > >> But the X-Fest seminar there was a month ago... >> But the traditional European FPGA conference will be in Amsterdam in >> August. > > Allright! >Article: 120057
On May 30, 4:06 pm, Peter Alfke <p...@xilinx.com> wrote: > On May 30, 3:08 pm, "u_stad...@yahoo.de" <u_stad...@yahoo.de> wrote: > > > hi > > > just a quick question: i saw that there is one x-fest in vienna on > > june 21. > > i am a student. can i register and attend aswell? and is it really > > free? > > > thanks > > Urban > > The answer is: Yes, yes, and yes. > The earlier engineers/students become familiar with our parts, the > better. > Herzlich willkommen. Es ist nie zu frueh, mit FPGAs vertraut zu > werden. > Peter So, to tie in with another part of this thread, FPGA's really are like drugs. Get them while they're young and the first hit is free. Alan Nishioka alan@nishioka.comArticle: 120058
On May 31, 11:01 am, ferorcue <le_m...@hotmail.com> wrote: > On May 29, 12:17 pm, "CTU FEE Jan Krakora" > > <krak...@control.felk.cvut.cz> wrote: > > To specify the problem, I thought the "Fatal: (vsim-3348)" one. Sorry Jan > > hi Jan, > > I still have the problem. I am using linux (debian) and the people > fromxilinxtold me today, that debian it is not supported, Only Red > Hat Enterprise 3. But this is very weird because I am using it, and it > works normally, the only think that is not working is thesimulation > in modelsim. > > I told one of my supervisors and he told me that he thinks that our > problem is not a problem of operating system or EDK, he thinks that it > is a problem of Modelsim. But I dont know how to solve it. > > I will continue trying to solve the problem, if you get a solution, > please let me know Hi, This message does not seem to be OS specific just as your supervisor said. I would bring it up again with the Xilinx tech support and ask them to try to reproduce it on their RH machine and if it is reproducible, then it is no longer OS specific. Everything I can see from the message makes it sound like it has to do with the EDK IP and not to do with the OS it is being run on. Thanks DuthArticle: 120059
Venkat wrote: > Can anyone suggest simple algorithms for implementation of finding the > inverse of a matrix (4 X 4)? Even information of IP Cores for such > functionality will be greatly appreciated. There might be a systolic array implementation that would make a convenient FPGA pipeline. How fast does it need to be? How big can it be? You will also need the appropriate floating point logic blocks. -- glenArticle: 120060
Just to answer my own question. I needed to use a wildcard with the instance. So instead of INST "fpu_inst" AREA_GROUP="fpu_group"; I needed to do INST "fpu_inst/*" AREA_GROUP="fpu_group"; Hopefully this will save someone else some trouble in the future. On May 31, 3:32 pm, javaguy11...@gmail.com wrote: > I am trying to use area_group in my constraints file, but I keep > getting the error > > ERROR:NgdBuild:753 - "constraints.ucf" Line 5: Could not find > instance(s) > 'gclockInst' in the design. To suppress this error specify the > correct > instance name or remove the constraint. > ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. > ERROR:NgdBuild:19 - Errors found while parsing constraint file > "constraints.ucf". > > I have tried this with several of the instances in my design, but I am > having no success. I am running ISE Webpack 9.1.03i > > The instance is present and is not getting optimized away. I can see > it in the floorplanner. > > Any suggestions on what I may be doing wrong?Article: 120061
Just to put it in perspective: Amsterdam to Eindhoven is 120 km or 75 miles, barely an hour's drive. But 6 hours by bicycle, the favorite mode of transportation. Nice, flat country... :-) (I grew up just on the other side of that border, and rode my bike all over the Netherlands, long time ago.) Peter On May 31, 10:42 am, n...@puntnl.niks (Nico Coesel) wrote: > Peter Alfke <p...@xilinx.com> wrote: > >Avnet picked Eindhoven as the preferred site in the Netherlands. > > They probably didn't want to drive too far themselves. Eindhoven is a > bit of a technology hotspot due to Philips but it is in the east part > of the country. Most people and companies are located in the west part > of the country. Most major events are therefore either located in > Amsterdam or Utrecht. > > >But the X-Fest seminar there was a month ago... > >But the traditional European FPGA conference will be in Amsterdam in > >August. > > Allright! > > -- > Reply to nico@nctdevpuntnl (punt=.) > Bedrijven en winkels vindt U opwww.adresboekje.nlArticle: 120062
Test01 wrote: > We have an application where I need to feed 160 differential data > inputs and 20 differential clock inputs to the high end V5 FPGA. > There is one differential clock for every 8 differential data inputs. > I would like to use LVPECL inputs for this. That sounds like a lot of ADS6425 parts ;-) Look through the DDR/DDR2/QDR app notes. The problem is very similar to using latching incoming byte lanes from DDR etc. memory.Article: 120063
Anyone know how the USB Blaster cable loads data to the C3 fpga on the board? The schematic shows a CPLD between the FPGA and the USB port. There is a USB to parallel chip between the cpld and the usb port. But I do not see any serial or parallel data going to the fpga. I wish Altera added more details to the starter kit documentation. There is all this source code but it is encrypted. So cannot even look at that. TIA -sanjayArticle: 120064
On May 31, 3:43 pm, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > Anyone know how the USB Blaster cable loads data to the C3 fpga on the > board? The schematic shows a CPLD between the FPGA and the USB port. > There is a USB to parallel chip between the cpld and the usb port. > But I do not see any serial or parallel data going to the fpga. > > I wish Altera added more details to the starter kit documentation. > There is all this source code but it is encrypted. So cannot even > look at that. > > TIA > -sanjay That CPLD along with the FT245 is the "embedded USB Blaster". You won't see any lines to the FPGA except for the JTAG leads. (I found the JTAG lines on the schematic - look again.) The documentation looked pretty complete to me. For the Xilinx board, the page of schematic with the USB loader is *missing*, and that area of the layout is obscured. Both companies used to ship separate dongles with their eval boards. But the plastic case of the dongle is the most expensive part, followed by the JTAG leads. By leaving those out, they can add the USB programmer for almost nothing. It's possible that both companies contracted out the design of their USB programming pods, so they can't (legally) distribute the information on the device. (Both companies make a ton of money selling IP; you have to understand that they will respect the IP rights of others.) Do a web search. There are a number of people actively tring to reverse engineer both dongles. At least until they discover hat they're spending 100's of hours to duplicate a gizmo that can be had for $50... G.Article: 120065
On May 29, 7:31 pm, bngguy <bng...@gmail.com> wrote: > Hi, > I'm working on implementing anFIRFilter on aFPGA(Spartan 3E), > here's what i want to accomplish --> > > TheFIRFilter coefficients are generated on a host system using > LabView, these coefficients are written to a RAM / PROM on a DSP > card , the number of taps is constant but other parameters like > sampling frequency and cut off frequencies can change according to > requirements. > > TheFPGAreads these coefficients from the RAM / PROM and implements > theFIRFilter.There should be a single bit file that is downloaded to > configure theFPGA. > > Any pointers in the right direction would be appreciated. > > Thanks > Tim Hi Tim, There's two halves to the question. The first is getting the coefficient values into the FPGA, and the second is creating/using a FIR structure which allows for coefficient reload. There's a new FIR filter design tool which creates clear text human readable Verilog based FIR filters (which can be synthesized to Spartan 3 with Xilinx ISE) with a coefficient reload option. If you want, you can also store multiple coefficient sets in the filter without having to reload them, and simply switch among the various sets (this works well for deeper memory, ie: store several sets on-line and switch among them). Anyway, here's a link : http://www.optunis.com/fir_hdl_writer/fir_hdl_writer_info.html Hope this helps, TonyArticle: 120066
On May 29, 7:31 pm, bngguy <bng...@gmail.com> wrote: > Hi, > I'm working on implementing anFIRFilter on aFPGA(Spartan 3E), > here's what i want to accomplish --> > > TheFIRFilter coefficients are generated on a host system using > LabView, these coefficients are written to a RAM / PROM on a DSP > card , the number of taps is constant but other parameters like > sampling frequency and cut off frequencies can change according to > requirements. > > TheFPGAreads these coefficients from the RAM / PROM and implements > theFIRFilter.There should be a single bit file that is downloaded to > configure theFPGA. > > Any pointers in the right direction would be appreciated. > > Thanks > Tim It looks like you'd like to quickly easily reload or change coefficients in a FIR filter (so you may want to just load in the coefficient values into a multiplier based FIR filter, rather than have to generate ROM LUT values to load into a distributed arithmetic FIR filter). There's a new tool which creates clear text human readable Verilog code for FIR filters (which can be synthesized into a Spartan with ISE). Options include reloadable coefficients as well as multiple coefficient sets. There's a self checking testbench with impulse, step and random response. You don't mention how fast your computation rate is, but this tool supports single or multiple clocks per computation (so you can decrease your multiplier usage). Anyway, here's a link : http://www.optunis.com/fir_hdl_writer/fir_hdl_writer_info.html Hope this helps, TonyArticle: 120067
On May 2, 10:01 pm, Gordon Freeman <gordonfreeman1...@gmail.com> wrote: > On Apr 26, 12:01 am, ghel...@lycos.com wrote: > > > > > On Apr 24, 4:06 am, Gordon Freeman <gordonfreeman1...@gmail.com> > > wrote: > > > > On Apr 24, 4:29 pm,FPGA<esp...@gmail.com> wrote: > > > > > Hi Gordon, > > > > > The core generator only generates the netlist for the IP with Verilog/ > > > > VHDL wrapper file functional simulation. > > > > If you use ISE, then you can generate the core inside the ISE and you > > > > can instantiate the core in your design. > > > > Just right click on your project and select "New source" and > > > > IP(Coregen & Arch Wizard) and you can generate > > > > the same core and ISE will add the necessary files automatically. > > > > > William > > > > On Apr 24, 12:16 am, Gordon Freeman <gordonfreeman1...@gmail.com> > > > > wrote: > > > > > > Hi everyone! > > > > > I use Xilinx Core generator to generate DAFIRfilter. Right now, I > > > > > want to take the verilog code for DAFIRfilter but I don't know how > > > > > can I do it. > > > > > Can you help me? > > > > Thank you for your reply. > > > But I can't modify it. > > > Can you show me how to take the verilog code for synthesize? I would > > > like to know how they process in this code.- Hide quoted text - > > > > - Show quoted text - > > > I think you do not understand: There is no verilog code to take. > > > It is a "black-box macro"; the verilog wrapper just sets the > > parameters (configuration) of that macro. > > > You might be able to learn something by doing a gate level simulation, > > but that would be very tedious. > > > GH. > > Thank you very much! > I think I must design it. I have found document talk about DA forFIR > filter. Ahhh.... The perils of vendor "black box" or encrypted designs. They're difficult to simulate. Use them, and they lock you into a system. If there's a bug, you're dependent on the vendor to fix it. There's a new EDA tool which makes clear text Verilog synthesizable source code for FIR filters (even testbenches for impulse, step, and random response), called the FIR HDL Writer from Optunis. Here's a web link : http://www.optunis.com/fir_hdl_writer/fir_hdl_writer_info.html Hope this helps, TonyArticle: 120068
Sandro wrote: > I know the "Spartan-3E 1600E MicroBlaze Development Kit" use the same > board ...but I don't need EDK... Buy it, and resell the EDK? At some point Digilent will probably start selling that board directly, without the EDK. Their deal with Xilinx might have an exclusivity period, or they might just not yet be able to build more than Xilinx is ordering. But the other Digilent boards sold by Xilinx have eventually become available directly from Digilent. I got one recently (and did need the EDK), but I don't need the Platform USB Cable, as I already had one. I'll probably find a use for the second one eventually. I was somewhat surprised that it is bundled with the Platform USB Cable, since the equivalent of that cable is actually built into the board. When I read the specs, I thought the mention of a USB cable meant that they were including just a literal USB cable to plug the board into a USB host. If you actually need the board, EDK, and a Platform USB Cable, it's quite a bargain. EricArticle: 120069
On Apr 11, 12:14 am, "kangwei...@gmail.com" <kangwei...@gmail.com> wrote: > i need a efficent FIRPolyphase second - order interpolator code > i want to use it on Cyclone II .Plese help me ,Thank you!!!!! It sounds from your request that you want to create a polyphase decomposed interpolation FIR Filter for Cyclone II. Forgive me, but this is a little general purpose. You probably want to specify the interpolation factor, the number of clocks to produce an output, etc. There's a new EDA tool which creates clear text human readable Verilog source code, which you can synthesize to Cyclone II. It even generates a testbench for impulse, step and random response. It's from Optunis, and is called the FIR HDL Writer. Here's a link : http://www.optunis.com/fir_hdl_writer/fir_hdl_writer_info.html Best of luck, TonyArticle: 120070
I am bit concerned about shear number of channels - 160 differential inputs each running at 800 Mbps. Is this possible using V5 110 device?Article: 120071
MM wrote:
> Thanks a lot Ken!
>
>> Depending what version of Kubuntu you're running, you may have other
>> troubles. For example, if you get errors referencing GLIBC you need
>> to set the environment variable LD_ASSUME_KERNEL=2.4.7 (this is not a
>> problem in recent releases of ISE/EDK).
>
> I am running Kubuntu 7.04, 32-bit version and the 9.1 version of the Xilinx
> tools. I don't recall seeing this error...
Good, that combination should be fine (one of my systems is Ubuntu 6.10,
I had no trouble).
>> Getting a download cable to work is also a treat. I recommend ignoring
>> the Xilinx drivers and use the userspace driver from:
>>
>> http://www.rmdir.de/~michael/xilinx/
>
> That's really a great advice! I was just in the middle of the process of
> trying to install Xilinx drivers :) Hopefully I haven't broken anything yet
> by half-working scripts :)
You'll still need the bit of the installation that handles usb firmware
loading (fxload) and permissions settings, but a variant of it.
At the moment, the only Xilinx-related stuff in my system directories
is a file /etc/udev/rules.d/xusbdfwu.rules containing the following:
----VVV
SYSFS{idVendor}=="03fd", SYSFS{idProduct}=="0008", NAME="windrvr6"
BUS=="usb", ACTION=="add", SYSFS{idVendor}=="03fd",
SYSFS{idProduct}=="0007", RUN+="/sbin/fxload -v -t fx2 -I
/usr/share/xusbdfwu.hex -D $TEMPNODE"
BUS=="usb", ACTION=="add", SYSFS{idVendor}=="03fd",
SYSFS{idProduct}=="0009", RUN+="/sbin/fxload -v -t fx2 -I
/usr/share/xusbdfwu.hex -D $TEMPNODE"
BUS=="usb", ACTION=="add", SYSFS{idVendor}=="03fd",
SYSFS{idProduct}=="000b", RUN+="/sbin/fxload -v -t fx2 -I
/usr/share/xusbdfwu.hex -D $TEMPNODE"
BUS=="usb", ACTION=="add", SYSFS{idVendor}=="03fd",
SYSFS{idProduct}=="000d", RUN+="/sbin/fxload -v -t fx2 -I
/usr/share/xusbdfwu.hex -D $TEMPNODE"
BUS=="usb", ACTION=="add", SYSFS{idVendor}=="03fd",
SYSFS{idProduct}=="000f", RUN+="/sbin/fxload -v -t fx2 -I
/usr/share/xusbdfwu.hex -D $TEMPNODE"
ACTION=="add", BUS=="usb", SYSFS{idVendor}=="03fd",
SYSFS{idProduct}=="0008", MODE="0666"
----^^^
Since the above is almost certainly mangled by my mailer, I separated
what should be single lines in the file with blank lines. In other
words, there is one line that starts with SYSFS{idVendor} and
ends with "windrvr6" (I think that line is actually not necessary,
but it's harmless), the next line starts with BUS=="usb" and ends
with $TEMPNODE, four more similar lines with different product IDs,
then a line that starts with ACTION and ends with "0666".
Note that the name of the file seems to be relavent - udev processes
rule files in order of filename, and getting the Xilinx stuff too early
seems to not work (i.e. I initially had this in a file "10-custom.rules"
but it didn't work there). I don't understand udev well enough to
know why that makes it break.
Anyway, since you're just starting to install the cable drivers I'll
follow up my own post with a description of how I got the userspace
shim to work transparently..
>> I have it working for impact, chipscope analyzer, and XMD, at least
>> in all modes I actually use. I can elaborate further all the fun I
>> had getting it to work on a 64-bit system, if that's something you'll
>> need (post here but CC my email to be sure I see it; I don't check
>> every day).
>
> It's interesting. I was told in the past by Xilinx that EDK wasn't working
> on 64-bit systems... Have they fixed it in 9.1 or have you found a
> workaround?
EDK does not work with a 64-bit ISE installation. I have both ISE and
EDK installed as 32-bit applications. The OS is the x86_64 version of
SuSE 9.3; the fact that all of the system binaries are 64 bit caused me
some pain getting it installed and getting the userspace cable driver to
work (to force the 32-bit ISE install, don't run setup at the top of the
installation directory; cd to bin/lin and run it from there. That is
also needed for all the service packs and IP updates). I have a 64-bit
ISE installation standing by should I need it, but I haven't yet had a
design big enough where it matters. [Note that running 32 bit will be a
bit faster, measurably so for long runs, due to the smaller pointer
sizes getting fetched more efficiently by the CPU].
>> In any case, it works great on my Linux boxen which is a relief since
>> EDK does not get along with my laptop at all (multiple applications
>> built on top of Cygwin are not playing nice at all).
>>
>> Good luck, and drop me a note if you need more help.
>
> Thanks again,
> /Mikhail
>
>
Article: 120072
Hi,
I'm working on implementing an FIR Filter on a FPGA (Spartan 3E),
here's what i want to accomplish -->
The FIR Filter coefficients are generated on a host system using
LabView, these coefficients are written to a RAM / PROM on a DSP
card , the number of taps is constant but other parameters like
sampling frequency and cut off frequencies can change according to
requirements.
The FPGA reads these coefficients from the RAM / PROM and implements
the FIR Filter.There should be a single bit file that is downloaded to
configure the FPGA.
Any pointers in the right direction would be appreciated.
Thanks
Tim
Article: 120073I am trying to use area_group in my constraints file, but I keep getting the error ERROR:NgdBuild:753 - "constraints.ucf" Line 5: Could not find instance(s) 'gclockInst' in the design. To suppress this error specify the correct instance name or remove the constraint. ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. ERROR:NgdBuild:19 - Errors found while parsing constraint file "constraints.ucf". I have tried this with several of the instances in my design, but I am having no success. I am running ISE Webpack 9.1.03i The instance is present and is not getting optimized away. I can see it in the floorplanner. Any suggestions on what I may be doing wrong?Article: 120074
Ken Ryan wrote: > Anyway, since you're just starting to install the cable drivers I'll > follow up my own post with a description of how I got the userspace > shim to work transparently.. OK here goes... Note this applies to the USB driver. Theoretically it also works with the parallel cable, but I haven't tested it. First, add the file /etc/udev/rules.d/xusbdfwu.rules as I described in my previous post. That gets the firmware loaded and device permissions set when you connect the usb cable. I *think* it's tailored narrowly enough to not open unwise permissions, but if it matters to you have someone with a clue about security look it over. Next download the userspace shim sources from http://www.rmdir.de/~michael/xilinx/ and compile them. For those on a 64-bit OS, edit the Makefile and add -m32 to the CFLAGS variable to force a 32-bit compile. Now, there seem to actually be only three binaries that try to communicate with the cable hardware: $XILINX/bin/lin/_impact iMPACT bitstream downloader (core) $CHIPSCOPE/bin/lin/cse Chipscope cable server $XILINX_EDK/bin/lin/xmd Software debugger server To use the driver shim, they each need the libusb_driver.so prelinked to intercept the windrvr calls. On a pure 32-bit platform you could simply set the environment variable LD_PRELOAD to the full pathname of the libusb_driver.so, but then the system attempts to prelink *all* of your binaries to that library. On a 64-bit platform this fails miserably. So I did the following: 1. Copy libusb_driver.so to $XILINX/bin/lin/ to ensure it's available for all users of the system (in my case: me, myself and I but whatever). 2. Rename $XILINX/bin/lin/_impact to $XILINX/bin/lin/_impact.bin (note 'm renaming _impact not impact). 3. Create a shell script called $XILINX/bin/lin/_impact containing the following: ---VVV #!/bin/sh # # Preload driver binary LD_PRELOAD=$XILINX/bin/lin/libusb-driver.so $0.bin $* ---^^^ 4. Ensure the script permissions are set with chmod +x. 5. Repeat steps 2-4 for the Chipscope and XMD binaries, as applicable. I use the identical script file in all three places; the $0.bin and different name ensures the right thing gets run. 6. Enjoy! Note that installing a service pack may overwrite this hack (the EDK9.1.02 service pack did that to the xmd script). Just repeat steps 2-4 to fix it. What's happening: I initially just used a csh alias to include the LD_PRELOAD, but that only worked for direct command-line invocations. Running any of these from a GUI bypasses the shell. Similarly, putting a script in the search path doesn't work, as the GUIs seem to call their helper programs via a direct path. By putting an executable shell script directly in the places where callers look for it, you can add the prelink and the Linux system libaries will sort out whether it's executing a binary or a shell script. The impact program was a bit weird, and threw me for a little while on my 64-bit box. The binary $XILINX/bin/lin/impact is what gets started, but after doing some initial stuff it then calls _impact to do the heavy lifting. I have no idea why that is so - perhaps _impact does the downloading and something else does the prom file preparation, and impact is just the front-end wrapper. It did have the bizarre behavior of working properly if I just ran impact alone, but if I added any command-line parameters it failed (the resulting message was highly misleading as well - failed to find libusb-driver.so even though the error message itself included the complete correct path...the clue was the error message was from tcsh not impact, indicating impact actually invoked my shell to execute _impact). I have used impact, chipscope analyser.sh and xmd with this setup, both direct from the command line and impact/xmd from within the xps GUI. If I were Xilinx I would jump on this userspace driver and can the kernel driver. Aside from debatable kernel module license issues, the userspace driver means users are mucking with their system a whole lot less, which *surely* has to reduce support calls! Three cheers to Michael Gernoth for his outstanding work in solving this problem (not to mention realizing it *could* be solved)! ken
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