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The problem has been solved: $ export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$XILINX/bin/lin /MikhailArticle: 120151
Any input on this will be greatArticle: 120152
> I read somewhere, there may be a conflict when using ICAP and JTAG. > Do anybody have any information about this? That is correct. Read the "Important Note" paragraph on page 3 of http://www.xilinx.com/bvdocs/ipcenter/data_sheet/opb_hwicap.pdf (actual page number is 70): "Important Note: The HWICAP core uses the ICAP found inside Virtex IITM and Virtex-II ProTM devices. The ICAP port interface is similar to the SelectMAP interface, but is accessible from general interconnects rather than the device pins. The JTAG or “Boundary Scan” configuration mode pin setting (M2:M0 = 101) will disable the ICAP interface. Therefore, when using the HWICAP core, another mode pin setting must be used. If JTAG will be used as the primary configuration method, select another mode pin setting to avoid disabling the ICAP interface. JTAG configuration will still be available because it overrides other means of configuration, and the HWICAP core will function as intended." "Besides being disabled with the Boundary Scan mode pin setting, the ICAP will be disabled if the persist bit in the device configuration logic’s control register is set. When using bitgen one must make sure that the Persist option is set to No, which is the default. This option is generally specified in the bitgen.ut file in the etc subdirectory of the EDK project."Article: 120153
Like so many who've come before more me I'm having problem getting the
Xilinx Parallel Port cable to work. I know there've been many posts on
this issue, but I'm still having trouble.
My system is a Fedora Core 2 running a 2.6.5-1.358 kernal.
The only parallel port on the computer is a PCI card with NetMOS Nm9805CV
chipset.
+The relevant output of "more /proc/pci":
Bus 4, device 1, function 0:
Class 0780: PCI device 9710:9805 (rev 1).
IRQ 11.
Master Capable. Latency=64.
I/O at 0xc400 [0xc407].
I/O at 0xc000 [0xc007].
I/O at 0xb800 [0xb807].
I/O at 0xb400 [0xb407].
I/O at 0xb000 [0xb007].
I/O at 0xa800 [0xa80f].
+The relevant output from "lspci -v":
04:01.0 Communication controller: NetMos Technology: Unknown device 9805
(rev 01) Subsystem: LSI Logic / Symbios Logic: Unknown device 0010
Flags: medium devsel, IRQ 11
I/O ports at c400
I/O ports at c000 [size=8]
I/O ports at b800 [size=8]
I/O ports at b400 [size=8]
I/O ports at b000 [size=8]
I/O ports at a800 [size=16]
+From "dmesg":
parport0: PC-style at 0x378 [PCSPP]
+And finally from iIMPACT 8.2i:
Connecting to cable (Parallel Port - parport0).
WinDriver v6.22 Jungo (c) 1997 - 2004 Build Date: Jul 25 2004 X86
19:07:39.
LPT base address = 0378h.
ECP base address = 0778h.
Cable connection failed.
Reusing 79118001 key.
Reusing FD118001 key.
Connecting to cable (Parallel Port - parport1).
WinDriver v6.22 Jungo (c) 1997 - 2004 Build Date: Jul 25 2004 X86
19:07:39.
Cable connection failed.
Reusing 7A118001 key.
Reusing FE118001 key.
(continuing through the other parports and USB)
I also have both windrvr6 and xpc4drvr modules loaded.
When I tried
rmmod parport_pc.o
insmod parport_pc.o io=0xc000 irq=11
the computer crashed.
My guess is since the cable connection fails immediately after determining
the base addresses for LPT and ECP on parport0 that Linux is not properly
seeing the PCI card, so it's not a problem with the Xilinx drivers.
Is there some way to test if a PCI card is properly installed? Some
hardware version of ping perhaps?
Thanks,
Laura
Article: 120154As seems to be the case, after I post a message asking for help I find what I am looking for. A few places that have some modular design examples: http://ic2.epfl.ch/~gmermoud/DPRtutorial.zip and http://wiki.ittc.ku.edu/rtrjvm/EDK_and_MD On Jun 1, 4:51 pm, javaguy11...@gmail.com wrote: > Is there anexampleof amodulardesignproject for ISE that I can > download. > I could not find one on the xilnx website or included in the ISE > examples directory > Beyond a picture shown in the Development System Reference Guide and > reading the chapter onmodulardesign, I am really no closer to > understanding how to setup such a project.Article: 120155
We are trying to build an ipcore in XPS. Based on the vhdl code we got from digilent's site, we are trying to interface with a graphics lcd on a Nexys. The vhdl code uses an inout port and from our understanding requires a tri-state to become an ipcore. When we are trying generate the netlist in XPS, we get the error: ERROR:Xst:2585 - Port <dbLcd_I> of instance <fsl_glcd_controller_0> does not exist in definition <fsl_glcd_controller>. ERROR:Xst:2585 - Port <dbLcd_O> of instance <fsl_glcd_controller_0> does not exist in definition <fsl_glcd_controller>. ERROR:Xst:2585 - Port <dbLcd_T> of instance <fsl_glcd_controller_0> does not exist in definition <fsl_glcd_controller>. We are unsure how to continue. Send help.Article: 120156
A memory block has been told having "read latency of 3", assume the read pointer has been reset How many read clocks does it take to read out the first 10 bytes? How many read cycles does it take to read out the next 8 bytes? Where's the read data? Assume the first rising edge of read clock is labled C0, next edge is C1, C2, C3...Article: 120157
Since you work at Xilinx, wouldn't there be many people there who can answer your question. I'm sure they know their own devices better than any of us. ---Matthew Hicks > Any input on this will be great >Article: 120158
I wish I did work at Xilinx. Any input will be great.Article: 120159
Woo look I can post from www.xtra.xilinx.com too does that mean I work for Xilinx?Article: 120160
Thank you Paul. You have detailed everything. I got more than I want. lolArticle: 120161
Yeah I figured that I would make that assertion and I would quickly get something along the response you gave. Upon further searching (www.xtra.xilinx.xom just forwards to xilinx) I see that they provide forums. I stand corrected. To answer the question, the pure number of differential signals isn't a problem, but that's a lot of clocks, in fact the Virtex 5 only has 20 clock inputs. Assuming you don't need another clock in your design, you would be fine. You might be able to save the special clock routing channels by using placement constraints and well thought-out pin assignments to minimize clock routing using the standard routing channels. Things of concern are metastabilty when trying to group all of the data channels together using a single fabric clock and the phase difference between all of the 20 clocks. ---Matthew Hicks > Woo look I can post from www.xtra.xilinx.com too does that mean I work > for Xilinx? >Article: 120162
On Jun 1, 6:38 pm, Marlboro <cco...@netscape.net> wrote: > A memory block has been told having "read latency of 3", assume the > read pointer has been reset > > How many read clocks does it take to read out the first 10 bytes? As many as it has too, gosh!! Tommy (applogies to Napoleon)Article: 120163
lgs23 schrieb: > Like so many who've come before more me I'm having problem getting the > Xilinx Parallel Port cable to work. I know there've been many posts on > this issue, but I'm still having trouble. > > My system is a Fedora Core 2 running a 2.6.5-1.358 kernal. > The only parallel port on the computer is a PCI card with NetMOS Nm9805CV > chipset. > > > +The relevant output of "more /proc/pci": > > Bus 4, device 1, function 0: > Class 0780: PCI device 9710:9805 (rev 1). > IRQ 11. > Master Capable. Latency=3D64. > I/O at 0xc400 [0xc407]. > I/O at 0xc000 [0xc007]. > I/O at 0xb800 [0xb807]. > I/O at 0xb400 [0xb407]. > I/O at 0xb000 [0xb007]. > I/O at 0xa800 [0xa80f]. > > +The relevant output from "lspci -v": > > 04:01.0 Communication controller: NetMos Technology: Unknown device 9805 > (rev 01) Subsystem: LSI Logic / Symbios Logic: Unknown device 0010 > Flags: medium devsel, IRQ 11 > I/O ports at c400 > I/O ports at c000 [size=3D8] > I/O ports at b800 [size=3D8] > I/O ports at b400 [size=3D8] > I/O ports at b000 [size=3D8] > I/O ports at a800 [size=3D16] > > +From "dmesg": > parport0: PC-style at 0x378 [PCSPP] > > > +And finally from iIMPACT 8.2i: > > Connecting to cable (Parallel Port - parport0). > WinDriver v6.22 Jungo (c) 1997 - 2004 Build Date: Jul 25 2004 X86 > 19:07:39. > LPT base address =3D 0378h. > ECP base address =3D 0778h. > Cable connection failed. > Reusing 79118001 key. > Reusing FD118001 key. > Connecting to cable (Parallel Port - parport1). > WinDriver v6.22 Jungo (c) 1997 - 2004 Build Date: Jul 25 2004 X86 > 19:07:39. > Cable connection failed. > Reusing 7A118001 key. > Reusing FE118001 key. > (continuing through the other parports and USB) > > > I also have both windrvr6 and xpc4drvr modules loaded. > When I tried > > rmmod parport_pc.o > insmod parport_pc.o io=3D0xc000 irq=3D11 > > the computer crashed. > > My guess is since the cable connection fails immediately after determining > the base addresses for LPT and ECP on parport0 that Linux is not properly > seeing the PCI card, so it's not a problem with the Xilinx drivers. > Is there some way to test if a PCI card is properly installed? Some > hardware version of ping perhaps? > > Thanks, > Laura on windows you can use this non standard PCI LPT card by sett=EDng special env variables set XIL_IMPACT_ENV_LPT_BASE_ADDRESS=3D set XIL_IMPACT_ENV_LPT_ECP_ADDRESS=3D dont know if that is possible under linux or not AnttiArticle: 120164
I've been looking at the various core/macro generators and they all seem horribly large and slow, almost like student designs. Has anyone seriously taken a good look at hand fitting multipliers and squarers into Altera/Xilinx FPGA's?Article: 120165
Dear All, Since the program cannot fit in an internal ram, I have to use external memory, such as ddr. As Xilinx edk indicates debugger, bootloader or ACE file should be used to initialize memory before the program can be executed. But I don't know how to initialze memory by using one of above methods. Could anyone enlighten me on it ? Thanks in advance, YaoArticle: 120166
Matthew Hicks wrote: > To answer the question, the pure number of differential signals isn't a > problem, but that's a lot of clocks, in fact the Virtex 5 only has 20 > clock inputs. Assuming you don't need another clock in your design, you > would be fine. You might be able to save the special clock routing > channels by using placement constraints and well thought-out pin > assignments to minimize clock routing using the standard routing channels. Using IO clocks instead of global clocks would be a solution. I'm not sure how many IO clocks a V5 that size has, though. But Jim Wu's ADEPT can help with that: http://home.comcast.net/~jimwu88/tools/adept/ IO clocks can only clock the ISERDES inside adjacent IOs, but that is exactly what is needed in this type of application. So you would clock the ISERDES with the IO-clock, do the 1:4-deserialization there, and use a divided by 4 clock as the write clock to a nearby FIFO. Have a look at xapp866: http://direct.xilinx.com/bvdocs/appnotes/xapp866.pdf, which describes a similar application. Problem there is that you have to use specific pins to connect the clock to, and a specific group of pins for the corresponding data pairs (again, ADEPT will help with the pin assignment). This usually makes PCB layout harder, because you can't just connect everything so you have matched-length differential pairs without vias and such, which you would usually try to achieve. HTH, Sean -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 120167
On Jun 2, 12:26 am, Tommy Thorn <tommy.th...@gmail.com> wrote: > On Jun 1, 6:38 pm, Marlboro <cco...@netscape.net> wrote: > > > A memory block has been told having "read latency of 3", assume the > > read pointer has been reset > > > How many read clocks does it take to read out the first 10 bytes? > > As many as it has too, gosh!! Lol, I meant the min. number of clock cycle it takes to read out the first 10 bytesArticle: 120168
bwilson79@gmail.com <bwilson79@gmail.com> wrote: > I want to use the inverse of LOCKED as a reset for the upstream logic to > guarantee it is held in reset until all the clocks are valid. .. and consider to set the DCM attribute/generic "startup" to true. WD --Article: 120169
Thanks for your feedback. I will utilize the recommended tool and the application note in my application. I do have a couple of questions: (1) With internal 1 to 4 deserializer as recommended, the internal data bus will be 640 bits wide at 200 MHz. I would like to buffer this externally using deep FIFO. If the FPGA has enough number of pins, is it OK to also include the 640 bits wide, 200MHz external FIFO in the same FPGA as the 180 differential input, 800Mbps interface? I was thinking about using Virtex5 110 device for this application. It will be great to get your feedback. (2) For similarly configured differential outputs from another FPGA (I call it transmitter FPGA) are there any concerns of simultaneous switch noise? 180 differntial outputs switching simultaneouly at 800Mbps. As per my understanding, the simultaneous switching noise applies more to the single ended outputs and not as much to the differential output. The common mode noise on differential noise (ss noise) will be there but it will be subtracted by the receiver. Is that correct?Article: 120170
On Jun 2, 5:26 am, Yao Sics <yao.s...@gmail.com> wrote: > Dear All, > > Since the program cannot fit in an internal ram, I have to use > external memory, such as ddr. As Xilinx edk indicates debugger, > bootloader or ACE file should be used to initialize memory before the > program can be executed. But I don't know how to initialze memory by > using one of above methods. Could anyone enlighten me on it ? > > Thanks in advance, > > Yao One method I employ for this is to use a small amount of internal ram (BRAM) to handle a bootloader. The bootloader would read the application from an external non-volatile storage (such as FLASH) and load it into the RAM for execution. It then jump's to the application entry point and the application begins execution. Now if you want to just test the application, you can use XMD to dynamically download the application directly to RAM for testing purposes. To perform that, with your JTAG cable connected and a valid image on the FPGA, you would perform the following from the xygwin bash shell (or real shell if you're lucky enough to be using *nix): 1) xmd 2) connect mb mdm -- This is for a MicroBlaze, which requires having the opb_mbm core in the project 3) connect powerpc<0, or 1> -- This is for a PowerPC 4) dow <executable file name> Now you're application would be downloaded to RAM and it can execute as normal. To build your application to reside in RAM, you need to either configure the default linker to set the application to reside in RAM, or set the default settings to set it in RAM, and make sure you don't have the application set to initialize BRAM. Mike KossArticle: 120171
I have a design using the MPMC2 with a PowerPC and a CDMAC w/ LocalLink TEMAC on a Virtex4-FX. On the ppc I have Linux 2.6.22-rc2 running. The system can ping and simple UDP messaging has been working. When I attempted to perform TCP communication, the packets were never being received by another linux system. I took a look at the messages on the write and the 3rd and 4th byte of the ethernet destination are wrong. Added debug messages to the kernel to see the data that was being passed, and it was (of course) correct. After grabbing the physical addresses of the buffers, I once again checked them using xmd and it showed the same result. The corruption occurs everytime, and different memory locations are being used. Is it possible that the CDMAC is doing some operation on the data and accidentally corrupting it? TIA, Mike KossArticle: 120172
I have a system on a Virtex4-FX with a MicroBlaze and the xilinx opb_emc (v 2.00). I thought I set up the parameters properly to match the async FLASH memory chip that I have on my development board, but the controller does not look to be respecting the settings I set. I have the system running at 100MHz, and the external FLASH chip is a 70ns Spansion part. On a read, the address needs to stay valid for 70ns, but it's only staying valid for ~2 cycles (where the cycles are based upon the 100MHz clock, and observed using ChipScope). The same happens for a write, for say putting the chip into CFI mode, the write line is only staying asserted for ~2 cycles when it needs to be 70ns as well. I tried increasing the timespec values for the ipcore, but the external operation stayed exactly the same even if I doubled the requirements. Has anyone seen or experienced similar problems? TIA, Mike KossArticle: 120173
Hi I have problem to implement a FIFO with "Synchronous WRITE, Asynchronous READ" in Xilinx device. Since the FIFO size is large (more than 48-deep words), I would like to use BRAM or Built-in FIFO. I tried "Synchronous WRITE, Synchronous READ" using dual-ported BRAM and it seems okay. Problem is that Every time we 'read', one cycle delay occurs. I want to 'immediately read' a data in the location that the "read address" points to. I am not finding a way to implement "Asynchronous READ" in BRAM. If anyone has this experience, please let us know. Thank you in advanceArticle: 120174
On Sat, 2007-06-02 at 13:08 +0000, morphiend wrote: > I have a system on a Virtex4-FX with a MicroBlaze and the xilinx > opb_emc (v 2.00). I thought I set up the parameters properly to match > the async FLASH memory chip that I have on my development board, but > the controller does not look to be respecting the settings I set. > > I have the system running at 100MHz, and the external FLASH chip is a > 70ns Spansion part. On a read, the address needs to stay valid for > 70ns, but it's only staying valid for ~2 cycles (where the cycles are > based upon the 100MHz clock, and observed using ChipScope). The same > happens for a write, for say putting the chip into CFI mode, the write > line is only staying asserted for ~2 cycles when it needs to be 70ns > as well. > > I tried increasing the timespec values for the ipcore, but the > external operation stayed exactly the same even if I doubled the > requirements. > > Has anyone seen or experienced similar problems? > > TIA, > > Mike Koss > Mike, Did you set the memory type to asynchronous? What you describe looks like synchronous mode. Jan
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