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On 5 Jun., 11:17, "Tim (one of many)" <t...@nooospam.roockyloogic.com> wrote: > austin wrote: > > > Unfortunately, Steve Knapp has left Xilinx to pursue an opportunity that > > intrigued him. We will miss him. > > If he's reading this, many thanks to Steve for all the help and support > over the years. And good luck for the future. If at first you don't > succeed, try and try and Triscend again. did Steve work at Triscend? I felt bad when Triscend was killed.. they had nice new prouduct lineup ready, but then all that got killed. sure some of the features planned for Triscend latest chips are now part of V4-V5, but having one less player in FPGA field is still a bit sad. I think Triscend products (those that never come out) would have had success I am referring here to triscend never announced FPGA+ARM +ethernet+ADC chips. AnttiArticle: 120301
Hi I would like some advice on how to decide on the specfication of oscillator required for a Virtex 4 MGT. I have had a look in the user guide and it recommends one by Epson. However is doesnt say how they arrived at this. Is there any sort of forumla that can be used to calculate parameters like max jitter for the data rate required. Cheers JonArticle: 120302
On Mon, 04 Jun 2007 12:46:51 -0000, "mahalingamv@gmail.com" <mahalingamv@gmail.com> wrote: >hey motty, > >i tried connecting it the port myclk to a temproary signal and then >to the fabtric, did not work. > >secondly. tried placing a bufg component in between port myclk and >mynewclk and the error is still the same Needs an ibufg, not a bufg component. Or an ibuf followed by a bufg; the ibufg is just shorthand for these two. - BrianArticle: 120303
On Mon, 04 Jun 2007 10:30:58 -0700, austin <austin@xilinx.com> wrote: >Simon, > >That is the intent of this number. Of course, some say this number is >inflated (to discourage ASIC conversion), and others say it is "realistic." I think it would be more useful if it was broken down a bit more; at least into memory gate count, other block (PPC,DSP) gate count and good old fashioned CLB fabric gate count. Just an opinion. - BrianArticle: 120304
Hi Guys,
I was trying to access CF by using API sysace_fread and
sysace_fwrite.
I checked xilfatfs library in the software platform settings and
#include <sysace_stdio.h>, but edk still complains.
---------------------------------------------------------------------------=
=AD--------------------------------------------
Running DRCs for OSes, Drivers and Libraries ...
ERROR:MDT - issued from TCL procedure
"::sw_xilfatfs_v1_00_a::xilfatfs_drc" line 15
xilfatfs () - Sysace HW module not present or not accessible from
this
processor. FATfs cannot be used without this module
ERROR:MDT - Error while running DRC for processor ppc405_1...
make: *** [ppc405_0/lib/libxil.a] Error 2
---------------------------------------------------------------------------=
=AD--------------------------------------------
Has anyone experienced this before? Any input would be appreciated!
Thanks in advance,
Yao
Article: 120305Jim, The note in the "changed" history at the end of the datasheet (3E), says only the max has changed. That is consistent with tighter process control. Also consistent with no change to the process center. http://direct.xilinx.com/bvdocs/publications/ds312.pdf page 161 Thanks for this opportunity to explain it. AustinArticle: 120306
Jon, Yes, V4 FX was very unpleasant for Xilinx (specifically, the MGT's). I have posted on this subject before. And, the issues with the MGT's, made many customers unhappy. I look to the future, and try not to dwell on the past, but you are absolutely correct: and I offer my apology as a Xilinx employee, and promise that many things have already changed so that we never make that mistake again (witness the roll-out of V5 LXT). Any abuse that is sent my way concerning the failure to realize the promises on V4 FX MGT is just something I and my colleagues will have to accept. AustinArticle: 120307
Antti, Yes, Steve worked at Triscend. Triscend had reached a point where it was either close the doors, and go out of business and put everyone on the street; or call up folks at Xilinx and ask if their excellent staff of employees could possibly find a home. The doors still closed. Since some were X-Xilinx employees, and we knew what excellent designers, etc. they were, it was a simple matter to ask them to come to 2100 Logic Drive the next day, rather than start looking for jobs. We did the same with DynaChip. The Triscend group has distinguished themselves with valuable additions to V5. The Dynachip group is responsible for the design excellence of Virtex II and continuing. It is not our fault that being a FPGA vendor is incredibly difficult. The history is littered with those who failed. Big names, like Intel, ATT Microelectronics, Motorola have all tried. And, the valley is littered with the stock of little shops that also failed. AustinArticle: 120308
On 5 Jun, 13:59, Yao Sics <yao.s...@gmail.com> wrote: > Hi Guys, > > I was trying to access CF by using API sysace_fread and > sysace_fwrite. > I checked xilfatfs library in the software platform settings and > #include <sysace_stdio.h>, but edk still complains. > > -------------------------------------------------------------------------= --=AD=AD-------------------------------------------- > Running DRCs for OSes, Drivers and Libraries ... > ERROR:MDT - issued from TCL procedure > "::sw_xilfatfs_v1_00_a::xilfatfs_drc" line 15 > xilfatfs () - Sysace HW module not present or not accessible from > this > processor. FATfs cannot be used without this module > > ERROR:MDT - Error while running DRC for processor ppc405_1... > > make: *** [ppc405_0/lib/libxil.a] Error 2 > -------------------------------------------------------------------------= --=AD=AD-------------------------------------------- > > Has anyone experienced this before? Any input would be appreciated! > > Thanks in advance, > > Yao Do you have the system ace module accessible over the bus from your processor? JonArticle: 120309
Hi groups, this is for neewbees and mig user... if you want to save your time, remember to modify ISE options (XST and Implements properties) for your design (the default choices causes PAR fails with something bad in ucf...) : see .bat files in reference design... hopes it helps, raphArticle: 120310
On 5 Jun., 16:33, austin <aus...@xilinx.com> wrote: > Antti, > > Yes, Steve worked at Triscend. > > Triscend had reached a point where it was either close the doors, and go > out of business and put everyone on the street; or call up folks at > Xilinx and ask if their excellent staff of employees could possibly find > a home. > > The doors still closed. > > Since some were X-Xilinx employees, and we knew what excellent > designers, etc. they were, it was a simple matter to ask them to come to > 2100 Logic Drive the next day, rather than start looking for jobs. > > We did the same with DynaChip. > > The Triscend group has distinguished themselves with valuable additions > to V5. > > The Dynachip group is responsible for the design excellence of Virtex II > and continuing. > > It is not our fault that being a FPGA vendor is incredibly difficult. > The history is littered with those who failed. Big names, like Intel, > ATT Microelectronics, Motorola have all tried. > > And, the valley is littered with the stock of little shops that also failed. > > Austin eh ok, maybe. still a bit pitty that ARM is not taking off in FPGAs as Triscend closed doors and Altera discontinued the products. AnttiArticle: 120311
Brian, I got an email from my software 'cousins' in Longmont: the "gate count" number is supplied by the hardware folks. ? "We have met the enemy, and it is us!" (from the old Pogo cartoon) So, we only have ourselves to blame it seems. I will try to find out who supplies the 'gate count' and discuss what it means. AustinArticle: 120312
Hi, My basic version of design has two interconnected microblaze, FSL has been used for interconnection. There is one application on each microblaze such that frist writes to second then the second microblaze sends some data back to the first one. My problem is that while performing Build all user application, it builds the application present in first microblaze but throws errror while building the application in second microblaze. I am using EDK 9.1i, please throw some expert comments on this problem. Regards, Shant ChandrakarArticle: 120313
On 25 May, 09:13, Alan Myler <amy...@eircom.net> wrote: > Niv (KP) wrote: > > On 24 May, 21:16, Alan Myler <amy...@eircom.net> wrote: > > >>Niv (KP) wrote: > > >>>I need to write some timing constraints for an ProAsic device. The > >>>Designer tool doesn't seem to cater for what I need; as follows: > > >>>FPGA1 (Xilinx) outputs data on clk rising edge & FPGA2 (my Actel) > >>>captures data on the clk falling edge (Same clock with very low skew > >>>to both devices) > >>>Similarly Actel outputs data on clk falling edge & Xilinx capture on > >>>rising edge. > >>>I have the Xilinx input & output delays and the clock period is 30 ns. > >>>The clock M/S ratio is 40/60 though, so the total allowed time from > >>>one device clocking out to the other device clocking in is therefore > >>>12 ns (40% of 30ns as worst case). PCB trace is assumed ~1ns. > > >>>So how do I apply the constraints to my Actel chip; I've never used an > >>>SDC file, so some tips or pointers to examples would be useful. > > >>>TIA, Niv > > >>You need the "set_output_delay" constraint I think. Designer "help" menu > >>will tell you how to use it. > > >>Alternatively use the Timing Analyser GUI in Designer to set the > >>constraints. > > >>Alan- Hide quoted text - > > >>- Show quoted text - > > > I find the timing analyser GUI (or "Smartime") confusing. I know > > exactly what I want to say, but I just can't understand how to apply > > my requirements using the Actel GUI. I've even asked the Actel FAE > > and he couldn't tell me how to do it, so what chance do I have! > > > I think a script is a far better method anyway, as it's fully > > repeatable without having to remember what boxes were/were not ticked > > etc. > > > Niv. > > Hi Niv, > > I agree, the GUI is a little confusing, and yes scripts are better. > > However, as a learning exercise it's not wasted time to enter the > requirements via the GUI and see what results you achieve. (Perhaps > double check the results using back-annotated gate-level simulation, > just to be sure that you're getting what you hope you've specified.) > > BTW you can export the GUI contraints to an SDC file from Designer > File->Export->ConstraintFiles > > Best of luck. > > Alan- Hide quoted text - > > - Show quoted text - Played around with this a bit: If I set clock to output delay, which is comprehensible, as 7ns, the saved .sdc file translates this to 23 ns output delay, which is patently wrong for my application as the the time between falling edge (Actel o/p) and rising edge (Xlx i/p) is only 15ns (possibly only 12ns with 60/40 clock). So, do I amend this to say output delay = 5ns where the 5ns := 1ns track delay, plus the 4ns Xilinx input delay (i/ p pad to register i/p max path), and forget about the clock period? TIA, Kev P.Article: 120314
haghdoost, Of interest might be to compare a c language flow, vs a HDL language flow, for a suite of designs. In other words, if you had: a video application, a dsp signal processing application a networking application each codes in both c, and VHDL, with the c being converted to HDL by a tool. How do these compare? Why is (is not) one better than the other? What elements of coding style do not work (well)? You may be able to find existing examples of HDL code for all of the above. All that is needed is the core element of the application, and it actually doesn't have to work (unlike a real product), but it has to be good enough for the compare. Specifications need to exist so you can code the equivalent function in c. This might be more of a Master's project, but it could also be a good senior year project. Discuss it with your advisor. The XUP (Xilinx University Program), has the tools, the boards, and might be able to provide you with what is required. Have your advisor contact the XUP with the requirements. AustinArticle: 120315
Jon, The extremely low jitter directly enables the transmitter of the MGTs to meet the output jitter requirements for all 40+ standards that we have characterization reports for. The Epson oscillator was chosen, and used in these characterization reports. If you want to use another oscillator, use the Epson as a set of requirements to select a comparable unit. AustinArticle: 120316
Hi, I'm looking for thoughts, impressions, pros, cons, etc, on System Generator, Synplify DSP, and Simulink HDL Coder. We develop image processing algorithms and we are trying to shorten the design cycle and eliminate the errors caused by a hand conversion of C or Matlab code to VHDL. It appears that System Generator and Synplify DSP are heavy on comms type functions. How useful are these tools if you need custom functions? Are the tools easy to use? Can System Generator be used with a Synplify Pro synthesis flow? It looks like AccelDSP + System Generator may be a good solution for developing custom algorithms. Any IP not found in System Generator could be done with AccelDSP and exported to System Generator. How well do these tools work/how mature are they? Is anyone using any of these tools for _real_ projects. Thanks for any insights, AndrewArticle: 120317
On Tue, 05 Jun 2007 07:53:31 -0700, Antti <Antti.Lukats@googlemail.com> wrote: >still a bit pitty that ARM is not taking off in FPGAs as Triscend >closed doors and Altera discontinued the products. I think you should blame ARM's greed for that.Article: 120318
hi all,
thanks very much for your responses.
port
myclk2 : in std_logic
it is connected to the system clock in the ucf file.
my current code in vhdl looks like this.
g1: ibufg (myclk2, myclk);
myclknot <= not myclk;
and then myclk also drives process here are the main errors again. any
suggestion is welcome.
thanks again to all u guyz.
1. ERROR:NgdBuild:924 - input pad net 'myclk' is driving non-buffer
primitives:
pin C on block my_user_command_register_1 with type FDE,
pin C on block my_user_command_register_2 with type FDE,
2. ERROR:NgdBuild:455 - logical net 'myclknot' has multiple driver(s):
pin O on block myclknot1_INV_0 with type INV,
pin PAD on block myclknot with type PAD
regards,
Mahalingam
Article: 120319Antti, ARM is nice, but how applicable to the day to day FPGA designer's SOC requirements? With the Virtex line, the IBM PPC is the clear winner, with some 30% of designers using the PPC before VII Pro was introduced, and as much as 50% using the PPC now. IBM's comment to us was "Xilinx has done more for the PPC architecture in one year, than we did in ten." The PPC lends itself to serious DSP programming, as it is quite similar to the processors sold just for DSP. In the Spartan family, the PPC is not the clear winner, with ARM being used primarily in low cost/low power apps. However, licensing ARM cores doesn't fit the Spartan business model, as it would increase the cost to the customer beyond what the benefit might be. And, with the chips getting more CLBs with each generation, we can wait and use soft processors until we see a clear winner emerging. There has even been thoughts of hardening the MicroBlaze(tm) core, but most feel that the last thing the world needs is 'yam' (yet another microprocessor). AustinArticle: 120320
Anyone has a good pointer to a portable (Windows, *nix) TCP/IP socket library that can be used with VHDL FLI, Verilog PLI/VPI, SystemC, or SystemVerilog DPI? -- AmalArticle: 120321
On Jun 5, 5:33 pm, austin <aus...@xilinx.com> wrote: >... >... > There has even been thoughts of hardening the MicroBlaze(tm) core, but > most feel that the last thing the world needs is 'yam' (yet another > microprocessor). > > Austin PPC, ARM, Microblaze.... I hope MIPS could be an option too! There are a lot of device using it and maybe using FPGA as glue for a hard MIPS inside the FPGA could lower such devices price... Sandro P.S. I don't know MIPS Licesing cost...Article: 120322
On Jun 5, 11:10 am, Amal <akhailt...@gmail.com> wrote: > Anyone has a good pointer to a portable (Windows, *nix) TCP/IP socket > library that can be used with VHDL FLI, Verilog PLI/VPI, SystemC, or > SystemVerilog DPI? Have you tried just using the common (BSD-derived I suppose) socket calls and found them not to work on both platforms, or somehow incompatible with the simulation interfaces you mention? I would think that if you just avoid vendor/os -specific extensions you should be fine.Article: 120323
On 5 Jun., 18:16, Sandro <sdro...@netscape.net> wrote: > On Jun 5, 5:33 pm, austin <aus...@xilinx.com> wrote: > > >... > >... > > There has even been thoughts of hardening the MicroBlaze(tm) core, but > > most feel that the last thing the world needs is 'yam' (yet another > > microprocessor). > > > Austin > > PPC, ARM, Microblaze.... I hope MIPS could be an option too! There are > a lot of device using it and maybe using FPGA as glue for a hard MIPS > inside the FPGA could lower such devices price... > > Sandro > P.S. I don't know MIPS Licesing cost... some dont care about licensing: there are * godson * godson-2 * some_similar_name all MIPS derivates http://www.theinquirer.net/default.aspx?article=24882 Antti there are also many MIPS cores for the use in FPGAsArticle: 120324
Sandro, MIPS was one of the three six years ago, PPC, MIPS, and I forget the other one. MIPS lost out to PPC, because our wireless, wired, and networking customers all used PPC. Nothing wrong with MIPS, it was just that we already had a huge market that was already using PPC. Austin
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