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Luc - The last version of ModelSim/Altera that I purchased had a limitation of the number of instantiations you were allowed. If I started manually instantiating IO buffers for wide ram busses, I'd hit the limit and ModelSim would refuse to run. John ProvidenzaArticle: 102876
John Adair wrote: > You really need to get a FAE involved and to check both the Easypath > availability and the charges and NRE for using those parts too. The 100K > volume market is for Xilinx, and all the other vendors for that matter, a > market that they are seriously interested in. My educated guess is that the > SF363 will be the package that is cheapest but there will be other > considerations such as board layout that you should consider on this package > at the same time. I also don't know Easypath status for that package so that > needs to be checked. > > John Adair > Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development > Board. > http://www.enterpoint.co.uk > > > "Anonymous" <someone@microsoft.com> wrote in message > news:Tincg.3668$Qg.540@tornado.southeast.rr.com... >> Is it possible to get Xilinx to just tell me what the cheapest V4FX device >> is possible for 100k units? The device also has to be easy path compatible >> as the eventual product is going to be very price sensitive. >> I agree with John, you need to talk with a Xilinx FAE/Sales Manager and they will be able to address your pricing concerns. BTW, the lowest cost V4FX will be the FX12 that you have selected with some modifiers due to package (small) and speed grade (medium). If you are having problems getting through to someone from Xilinx, drop me an email and I'll get it taking care of. Ed McGettigan -- Xilinx Inc.Article: 102877
Dave, sorry for late reply.
Here is the code:
entity Main is
Port (
btn : in std_logic_vector(3 downto 0);
sel : in std_logic_vector(7 downto 0);
TXD : out std_logic := '1';
RXD : in std_logic := '1';
led : out std_logic_vector(7 downto 0);
CLK : in std_logic;
RST : in std_logic := '0';
ann : out std_logic_vector(3 downto 0);
lcdout : out std_logic_vector(7 downto 0));
end Main;
architecture Behavioral of Main is
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
component UARTcomponent
Port (
TXD : out std_logic := '1';
RXD : in std_logic;
CLK : in std_logic; --Master Clock
DBIN : in std_logic_vector (7 downto 0); --Data Bus in
DBOUT : out std_logic_vector (7 downto 0);--Data Bus out
RDA : inout std_logic; --Read Data Available
TBE : inout std_logic := '1'; --Transfer Bus Ready
RD : in std_logic; --Read Strobe
WR : in std_logic; --Write Strobe
PE : out std_logic; --Parity Error Flag
FE : out std_logic; --Frame Error Flag
OE : out std_logic; --Overwrite Error Flag
RST : in std_logic := '0'); --Master Reset
end component;
component LCDcomponent
Port ( an3 : out std_logic;
an2 : out std_logic;
an1 : out std_logic;
an0 : out std_logic;
lcddisplay : out std_logic_vector(7 downto 0);
datain : in std_logic_vector(7 downto 0));
end component;
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
type mainState is (
idle, receive,
initSendX, sendX, waitSendX,
initSendY, sendY, waitSendY);
-- type sendStates is (
-- sendX,
-- sendY,
-- sendDir,
-- sendAction,
-- sendIdle);
-- signal sendState, sendNextState : sendStates := sendIdle;
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
signal dbInSig : std_logic_vector(7 downto 0);
signal dbOutSig: std_logic_vector(7 downto 0);
signal rdaSig : std_logic;
signal tbrSig : std_logic;
signal rdSig : std_logic;
signal wrSig : std_logic;
signal peSig : std_logic;
signal feSig : std_logic;
signal oeSig : std_logic;
signal state : mainState := idle;
signal stNext : mainState;
signal X : std_logic_vector(7 downto 0) := "00110010";
signal Y : std_logic_vector(7 downto 0) := "00110100";
signal direction: std_logic_vector(2 downto 0) := "110";
signal action : std_logic_vector(1 downto 0) := "11";
signal UARTReady : std_logic := '0';
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal dataReady : std_logic := '0';
shared variable send : std_logic := '0';
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
LCD: LCDcomponent port map (
an3 => ann(3),
an2 => ann(2),
an1 => ann(1),
an0 => ann(0),
lcddisplay => lcdout,
datain => dbOutSig);
UART: Uartcomponent port map (
TXD => TXD,
RXD => RXD,
CLK => CLK,
DBIN => dbInSig,
DBOUT=> dbOutSig,
RDA => rdaSig,
TBE => tbrSig,
RD => rdSig,
WR => wrSig,
PE => peSig,
FE => feSig,
OE => oeSig,
RST => RST);
SET_DATA: process(btn, sel)
begin
if btn(0) = '1' then --reset
reset <= '1';
dataReady <= '1';
else
reset <= '0';
end if;
if btn(2) = '1' then -- set fromX
X <= sel;
dataReady <= '0';
end if;
if btn(1) = '1' then -- set fromY
Y <= sel;
direction <= "000";
dataReady <= '0';
end if;
end process;
RUN: process(CLK, UARTready) -- generate the robotcontroller clock
begin
if dataReady = '1' AND UARTready = '1' then
clock <= CLK;
else
clock <= '0';
end if;
end process;
process (clock, reset)
variable counter : std_logic_vector(15 downto 0):=
"0000000000000000";
begin
if (CLK = '1' and CLK'Event) then
if reset = '1' then
send := '0';
counter := "0000000000000000";
else
if counter = "1100" then
send := '1';
else
send := '0';
end if;
counter := counter + "0000000000000001";
if counter > "1111111111111110" then
counter := "0000000000000000";
end if;
end if;
end if;
end process;
process (CLK, RST)
begin
if (CLK = '1' and CLK'Event) then
if RST = '1' then
state <= idle;
else
state <= stNext;
end if;
end if;
end process;
UART_STATE : process (state, tbrSig, rdaSig, dboutsig, x, y,
direction, action)
variable counter : std_logic_vector(2 downto 0) := "000";
begin
case state is
when idle =>
led(0) <= '0';
led(1) <= '1';
led(2) <= '0';
led(3) <= '1';
led(4) <= dbInSig(0);
led(5) <= dbInSig(1);
led(6) <= dbInSig(2);
led(7) <= dbInSig(3);
rdSig <= '1';
wrSig <= '0';
if send = '1' AND dataReady = '1'then
stNext <= initSendX;
UARTready <= '0';
else
UARTready <= '1';
stNext <= idle;
end if;
when initSendX =>
UARTready <= '0';
led(0) <= '1';
led(1) <= '0';
led(2) <= '1';
led(3) <= '1';
led(4) <= '1';
led(5) <= '1';
led(6) <= '1';
led(7) <= '1';
rdSig <= '1';
dbInSig <= "00110001";
if tbrSig = '0' then
wrSig <= '0';
stNext <= sendX;
else
wrSig <= '1';
stNext <= initSendX;
end if;
when sendX =>
UARTready <= '0';
led(0) <= '1';
led(1) <= '1';
led(2) <= '0';
led(3) <= '1';
led(4) <= '1';
led(5) <= '1';
led(6) <= '1';
led(7) <= '1';
dbInSig <= X; --"00110010";
rdSig <= '1';
if tbrSig = '1' then
stNext <= waitSendX;
counter := "000";
wrSig <= '0';
else
stNext <= sendX;
wrSig <= '0';
end if;
when waitSendX =>
UARTready <= '0';
stNext <= initSendY;
when initSendY =>
UARTready <= '0';
led(0) <= '1';
led(1) <= '1';
led(2) <= '1';
led(3) <= '0';
led(4) <= '1';
led(5) <= '1';
led(6) <= '1';
led(7) <= '1';
rdSig <= '1';
dbInSig <= "00110011";
if tbrSig = '0' then
wrSig <= '0'; --0
stNext <= sendY;
else
wrSig <= '1';
stNext <= initSendY;
end if;
when sendY =>
UARTready <= '0';
led(0) <= '1';
led(1) <= '1';
led(2) <= '1';
led(3) <= '1';
led(4) <= '0';
led(5) <= '1';
led(6) <= '1';
led(7) <= '1';
dbInSig <= Y; --"00110100";
rdSig <= '1';
if tbrSig = '1' then
stNext <= waitSendY;
wrSig <= '0';
else
stNext <= receive;
wrSig <= '1';
end if;
when receive =>
led(0) <= '0';
led(1) <= '1';
led(2) <= '1';
led(3) <= '1';
led(4) <= '1';
led(5) <= '1';
led(6) <= '1';
led(7) <= '1';
rdSig <= '0';
wrSig <= '0';
if rdaSig = '1' then
led(4) <= dbOutSig(0);
led(5) <= dbOutSig(1);
led(6) <= dbOutSig(2);
led(7) <= dbOutSig(3);
UARTready <= '1';
stNext <= idle;
else
stNext <= receive;
end if;
when others =>
UARTready <= '0';
led(0) <= '1';
led(1) <= '0';
led(2) <= '1';
led(3) <= '0';
led(4) <= '1';
led(5) <= '0';
led(6) <= '1';
led(7) <= '0';
end case;
end process;
Article: 102878Telenochek wrote: >>1) Before you assemble, check for supply and ground shorts. >>Too late? >> >> > >Its not too late, I have multiple boards for this. >Without FPGA (TQFP144) chip on board, there aren't any shorts. >I have checked connections with stereo microscope, no solder bridges. > >I think the next thing I will try is to assemble everything, but the >FPGA >and verify that everything without FPGA is fine. >Trouble is that FPGA will be harder to solder with all the stuff on the >board already. > > Have you verified where pin 1 is? I got tripped up a while ago with Xilinx using a center-of-side pin 1 on CPLD packages but a corner pin 1 on FPGAs. Really dumb mistake, but pretty easy to do. JonArticle: 102879
Hi, We want to the purchase the Xilinx PCIe IP core for a high speed serial link for use with the Xilinx ML321 V2pro development board. 1) Is it possible to connect the PCIe core implemented on the ML321 board to a PC. (like some sort of connector plugs into the BERT headers of the board and to the PC or something) 2) Does the implementation of the core and developing the link require expertise with FPGA's and HDL? - EshwarArticle: 102880
Clark - On Mon, 22 May 2006 16:05:52 GMT, "Anonymous" <someone@microsoft.com> wrote: >Can anyone explain why the quotes that we are getting from Xilinx are 4x >their own marketing materials? For example this article > >http://www.ednasia.com/article.asp?articleid=1913 > >says that quantity 50k of an fx12 would be $29.99. We are being quoted about >$112 for 100k units. Most of the other device prices we are getting are also >about 4x what I suspect they must be considering the applications they are >going into. > >Are we talking to the wrong people? Is there a direct xilinx contact to >negotiate large volume deals. > >Thanks, >Clark > This question arises from time to time; here's my take: http://www.sonic.net/~bobperl/blogger/2006/01/things-you-can-ignore-press-release.html Bob Perlman Cambrian Design Works http://www.cambriandesign.comArticle: 102881
I'm having what appears to be an 'output drive strength' problem with some Micron DDR DRAMs (46V32M16). Specifically, it appears that the parts either are not able to drive SSTL-2 Class II nets or the power up behavior of the Micron device does not default to SSTL-2 Class II as it says in the specification. This behavior seems to be present when using 'newer' die revisions of the part. The particular board design uses an Altera Stratix II EP2S60 which in turn uses an Altera Megacore version 3.2.1 DDR Controller. The board design itself is SSTL-2 Class II for the DDR signals and has been working in the lab without problem for approximately 1 year using older die revision parts. I haven't been able to confirm on the actual board yet whether or not the Megacore's DDR Controller design performs a write to the 'Extended Mode Register' to overwrite the power up default value for the output drive strength or not, but in the simulation model it appears to write all 0 which is correct and should leave the drive strength at what is needed for Class II operation. When I probe DQ0 during a read, the signal only moves between 0.96V and 1.54V with 'newer' die rev parts (Rev C and Rev F) but swings between -0.21V and 2.5V with an 'older' die rev part. The board design itself is SSTL-2 Class II and has been working without incident for approximately the past year. Now I'm testing the newer die revision parts and it is failing functionally. Poking around all the inputs doesn't seem to show anything amiss but when I look at the DQ and DQS pins during a read (i.e. when the Micron DDR is driving) I seem to see this same 'small' voltage swing. I'm still trying to validate whether the Altera DDR controller is walking through the initialization sequence properly on the actual board but was wondering if anyone else had seen such stuff before. Any suggestions? KJArticle: 102882
Jim Granville <no.spam@designtools.co.nz> writes: > I see today QuickLogic are ramping their PolarPro devices : > Claim appx $2.95 (in the mythical 'high volume' ) for the 640 register > device. Looks great for low-power applications! But I was surprised to be completely unable to find a list of their distributors on the QuickLogic web site. How do they expect to sell any parts? Any idea of the cost of the development software? It was also unclear to me whether the parts can be programmed in-circuit (though of course only once), or whether they have to be programmed by a standalone programmer before they are soldered down.Article: 102883
When you say "shorted", how many ohms (without power applied) are you seeing between VCC* and GND? Is it a dead short (i.e. a couple of ohms max), or is it in the ~15 ohms or more category? If the latter, it is probably not shorted, and may just be the unpowered resistance of the power system (load and/or regulator). If it is a dead short, and it does not exist without the devices on the board, then there are a few options. Solder bridges or faulty components, or you may have a mistake in the pinout of one of the devices, and have a device ground pin tied to the power plane, or vise-versa. AndyArticle: 102884
John, > Luc - > > The last version of ModelSim/Altera that I purchased had a limitation > of the number of instantiations you were allowed. If I started > manually instantiating IO buffers for wide ram busses, I'd hit the > limit and ModelSim would refuse to run. There is indeed a 255-instance limit, so that is correct. However, as you can see from being able to run gate-level simulations, this limitation is not there when actually instantiating Altera cell primitives. Thus, I'm not entirely sure how you ran into this limit, unless you wrapped the BIDIRs into something slightly higher-level. BTW: Why did you instantiate those IO buffers? So far I've always been able to infer them. Best regards, BenArticle: 102885
"Jon Elson" <jmelson@artsci.wustl.edu> wrote in message news:447212D6.1060008@artsci.wustl.edu... > Have you verified where pin 1 is? I got tripped up a while ago with > Xilinx > using a center-of-side pin 1 on CPLD packages but a corner pin 1 on FPGAs. > Really dumb mistake, but pretty easy to do. > > Jon I second this as a necessary check. The file I looked to for Xilinx CPLD orientation guidance (last time I specified orientation for a tech) had superfluous information. The text was shown along with a circle (or two). There was a specific cirle locating the pin 1 location that wasn't pointed out as *the* unique identifying feature and was not readily visible on the part without the right shadowing.Article: 102886
No, they really are shorted, 1.2ohms. I will try verifying the pins again. Then soldering everything except the FPGA & Flash PROM to see what the state of the pins is. It would be very nice to compare to a really simple board/schematic however. PavelArticle: 102887
Is anybody out there actually using ModelSim Designer? We have a single license as well as 2 PE licenses. Today I couldn't get a PE license so I had to use designer. It was the biggest pain in the ass. First problem was that it couldn't import my PE 6.1d project file (other than being slow and clunky). When I finally got all my files added to the project and tried to compile the top level, it would crash. I had to go to each level in the heirarchy and compile manually (couldn't find any sort of compile all). I tried to load my simulation and it complained about some constants declared in a package. I check the package and its fine. I try to recompile it. Designer doesn't compile it because it thinks its up to date even though I explicitly told it to compile. I fought with the tool for a couple hours and gave up. My problems are probably just issues of not knowing how to use the tool. My project may have been more portable if I was using TCL scripts to compile everything. Oh well. I like to click "Compile Out of Date" in PE. So is anyone using Designer and liking it? I hate it. I told my boss he can have my PE key when he pries it from my cold dead fingers. He seems to think that Mentor is going to be dropping PE and Designer is its replacement. Anyone know anything about that? AndrewArticle: 102888
Nigel wrote: > cannot say. > vendor is not Xilinx. Can you clarify 'vendor' are you : a) buying devices from this company [= distributor] b) buying completed PCBs from this company c) do you really mean customer - they buy boards from you, to sell/install ? -jgArticle: 102889
On 2006-05-22, KJ <Kevin.Jennings@Unisys.com> wrote: > I'm having what appears to be an 'output drive strength' problem > with some Micron DDR DRAMs (46V32M16). Ok, I'm fully admitting that I didn't read your post super-carefully and I'm not looking at the datasheet, but there is a setting in the mode bits for drive strength in those Micron DDR chips. -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 102890
Austin Lesea wrote: > The only choice is "multi." Looks like it's going to be an interesting "multi"-year industry change :)) http://www.electronicproducts.com/ShowPage.asp?SECTION=3700&PRIMID=&FileName=hljh02.jul2006.htmlArticle: 102891
the sendY state should be
when sendY =>
UARTready <= '0';
led(0) <= '1';
led(1) <= '1';
led(2) <= '1';
led(3) <= '1';
led(4) <= '0';
led(5) <= '1';
led(6) <= '1';
led(7) <= '1';
dbInSig <= Y; --"00110100";
rdSig <= '1';
if tbrSig = '1' then
stNext <= receive;
<<<<<<<<<<<<<<
wrSig <= '0';
else
stNext <= sendY;
<<<<<<<<<<<<<<
wrSig <= '1';
end if;
Article: 102892Bob Perlman wrote: > This question arises from time to time; here's my take: > > http://www.sonic.net/~bobperl/blogger/2006/01/things-you-can-ignore-press-release.html > > Bob Perlman > Cambrian Design Works > http://www.cambriandesign.com On the otherhand there are strong truth in advertising laws in many states, including Calif. So if they quote the price and product, one can issue a PO based on those terms and start designing, targeting that delivery date. So it might not be a dream price after all. The DA where I used to live in Calif yanked advertising privs from a company for a year that was doing bait and switch that way after a few complaints. A lot harder to stay in business with only walk in traffic and poor word of mouth reputaion.Article: 102893
Ed McGettigan wrote > lowest cost V4FX will be the FX12 that you have selected with some > modifiers due to package (small) and speed grade (medium). In the far off days of the XC3000, Peter wrote that the uplift was around 10% per speed grade and 10% per package size (if memory serves.) You could start negotiating from these figures, though who knows whether they still apply - we aren't in the 68-pin/84-pin world any more ;-)Article: 102894
Mellby wrote: > I need help to program the SPI-memory connected to a Spartan3E device. The > memory is a M25P40. > > I already have the devices on a circuit board. > > What steps must I take to be able to program the SPI-memory via ISE8.1i? > > A step by step guide would be nice. There is a step-by-step guide for the Spartan-3E Starter Kit board, starting on page 90 in the user guide (UG230). It covers how to generate a programming file and how to use the XAPP445 (XSPI) software. http://www.xilinx.com/bvdocs/userguides/ug230.pdf There are also some programming examples in the Spartan-3E Starter Kit reference designs. http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm In specific, there is a PicoBlaze-based design that uses the RS-232 interface and HyperTerm. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs http://www.xilinx.com/spartan3e --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 102895
b) sort of - we are buying a box from the vendor that has a PCB in it that has the cool runner on it.Article: 102896
good point. we havent measured the continuity in both directions. the short is real (at least in one direction - from Vcc to ground, less than an ohm) the cause is, as yet, TBD.Article: 102897
given a complete lack of eveidence for this "capacity-induced failure", it seems more probable that the failures were due to ESD, contamination, miswiring, etc.Article: 102898
On 22 May 2006 17:25:33 -0700, the renowned "Nigel" <neilchamberlain@hotmail.com> wrote: >good point. we havent measured the continuity in both directions. > >the short is real (at least in one direction - from Vcc to ground, less >than an ohm) > >the cause is, as yet, TBD. How much fault current is the supply capable of? Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.comArticle: 102899
How does one, using the Virtex-4 datasheet, calculate IOB setup and hold time requirements and global clock-to-out time for IO standards other than LVCMOS25 fast 12mA? Thanks in advance, Bob
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