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Antti <Antti.Lukats@xilant.com> wrote: > Jon Beniston schrieb: > > Antti wrote: > > > Antti schrieb: > > > > [] > > Save yourself some trouble. Give it 12 months after the PR before you > > try to use them. > > > > Cheers, > > Jon > Jon, > 12 Month's ? They will be obsolete by then - Cyclone-III is coming out > in late February(or March) and Altera has promised IMMEDIATE > availability > of both silicon and development boards, starting from PR launch date. How many month has Spartan3E been announced. And still now sign of XC3S500E-PQ208 on the webshop and catalogue distributors... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 113026
Hi, I have just finished this free commercial grade tool. I wish it is useful. Topweaver Anydivider (TAD) is a GUI based EDA tool to generate a divided output clock (frequency = Fout) based on an input clock (frequency = Fin), without a DLL/PLL. The waveform of the output clock can be either from automatical calculation or from visual adjustment. Fout=Fin * M / N TAD can analyze the relation of duty cycle and jitter. The generated code are written by verilog. Thanks to the mixed-language feature of most EDA tools, VHDL user can use it directly. For more features, please visit http://www.topweaver.com/doc/tad/tad.htm Download http://www.topweaver.com/download.htmArticle: 113027
hi newsgroup, in the Xilinx application note "XAPP224.pdf" it is said (chapter: Using the Received Data) : "Some example code for this circuitry is given in the design files as mentioned below" Did I miss a thing ? In which vhdl file the description can be found ? Thank you for your help. Rgds Andr=E9Article: 113028
ALuPin@web.de wrote: > in the Xilinx application note "XAPP224.pdf" it is said (chapter: Using > the Received Data) : > > "Some example code for this circuitry is given in the design files as > mentioned below" > > Did I miss a thing ? In which vhdl file the description can be found ? On page 7 there is a link to http://www.xilinx.com/bvdocs/appnotes/xapp224.zip In top_fast.vhd rxcount is incremented by 1 or 2 and rxreg is shifted by 1 or 2 depending on dvalid. Alan Nishioka alan@nishioka.comArticle: 113029
Here's a summary of my problem: I have multiple ngc files, e.g.: top.ngc support1.ngc support2.ngc support3.ngc "top" is the top level ngc and "support1-3" are cores need to actually implement "top" Imagine I have VHDL for "top" but not for the others. I'd like to have a single ngc (or edif or whatever) file that describes the whole component. Is this possible? The resultant file would be needed for physical synthesis, not just simulation, so ngd2edif wouldn't do the job, even if it was still around. Every couple of months I try to figure out a way to do this and end up giving up after wasting a good bit of time. If someone could tell me once and for all if it's possible or not it would save me lots of pain. Thanks, RobinArticle: 113030
hi, We have a FPGA Board, on which there is a RAM. RAM connected with FPGA, nat=FCrlich, :) How can i make sure, the output of the RAM is HIGH Z, when i set de-select the RAM. I 've a logic analyzer anhand, is this useful? Thanks ChengArticle: 113031
Robin, There is an "ngcbuild" tool included with the ISE software. As you might expect, this assembles the top level NGC with any sub levels (NGC or EDIF) and produces a single ngc file. Use the same options as you would for ngdbuild, including any UCF file, data directories, etc. Just type ngcbuild -h on the command line to get further details. Will this meet your needs? thanks, david. Robin Bruce wrote: > Here's a summary of my problem: > > I have multiple ngc files, e.g.: > > top.ngc > support1.ngc > support2.ngc > support3.ngc > > "top" is the top level ngc and "support1-3" are cores need to actually > implement "top" > > Imagine I have VHDL for "top" but not for the others. > > I'd like to have a single ngc (or edif or whatever) file that describes > the whole component. Is this possible? The resultant file would be > needed for physical synthesis, not just simulation, so ngd2edif > wouldn't do the job, even if it was still around. > > Every couple of months I try to figure out a way to do this and end up > giving up after wasting a good bit of time. > > If someone could tell me once and for all if it's possible or not it > would save me lots of pain. > > Thanks, > > Robin >Article: 113032
zhongqiang.ch...@gmail.com wrote: > hi, > > We have a FPGA Board, on which there is a RAM. RAM connected with FPGA, > nat=FCrlich, :) > > How can i make sure, the output of the RAM is HIGH Z, when i set > de-select the RAM. I 've a logic analyzer anhand, is this useful? You could use a logic analyzer if you need a dynamic analysis. You could try adding a resistor between one of the data signals and an address line that is not used to address or select the RAM. Then you can access an address that does not select any device with the address line both high and low. You should see the data line follow the state of the address line. If not, something is driving the bus and you have a problem. I don't see how you can easily tell which device gives you the problem however. The only way to tell if it is the RAM is to isolate the RAM from the bus and see if the problem follows the RAM.Article: 113033
zhongqiang.ch...@gmail.com wrote: > We have a FPGA Board, on which there is a RAM. RAM connected with FPGA, > nat=FCrlich, :) > > How can i make sure, the output of the RAM is HIGH Z, when i set > de-select the RAM. I 've a logic analyzer anhand, is this useful? You can't use a logic analyzer as it will only read a 1 or 0 depending on the threshold. You can use a oscilloscope. Look for midrange values. Or if the bus has pullups or pull downs, look for exponential decays (since a passive pullup will change the signal slower than an active driver). This assumes no bus keeper circuitry (probably not on an fpga). Alan Nishioka alan@nishioka.comArticle: 113034
I'm just wondering if anyone here has seen the same problem I'm
running into. I have a design where I'm playing around a bit with
RLOC. The layout of the design should be something like this:
AAAA BBBB
AAAA BBBB
AAAA BBBB
AAAA BBBB
CCCC DDDD
CCCC DDDD
CCCC DDDD
CCCC DDDD
Where A, B, C, D are instantiations of the same module. It
contains hierarchical instantiations of other RLOCed modules.
However, when I look in the floorplanner, the modules look
something like the following after place & route:
AAAA BBBBB
A AAAA BBBBB
A AA BBBB
AAAA BB
D
CCCC DDD
CCCCC DDDD
CCC C DD DD
CCC DDDD
The funny thing is that everything is still one giant RPM according
to the floorplanner. I don't think that I've made a mistake in the
RLOC placement since I should get the same shape for all of the
module instantiations in that case if I've understood things
correctly.
So I'm wondering if anyone has an idea of what could be wrong. I've
had an issue with ISE 8.2 (SP3) where some RLOCs just disappeared
if I instantiated the same module several times so I've gone back
to ISE 8.1 (SP3).
Are the tools allowed to move individual parts of an RPM? If so,
what can I do to avoid this issue?
One thing which could have an impact is that I'm not defining
any hsets, so every component ends up in the default "hset".
(By looking at the intermediate files using ngc2edif and xdl -ncd2xdl
I'm prepared to blame par for moving my components.) I've tried to
search the answer database on xilinx.com but I haven't found
anything which sheds any light on this problem.
/Andreas
Article: 113035Do you specify your RLOCs in the .ucf? Source? If source, within the submodules? Where the submodules are instatiated? I'm wondering if your concept of sets meshes with the Xilinx concept. If they're all in the same source file for an implied set or in the UCF with the appropriate sets declared explicitly, you should have a good RLOC that shows up as a USER_RPM in FPGA Editor. "Andreas Ehliar" <ehliar@isy.liu.se> wrote in message news:el482c$rfh$1@news.lysator.liu.se... > I'm just wondering if anyone here has seen the same problem I'm > running into. I have a design where I'm playing around a bit with > RLOC. The layout of the design should be something like this: > > > AAAA BBBB > AAAA BBBB > AAAA BBBB > AAAA BBBB > > > CCCC DDDD > CCCC DDDD > CCCC DDDD > CCCC DDDD > > > Where A, B, C, D are instantiations of the same module. It > contains hierarchical instantiations of other RLOCed modules. > > However, when I look in the floorplanner, the modules look > something like the following after place & route: > > > AAAA BBBBB > A AAAA BBBBB > A AA BBBB > AAAA BB > > D > CCCC DDD > CCCCC DDDD > CCC C DD DD > CCC DDDD > > The funny thing is that everything is still one giant RPM according > to the floorplanner. I don't think that I've made a mistake in the > RLOC placement since I should get the same shape for all of the > module instantiations in that case if I've understood things > correctly. > > So I'm wondering if anyone has an idea of what could be wrong. I've > had an issue with ISE 8.2 (SP3) where some RLOCs just disappeared > if I instantiated the same module several times so I've gone back > to ISE 8.1 (SP3). > > Are the tools allowed to move individual parts of an RPM? If so, > what can I do to avoid this issue? > > One thing which could have an impact is that I'm not defining > any hsets, so every component ends up in the default "hset". > > (By looking at the intermediate files using ngc2edif and xdl -ncd2xdl > I'm prepared to blame par for moving my components.) I've tried to > search the answer database on xilinx.com but I haven't found > anything which sheds any light on this problem. > > /AndreasArticle: 113036
Hi Cheng, Get models of the RAM and simulate the thing in ModelSIM or somesuch. HTH, Syms.Article: 113037
HI all, I am a student. I am new to verilog and FPGA. I have a question. How do I use the 16x2 LCD which is on the development board? I have a verilog code which I want the LCD to load the ASCII char from the verilog code I written. The verilog code is just a few shift register acting like a LUT (look up table). Is there any way i can control the 16x2 LCD or is there any macro? I realize that the LCD i/o is connected to the GPIO so is there any way i can use the on board LCD? Thanks in advance. Regards, ShelaArticle: 113038
Andreas Ehliar wrote: > I'm just wondering if anyone here has seen the same problem I'm > running into. I have a design where I'm playing around a bit with > RLOC. The layout of the design should be something like this: > > > AAAA BBBB > AAAA BBBB > AAAA BBBB > AAAA BBBB > > > CCCC DDDD > CCCC DDDD > CCCC DDDD > CCCC DDDD > > > Where A, B, C, D are instantiations of the same module. It > contains hierarchical instantiations of other RLOCed modules. > > However, when I look in the floorplanner, the modules look > something like the following after place & route: > > > AAAA BBBBB > A AAAA BBBBB > A AA BBBB > AAAA BB > > D > CCCC DDD > CCCCC DDDD > CCC C DD DD > CCC DDDD > > The funny thing is that everything is still one giant RPM according > to the floorplanner. I don't think that I've made a mistake in the > RLOC placement since I should get the same shape for all of the > module instantiations in that case if I've understood things > correctly. > > So I'm wondering if anyone has an idea of what could be wrong. I've > had an issue with ISE 8.2 (SP3) where some RLOCs just disappeared > if I instantiated the same module several times so I've gone back > to ISE 8.1 (SP3). > > Are the tools allowed to move individual parts of an RPM? If so, > what can I do to avoid this issue? > > One thing which could have an impact is that I'm not defining > any hsets, so every component ends up in the default "hset". > > (By looking at the intermediate files using ngc2edif and xdl -ncd2xdl > I'm prepared to blame par for moving my components.) I've tried to > search the answer database on xilinx.com but I haven't found > anything which sheds any light on this problem. > > /Andreas The mapper, after parsing the hierarchy remaps the row and column assignments in your RPM so that the lower left corner of the hierarchical RPM is x0y0. If the lower left corner of your RPM, after any trimming by map is in an odd column or odd row, it does exactly what you are experiencing here as a result of re-assigning the RLOCs so that the left bottom element is x0y0. Set up your RLOCs so that the bottom left corner, after any trimming, is x0y0, or at least is even for both x and y so that it doesn't try to put a column that had been for an odd column into an even column. The issue is that even if the placement is legal (i.e. there are no slice M parts going into a slice L as a result of the realignment), the even and even+1 columns are translated as being in one CLB (recalling that each CLB has 2 columns of slices), and then the mapper re-aligns the RLOC columns but does not rebuild the CLB.Article: 113039
zhongqiang.cheng@gmail.com wrote: > hi, > > We have a FPGA Board, on which there is a RAM. RAM connected with FPGA, > nat=FCrlich, :) > > How can i make sure, the output of the RAM is HIGH Z, when i set > de-select the RAM. I 've a logic analyzer anhand, is this useful? > > Thanks > > Cheng Unless you believe you have a bad device, trust the datasheet. Look at the control signals with a scope (a logic analyser can be good but it only shows whether a signal is above or below a set threshold which is _not_ the same as a signal being a valid high or low). If the signals in question (which vary according to type of RAM) show deselect, then you can safely assume it has deselected. On this note, however, you should pay close attention to the datasheet; there is usually (almost always) a delay (thz, tlz etc.) from deselect becoming true and the outputs actually going hi-Z. Cheers PeteSArticle: 113040
"Antti" <Antti.Lukats@xilant.com> schrieb im Newsbeitrag news:1165318595.041905.299450@80g2000cwy.googlegroups.com... > Antti schrieb: > >> as Xilinx PR ES samples are available, and tools support for S3A also, > > as usual - the documentation is not complete :( > > the DNA featured (unique ID) is only mentioned and not described at all > > and, I really really wonder how Xilinx has managed to get > a MicroBlaze to fit into 75% of Spartan-3A !!! UUUUUUUPS my BAD! the 75% LUT useage of Microblaze SoC in S3A-50 is truly correct test design for S3-50 shows (Microblaze 4, LMB RAM, OPB UART) Number of Slice Flip Flops: 335 out of 1,536 21% Number of 4 input LUTs: 842 out of 1,536 54% S3A-50 has 1408 LUTs so it means 59,8 % of LUT's nt 75! sorry for my bad statement, I have had recently trouble fitting MB systems into S3e-100 so I somehow assumed the 75% of s3a-50 just cant be possible. AnttiArticle: 113041
Daveb wrote: > Hi, > > I'm using a microcontroller to configure a Spartan-3 device. The device > seems to configure ok (the design works as expected) but INIT_B goes > low & stays low after the last frame has been clocked in. According to > the datasheet this indicates a CRC error. > > Does anyone have any idea why I'd get a CRC error but my design still > works ? > > Thanks > Dave Hi Dave, Reading the remainder of the thread, it sounds like you've resolved the issue. It is true that INIT_B flags a CRC error during configuration. After configuration, however, it becomes a full-fledged user-I/O pin. If the DONE pin goes High, the FPGA has happily and successfully finished configuration, at which point the INIT_B pin is yours for the keeping. If you do not actively use it in the application, the Xilinx ISE softwrare automatically makes in an input pin with a pull-down resistor (never let CMOS inputs float!). On Spartan-3 FPGA, that pull-down resistor can be quite strong, below 1K-ohms for some I/O standards. I see from the rest of the posting that there is lots of confusion over which pins have pull-ups or pull-downs, when they're active, and which bitstream options control them after configuration. I share your confusion. As a consequence, we recently released a new Spartan-3 Generation Configuration User Guide that covers the new Spartan-3A FPGA family plus the previous Spartan-3E and Spartan-3 FPGA families. The current version is available for download from Xilinx.com at the following location. http://www.xilinx.com/bvdocs/userguides/ug332.pdf Page 38 specifically covers what to do with the INIT_B pin after configuration to avoid this particular issue. The table on page 49 also indicates which pins have dedicated, active, internal pull-up resistors that are always enabled during configuration. As always, we try to make the Spartan-3 FPGA design process as easy as possible and we love to hear how we might improve the documentation or your experience using Xilinx FPGAs. If you have specific improvements, please let us know by clicking the [Feedback] link at the bottom of the user guide, or ... http://www.xilinx.com/xlnx/xweb/xil_feedback.jsp?key=ug332.pdf&contentType=XFILE&transTable=XFILE_TRANS&revName=REV_NUM&title=TITLE&iLanguageID=1&revNum=1.0 Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs http://www.xilinx.com/spartan3e E-mail: steve.knapp@xilinx.com --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 113042
radarman wrote: > Antti wrote: > > radarman schrieb: > > > > > Hello all, > > > I recently bought one of the Parallax Stratix "SmartPack" boards on > > > eBay. It was a good deal, and the FPGA works fine, but I've run into a > > > bit of trouble with the PX loader program. > > > > http://forums.parallax.com/forums/default.aspx?f=15&m=103540 > > > > ?help? > > > > Antti > > That's a good link, but not applicable. I can download designs over the > JTAG port, and they work just fine, which implies that the problem > isn't in the configuration bitstream. Note, I used the supplied sample > .qsf file as a reference, so I see the "ES" part in the device > selection page. > > The problem is that when I use one of the onboard com ports, the PX > loader "hangs" midway through the transfer, requiring me to kill the > process. It seems to always occur at 76 bytes, which is curious. > > I've also tried it with a USB serial adapter, and the transfer does > seem to complete; but the same design that worked just fine when loaded > via JTAG fails when loaded via PX. I've been nervous about supplying > the /P parameter, to program the onboard EEPROM. > > I'm still trying various things, but right now I don't suspect an error > in generating the programming file. It also occurred to me that this > could be why the board was returned in the first place... While it would still be nice to know if the nStatus line can be tied off during configuration, it appears that the problem was with my PC. I tried another PC, and the PX loader works just fine.Article: 113043
Antti wrote: > Antti schrieb: > > > as Xilinx PR ES samples are available, and tools support for S3A also, > > as usual - the documentation is not complete :( [... snip ...] > Antti Hi Antti, There was about a 2-3 hour span last night when the Spartan-3A technical documentation wasn't yet available on the Xilinx web site. The nearly 1,000 pages of documentation all went live about 11 PM Pacific time on 4-DEC-2006. DS529: Spartan-3A FPGA Family Data Sheet [198 pages] ================================================== http://www.xilinx.com/bvdocs/publications/ds529.pdf The data sheet primarily covers the nitty-gritty specifications. All the technical description and "how to" information is now integrated into the following two user guides. The data sheet points you to these guides as well. UG331: Spartan-3 Generation FPGA User Guide [498 pages] ================================================== http://www.xilinx.com/bvdocs/userguides/ug331.pdf This user guide covers practically everything except configuration for the Spartan-3A, Spartan-3E, and Spartan-3 FPGA families. UG332: Spartan-3 Generation Configuration User Guide [266 pages] ================================================== http://www.xilinx.com/bvdocs/userguides/ug331.pdf This user guide covers only configuration topics for the Spartan-3A, Spartan-3E, and Spartan-3 FPGA families. Lastly, there is a separate user guide for the Spartan-3A Starter Kit Board due out in January 2007. It is similar to the Spartan-3E Starter Kit board but adds a few functions that highlight new Spartan-3A features. Spartan-3A Starter Kit http://www.xilinx.com/s3astarter UG330: Spartan-3A Starter Kit Board User Guide [98 pages] ================================================== http://www.xilinx.com/bvdocs/userguides/ug331.pdf > > the DNA featured (unique ID) is only mentioned and not described at all > The Device DNA feature is described in more detail on page 246 of the Configuration User Guide. http://www.xilinx.com/bvdocs/userguides/ug331.pdf You may also be interested in the associated article discussing how to use the Device DNA. How to implement high-security in low-cost FPGAs http://www.pldesignline.com/howto/showArticle.jhtml?articleID=196601422 --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs http://www.xilinx.com/spartan3e E-mail: steve.knapp@xilinx.com --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 113044
"Steve Knapp (Xilinx Spartan-3 Generation FPGAs)" <steve.knapp@xilinx.com> schrieb im Newsbeitrag news:1165346298.454531.194840@16g2000cwy.googlegroups.com... > Antti wrote: >> Antti schrieb: >> >> > as Xilinx PR ES samples are available, and tools support for S3A also, >> >> as usual - the documentation is not complete :( > > [... snip ...] > >> Antti > > Hi Antti, > > There was about a 2-3 hour span last night when the Spartan-3A > technical documentation wasn't yet available on the Xilinx web site. > The nearly 1,000 pages of documentation all went live about 11 PM > Pacific time on 4-DEC-2006. [..] no problems, I actually found all i was looking for, but I had already posted before > You may also be interested in the associated article discussing how to > use the Device DNA. > > How to implement high-security in low-cost FPGAs > http://www.pldesignline.com/howto/showArticle.jhtml?articleID=196601422 > > --------------------------------- > Steven K. Knapp > Applications Manager, Xilinx Inc. > General Products Division > Spartan-3/-3E FPGAs > http://www.xilinx.com/spartan3e > E-mail: steve.knapp@xilinx.com > --------------------------------- > The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs. Steven - you arent working for Altera? I clicked on the link to plddesignline and got a big flashing Altera Stratix-III AD flyer !! ok, well its beyound your control, but was amusing. similarly as it was amysing to come to Xilinx booth at Electronica2006, all it was to see was a big Actel Logo as their booth was just befor Xilinx and way more visible. AnttiArticle: 113045
Hi Steven, There is a TCL command interface for acquiring data from In-system Memory Content Editor off a device. The TCL package is called insystem_memory_edit, which is only available in the TCL shell provided by quartus_stp. (quartus_stp -s). The best way to get help on this topic is to use the online help by evoking quartus_sh --qhelp from the command prompt. In the upper left hand window, scroll down to the Tcl API packkages and click on insystem_memory_edit.When you do this you will see the package commands in the upper right hand window. Click on on the commnds and you wil see details on their description and example usage in the lower panel. Once you get this to work you may add all these commands into a single tcl_script and invoke it with quartus_stp -t <script_file_name> Hope this helps, Subroto Datta Altera Corp. On Dec 5, 2:35 am, Steven Derrien <sderrienREM...@irisa.fr> wrote: > Hi folks, > > Does anyone know wether it is possible to use the quartus "In system > memory editor" feature from command line ? > > I have been searching Altera documentation with little success... > > Thanks in advance, > > StevenArticle: 113046
Antti Lukats wrote: > "Antti" <Antti.Lukats@xilant.com> schrieb im Newsbeitrag > news:1165318595.041905.299450@80g2000cwy.googlegroups.com... > > Antti schrieb: > > [... snip ...] > > and, I really really wonder how Xilinx has managed to get > > a MicroBlaze to fit into 75% of Spartan-3A !!! > > UUUUUUUPS my BAD! > > the 75% LUT useage of Microblaze SoC in S3A-50 is truly correct > > test design for S3-50 shows (Microblaze 4, LMB RAM, OPB UART) > > Number of Slice Flip Flops: 335 out of 1,536 21% > Number of 4 input LUTs: 842 out of 1,536 54% > > S3A-50 has 1408 LUTs so it means 59,8 % of LUT's nt 75! > > sorry for my bad statement, I have had recently trouble fitting > MB systems into S3e-100 so I somehow assumed the 75% of > s3a-50 just cant be possible. > > Antti While I haven't tried this myself, I expect that the difference is the enhanced 18K block RAMs on Spartan-3A FPGAs. Essentially, all Spartan-3, Spartan-3E, and Spartan-3A FPGAs have the same 18 Kbit block RAM. However, Spartan-3A FPGAs add byte-level write enables for the 1Kx18 and the 512x36 organizations. See pages 153-154 in the Spartan-3 Generation User Guide. http://www.xilinx.com/bvdocs/userguides/ug331.pdf The MicroBlaze controller uses byte-level write operations. These are emulated in Spartan-3 and Spartan-3E FPGAs with additional logic. On Spartan-3 FPGAs, the entire design is simplified and more optimal. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs http://www.xilinx.com/spartan3e E-mail: steve.knapp@xilinx.com --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 113047
"Steve Knapp (Xilinx Spartan-3 Generation FPGAs)" <steve.knapp@xilinx.com> schrieb im Newsbeitrag news:1165347583.878327.14740@80g2000cwy.googlegroups.com... > Antti Lukats wrote: >> "Antti" <Antti.Lukats@xilant.com> schrieb im Newsbeitrag >> news:1165318595.041905.299450@80g2000cwy.googlegroups.com... >> > Antti schrieb: >> > > [... snip ...] >> > and, I really really wonder how Xilinx has managed to get >> > a MicroBlaze to fit into 75% of Spartan-3A !!! >> >> UUUUUUUPS my BAD! >> >> the 75% LUT useage of Microblaze SoC in S3A-50 is truly correct >> >> test design for S3-50 shows (Microblaze 4, LMB RAM, OPB UART) >> >> Number of Slice Flip Flops: 335 out of 1,536 21% >> Number of 4 input LUTs: 842 out of 1,536 54% >> >> S3A-50 has 1408 LUTs so it means 59,8 % of LUT's nt 75! >> >> sorry for my bad statement, I have had recently trouble fitting >> MB systems into S3e-100 so I somehow assumed the 75% of >> s3a-50 just cant be possible. >> >> Antti > > While I haven't tried this myself, I expect that the difference is the > enhanced 18K block RAMs on Spartan-3A FPGAs. > > Essentially, all Spartan-3, Spartan-3E, and Spartan-3A FPGAs have the > same 18 Kbit block RAM. However, Spartan-3A FPGAs add byte-level write > enables for the 1Kx18 and the 512x36 organizations. See pages 153-154 > in the Spartan-3 Generation User Guide. > http://www.xilinx.com/bvdocs/userguides/ug331.pdf > > The MicroBlaze controller uses byte-level write operations. These are > emulated in Spartan-3 and Spartan-3E FPGAs with additional logic. On > Spartan-3 FPGAs, the entire design is simplified and more optimal. > > --------------------------------- > Steven K. Knapp > Applications Manager, Xilinx Inc. > General Products Division > Spartan-3/-3E FPGAs > http://www.xilinx.com/spartan3e > E-mail: steve.knapp@xilinx.com > --------------------------------- > The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs. > Hi Steve, you are nottop at MicroBlaze tech details - the byte enables on BRAMs are NEVER emulated by the current EDK tools, thats why the minimum BRAM size for S-3 s 8K, all BRAM blocks are required to have minimum 4 BRAMs so each bytelane has its own BRAM and no emulation is necessary surprisingle the open-source OpenFire MicroBlaze clone DOES support byte writes to single BRAM, because of that OpenFire is useable with S3A with current EDK tool versions that do not support yet S3A byte write feature - this prevents EDK 8.2 to be used to target S3A-50 because it has only 3 BRAMs not to mention that DATA2MEM doesnt support S3A at all, here again the OpenFire includes methods to retrive the BRAM locate info from .LL files post implementation so using that method and custom bitfile patch program a MicroBlaze design in S3A would be possible even today - even before Xilinx releases full support for S3A in their tools. AnttiArticle: 113048
[... snip ...] > > Steven - you arent working for Altera? > > I clicked on the link to plddesignline and got a big flashing Altera > Stratix-III AD flyer !! > ok, well its beyound your control, but was amusing. > similarly as it was amysing to come to Xilinx booth at Electronica2006, all > it was to > see was a big Actel Logo as their booth was just befor Xilinx and way more > visible. > > Antti I saw that too, but unfortunately I don't get to decide who advertizes on the EE Times web sites. Hey, if you can afford a Stratix-III FPGA, I'd really like to introduce you to the following superior FPGA product line. :-) http://www.xilinx.com/virtex5 --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E/-3A FPGAs http://www.xilinx.com/spartan3e http://www.xilinx.com/spartan3a E-mail: steve.knapp@xilinx.com --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 113049
"Steve Knapp (Xilinx Spartan-3 Generation FPGAs)" <steve.knapp@xilinx.com> schrieb im Newsbeitrag news:1165348083.641699.51670@80g2000cwy.googlegroups.com... > [... snip ...] >> >> Steven - you arent working for Altera? >> >> I clicked on the link to plddesignline and got a big flashing Altera >> Stratix-III AD flyer !! >> ok, well its beyound your control, but was amusing. >> similarly as it was amysing to come to Xilinx booth at Electronica2006, >> all >> it was to >> see was a big Actel Logo as their booth was just befor Xilinx and way >> more >> visible. >> >> Antti > > I saw that too, but unfortunately I don't get to decide who advertizes > on the EE Times web sites. > > Hey, if you can afford a Stratix-III FPGA, I'd really like to introduce > you to the following superior FPGA product line. :-) > http://www.xilinx.com/virtex5 > > --------------------------------- > Steven K. Knapp > Applications Manager, Xilinx Inc. > General Products Division > Spartan-3/-3E/-3A FPGAs > http://www.xilinx.com/spartan3e > http://www.xilinx.com/spartan3a > E-mail: steve.knapp@xilinx.com > --------------------------------- > The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs. > HAHA - ROTFL I have been playing with Virtex-5 on my desk for some time now. V-5 is pretty cool, as finger-excercise I designed a UART and baud rate divider for Virtex-5 that uses as much as LUTs --- 0 (zero) FF's --- 0 (zero) :) Really - not cheating, it utilizes DSP48E --- 1 (one) but not FFs or LUTs from FPGA fabric -------- S-III will come before christmas (2007), ok some months before ;) Antti
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