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"Quesito" <francesco_poderico@yahoo.com> wrote: >Hi all, >for the picoblaze funs... >you can download the latest version of picoblaze C compiler on my >website >www.poderico.co.uk >the latest version is 1.8.4 >In this version you have the optimizer (just started) >I've got an example how to use the LCD IF on the Spartan3E starter >kit... if you want to have a try.. please send me an email for any >suggestions... or improvement... The examples seem a bit like a macro based C compiler. The code for reading/writing I/O is huge. Maybe it is better to introduce some language extensions that will map variables into the I/O space. Most 8051 C compilers do this. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 113001
Hello all, I recently bought one of the Parallax Stratix "SmartPack" boards on eBay. It was a good deal, and the FPGA works fine, but I've run into a bit of trouble with the PX loader program. I'm not clear whether it is a problem with the loader itself, the serial port. I don't suspect the PIC microcontroller, as the initial default configuration loads. The trouble is, I don't understand the failure, or the protocol. I know from the docs that the binary data is RLE compressed, but I don't understand the handshaking stuff. I'm working on finding a workable configuration, but so far it hasn't gone too well. In the event that I can't get the PX stuff working, I thought about just depopulating the PIC, and dead-bugging an appropriate configuration memory to the board. The problem is that the nStatus line may not be available. I do have access to nCONFIG, DEV_CLRn, CONF_DONE, DCLK, and DATA0. I'm curious to know what would happen if one wired in, say, an EPCx device, and left the nCS line tied active. In theory, if you don't reuse the bit in the design, shouldn't it be harmless? Will this confuse the EPCx? Thanks!Article: 113002
cippalippa wrote: > thanks for the answer. > However I already see the Xilinx reference design but I have a bad > experience with this kind of design. > I don't need particular performace; 100 MHz speed and burst 2 for me is > enaught. > I see that opencores IP seems simple and Xilinx IP with MIG seems > complicate; I ask to Xilinx Field Application engineer if this IP > generated from Xilinx MIG works and they ask me: "I don't know"; so if > I'm not sure that this controller work I prefer to use Opencore IP. > Sameone have already use the Opencore DDR sdram controller? If so how I > must modify the design for the sintesis? Maybe I misunderstood, but it already does synthesize. David Ashley, as posted here earlier, did the needed modification to get it running on the Spartan 3E Start Kit. With just a .ucf adjustment, it worked on Digilent's Spartan 3E1600 board. That said, the Opencore DDR controller is not perfect, but it's a good starting point for verifying that the basic .ucf constaints are set up (mostly) correctly. TommyArticle: 113003
radarman schrieb: > Hello all, > I recently bought one of the Parallax Stratix "SmartPack" boards on > eBay. It was a good deal, and the FPGA works fine, but I've run into a > bit of trouble with the PX loader program. http://forums.parallax.com/forums/default.aspx?f=15&m=103540 ?help? AnttiArticle: 113004
Hi everyone, When I launch an external application such as XMD, the Software Debugger or Platform Studio SDK from the Xilinx Platform Studio 8.2 my Window XP desktop will freeze for an indefinite amount of time. The mouse can be moved, but all mouse clicks and keyboard input seems to be dead. The only way for me to recover control of my PC is to hit Ctrl-Alt-Delete which seems to wake the PC up from whatever state it's in and I can then continue to use the application that was launched. When I first installed EDK 8.2 a few months ago it worked fine, but this problem seemed to come from out of the blue a few weeks ago. Applying the latest EDK updates to bring things up 8.2.02i did not seem to fix anything. Also, no other applications on my PC suffer from the same problems so I'm fairly certain it's a problem with the Xilinx applications themselves. Has anyone seen such an issue? Any clues on where I can look to see what might be misconfigured on my system? Thanks, Mike ThompsonArticle: 113005
Antti wrote: > radarman schrieb: > > > Hello all, > > I recently bought one of the Parallax Stratix "SmartPack" boards on > > eBay. It was a good deal, and the FPGA works fine, but I've run into a > > bit of trouble with the PX loader program. > > http://forums.parallax.com/forums/default.aspx?f=15&m=103540 > > ?help? > > Antti That's a good link, but not applicable. I can download designs over the JTAG port, and they work just fine, which implies that the problem isn't in the configuration bitstream. Note, I used the supplied sample .qsf file as a reference, so I see the "ES" part in the device selection page. The problem is that when I use one of the onboard com ports, the PX loader "hangs" midway through the transfer, requiring me to kill the process. It seems to always occur at 76 bytes, which is curious. I've also tried it with a USB serial adapter, and the transfer does seem to complete; but the same design that worked just fine when loaded via JTAG fails when loaded via PX. I've been nervous about supplying the /P parameter, to program the onboard EEPROM. I'm still trying various things, but right now I don't suspect an error in generating the programming file. It also occurred to me that this could be why the board was returned in the first place...Article: 113006
thank u folks.... John, which version of xilinx wer u working on? I am currently working on 8.1 and was trying to use the lock pins constraint, INST "lut_name" LOCK_PINS = "I0:A1, I1:A2, I2:A3, I3:A4"; it pops up with a syntax error in da UCF file. I dont know wer I am goin wrong. could u suggest me smthin on this.... thank u Mr.BArticle: 113007
Mr B., could you please tell us why the LUT-address bit-order is important for you. Everybody knows that it is irrelevant in most cases. Yours must be special... Peter Alfke, Xilinx Mr.B wrote: > thank u folks.... > > John, which version of xilinx wer u working on? I am currently working on 8.1 and was trying to use the lock pins constraint, INST "lut_name" LOCK_PINS = "I0:A1, I1:A2, I2:A3, I3:A4"; it pops up with a syntax error in da UCF file. I dont know wer I am goin wrong. could u suggest me smthin on this.... > > thank u > > Mr.BArticle: 113008
Hi Pete I am tryin to permute the input order for that I need to fix the inputs in a certain fashion. Mr.B Peter Alfke wrote: > Mr B., could you please tell us why the LUT-address bit-order is > important for you. > Everybody knows that it is irrelevant in most cases. Yours must be > special... > Peter Alfke, Xilinx > > Mr.B wrote: > > thank u folks.... > > > > John, which version of xilinx wer u working on? I am currently working on 8.1 and was trying to use the lock pins constraint, INST "lut_name" LOCK_PINS = "I0:A1, I1:A2, I2:A3, I3:A4"; it pops up with a syntax error in da UCF file. I dont know wer I am goin wrong. could u suggest me smthin on this.... > > > > thank u > > > > Mr.BArticle: 113009
Tommy Thorn wrote: > Maybe I misunderstood, but it already does synthesize. David Ashley, as > posted here earlier, did the needed modification to get it running on > the Spartan 3E Start Kit. With just a .ucf adjustment, it worked on > Digilent's Spartan 3E1600 board. Do you have a link to a working project or the ucf file? I would like to use the DDR SDRAM, too, but I can't find the posting. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 113010
I suppose you know already that you can achieve the same result by changing the content of the LUT, either by reconfiguration or even dynamically by shifting in the new pattern serially.(SRL16) Peter Alfke, Xilinx On Dec 4, 4:31 pm, bharadwaj...@gmail.com wrote: > Hi Pete > > I am tryin to permute the input order for that I need to fix the inputs > in a certain fashion. > > Mr.B > > Peter Alfke wrote: > > Mr B., could you please tell us why the LUT-address bit-order is > > important for you. > > Everybody knows that it is irrelevant in most cases. Yours must be > > special... > > Peter Alfke, Xilinx > > > Mr.B wrote: > > > thank u folks.... > > > > John, which version of xilinx wer u working on? I am currently working on 8.1 and was trying to use the lock pins constraint, INST "lut_name" LOCK_PINS = "I0:A1, I1:A2, I2:A3, I3:A4"; it pops up with a syntax error in da UCF file. I dont know wer I am goin wrong. could u suggest me smthin on this.... > > > > thank u > > > > Mr.BArticle: 113011
john wrote: > Hi, > > A part of my project needs the FPGA spartan3 ( XC3S100) to be > interfaced with the USB via FIFO. I made the FIFO using logic core's > FIFO generator v 2.3. I am intending to make a asynchronous FIFO. The > FIFO has full, almost full, read , write signals. Would XEM3010 be the > right choice for it? Please advice! What is XEM3010? Why do you need a FIFO, and why does it need to be asynchronous?Article: 113012
Frank Buss wrote: > Tommy Thorn wrote: > > > Maybe I misunderstood, but it already does synthesize. David Ashley, as > > posted here earlier, did the needed modification to get it running on > > the Spartan 3E Start Kit. With just a .ucf adjustment, it worked on > > Digilent's Spartan 3E1600 board. > > Do you have a link to a working project or the ucf file? I would like to > use the DDR SDRAM, too, but I can't find the posting. Sorry, it was a bit tricky to find. The original thread: http://groups.google.com/group/comp.arch.fpga/tree/browse_frm/thread/a58600c317356edb/27f9d22a4590952b?rnum=11&q=david+ashley+ddr&_done=%2Fgroup%2Fcomp.arch.fpga%2Fbrowse_frm%2Fthread%2Fa58600c317356edb%2F979d5e1695dc1710%3Flnk%3Dst%26q%3Ddavid+ashley+ddr%26rnum%3D2%26#doc_27f9d22a4590952b For your convienience, the source (quoting David: "It's a pretty much identical copy of the open cores ddr controller, except I removed one DCM, and I wrapped it all in a synthesizable tester targeted to the spartan-3e starter board."): http://www.xdr.com/dash/fpga/ My humble contribution: a complete constraints file for the Digilent Spartan 3E-1600 Development Board (aka. Spartan 3E starter kit in the XC3S1600E edition): http://not.meko.dk/spe1600e-1.1.ucf Please share any improvements or suggestions. TommyArticle: 113013
Hi, I have a design with a Spartan3E driving some PCI logic. I'm trying to simulate part of the design using HyperLynx 7.5 and the Spartan3e IBIS model from Xilinx. 1. When I set the I/O standard for the pin(s) in question, the steady-state output high voltage is 3V, not 3.3V . I know Xilinx only claims PCI 3.3V compatability if the I/Os are run at 3V -- is this output voltage hard coded in the IBIS model? I think all the power supplies in HyperLynx are correctly set, including the 3.3V supply. 2. In HyperLynx, when I change the I/O standard for the pin (i.e. LVCMOS, SSTL, etc) the "pin number" for the selected pin seems to change. Is this "pin number" just refering to an I/O standard the IBIS file supports? 3. Xilinx XAP653 has some guidelines for PCI and clamp diode / resistor calculations. Page 2 seems to be a bit circular when it comes to computing the resistance to limit the current, and more specifically the foward voltage for the didoe . Where does the knowledge of using 1V for the diode's Vf come from? It seems the assumption is made that Vf is 1V, current is calculated, and then the Vf is re-referenced based on the foward current and it is "confirmed" Vf is 1V... Your help is welcome. /\/\/\/\/\/\/\/\/\/\/\/\/\_____ Into the EE Ether we go!Article: 113014
Hi I have to simulate a gate level netlist file with test bench and dummy host model in modelsim SE in quartus s/w.Can you give hint. sorry for the disturbance kumar Subroto Datta wrote: > The details can be found in the Quartus Handbook at > http://www.altera.com/literature/hb/qts/qts_qii53001.pdf > > Hope this helps, > Subroto Datta > Altera Corp. > > "ram" <vsrpkumar@rediffmail.com> wrote in message > news:1165028275.314021.115460@j44g2000cwa.googlegroups.com... > > Hi > > I am using modelsim for simulation and quartus 6.0 for remaining.I have > > generated custom netlist ffrom quartus.I want to simulate in modelsim > > .How to link library of cyclone device.How to do that.Can anybody help > > me.Thanking you > >Article: 113015
Good Idea, OK I will do! Nico Coesel wrote: > "Quesito" <francesco_poderico@yahoo.com> wrote: > > >Hi all, > >for the picoblaze funs... > >you can download the latest version of picoblaze C compiler on my > >website > >www.poderico.co.uk > >the latest version is 1.8.4 > >In this version you have the optimizer (just started) > >I've got an example how to use the LCD IF on the Spartan3E starter > >kit... if you want to have a try.. please send me an email for any > >suggestions... or improvement... > > The examples seem a bit like a macro based C compiler. The code for > reading/writing I/O is huge. Maybe it is better to introduce some > language extensions that will map variables into the I/O space. Most > 8051 C compilers do this. > > > -- > Reply to nico@nctdevpuntnl (punt=.) > Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 113016
When I make the readback on the Spartan II concerning a configuration's bitstream which changes the state of some flip flop, the returned bitstream is not the current one but starting bitstream whitout changes.Article: 113017
Hi folks, Does anyone know wether it is possible to use the quartus "In system memory editor" feature from command line ? I have been searching Altera documentation with little success... Thanks in advance, StevenArticle: 113018
OpalKelly XEMs are a very simple interface to USB2.0. The FrontPanel software and cores include pipeline transfer triggered by PC for connection to spartan3 FIFOs. If you don't need aditional SDRAM or nonvolatile PROM to store FPGA program, then XEM3001 is enough. Cheers, Ales john wrote: > Hi, > > A part of my project needs the FPGA spartan3 ( XC3S100) to be > interfaced with the USB via FIFO. I made the FIFO using logic core's > FIFO generator v 2.3. I am intending to make a asynchronous FIFO. The > FIFO has full, almost full, read , write signals. Would XEM3010 be the > right choice for it? Please advice! > > Regards > JohnArticle: 113019
as Xilinx PR ES samples are available, and tools support for S3A also, well this is not so true because data2mem does not support S3A, those Microblaze designs with EDK flow will fail on NGBUILD, the same applies to Virtex-5 all devices except 50(T) - so as of today the latest ISE/EDK supports Virtex-5 ---> LX50(T) only ! DATA2MEM fails for all other devices Spartan3A ---> no devices, DATA2MEM is not supporting S3a of course designs that dont use softcore processors can be implemented with current tools as well, also for S3A and V5 other than LX50(T). I wonder why there is no date on ISE 8.2 SP4 release? WebCase allows SP4 to be selected already. AnttiArticle: 113020
Antti schrieb: > as Xilinx PR ES samples are available, and tools support for S3A also, as usual - the documentation is not complete :( the DNA featured (unique ID) is only mentioned and not described at all and, I really really wonder how Xilinx has managed to get a MicroBlaze to fit into 75% of Spartan-3A !!! IMHO none of Xilinx MicroBlaze released versions would fit into 75% of S3-50A never! maybe MicroBlaze 6 has special options to be 'ultra lite' like NIOS has, then it might be possible, but otherwise I have hard times believing MicroBlaze fits into 50A AnttiArticle: 113021
Antti <Antti.Lukats@xilant.com> wrote: > Antti schrieb: > > as Xilinx PR ES samples are available, and tools support for S3A also, > as usual - the documentation is not complete :( > the DNA featured (unique ID) is only mentioned and not described at all > and, I really really wonder how Xilinx has managed to get > a MicroBlaze to fit into 75% of Spartan-3A !!! > IMHO none of Xilinx MicroBlaze released versions would fit into 75% of > S3-50A never! > maybe MicroBlaze 6 has special options to be 'ultra lite' like NIOS > has, then it might be possible, but otherwise I have hard times > believing MicroBlaze fits into 50A It's a pity that the datasheet doesn't mention the xc3s1400a_pq208 that the ISE 8.2 BSDL file made us hope for. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 113022
Antti schrieb: > Antti schrieb: > > > as Xilinx PR ES samples are available, and tools support for S3A also, > > as usual - the documentation is not complete :( > > the DNA featured (unique ID) is only mentioned and not described at all uups (I should RTFM) it is described fully Antti PS the biggest news is possible extended VCCAUX range! now S3a can be used similar to Altera FPGAs with only 2 voltages eg separate VCCAUX is no longer required!Article: 113023
Antti wrote: > Antti schrieb: > > > as Xilinx PR ES samples are available, and tools support for S3A also, > > as usual - the documentation is not complete :( > > the DNA featured (unique ID) is only mentioned and not described at all > > and, I really really wonder how Xilinx has managed to get > a MicroBlaze to fit into 75% of Spartan-3A !!! > > IMHO none of Xilinx MicroBlaze released versions would fit into 75% of > S3-50A never! > > maybe MicroBlaze 6 has special options to be 'ultra lite' like NIOS > has, then it might be possible, but otherwise I have hard times > believing MicroBlaze fits into 50A Save yourself some trouble. Give it 12 months after the PR before you try to use them. Cheers, JonArticle: 113024
Jon Beniston schrieb: > Antti wrote: > > Antti schrieb: > > [] > Save yourself some trouble. Give it 12 months after the PR before you > try to use them. > > Cheers, > Jon Jon, 12 Month's ? They will be obsolete by then - Cyclone-III is coming out in late February(or March) and Altera has promised IMMEDIATE availability of both silicon and development boards, starting from PR launch date. Antti
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