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On Feb 2, 9:53 am, "bharat_in" <ecbha...@gmail.com> wrote: > Hi, > Does anyone know how to implemtent circle generation algorithm in > verilog? > i want to implement it in spartan 3 kit,for VGA pattern generator. > i don't want to use ROM and RAM. > please, reply as soon as possible There was a thread in this newsgroup titled Video Circle Generator Try Google groups...Article: 115201
These links should keep you busy for a while: http://direct.xilinx.com/bvdocs/userguides/ug012.pdf (chapter 4) http://www.xilinx.com/bvdocs/appnotes/xapp138.pdf http://www.xilinx.com/bvdocs/appnotes/xapp139.pdf -David "nana" <nmichou@utk.edu> wrote in message news:1170388556.873878.192840@v33g2000cwv.googlegroups.com... > Can anybody tell me how to read the contents of the FPGA? > I am working on xupv2p development board and after I download data to > the fpga I want to read back its contents. > Thank you >Article: 115202
If the receiver can not determine which FC information to update then it must not update the FC information. Otherwise updating of the FC information is optional when a receiver receives a malformed TLP. So depending on what the receiving device does, or how malformed the packet is, your scenario could certainly play out. But the receiving device will send an ERR_FATAL message to the root complex Colin "Fred" <fred@n0spam.com> wrote in message news:1170332691.17553.0@iris.uk.clara.net... >I know there is a PCI-Express newsgroup but there are very few posts of any >relevance to PCI Express itself. > > Is there another newsgroup more dedicated to the workings of PCI Express? > > I have the following question: What happens when a mal formed packet is > received? The transmitter CC will be incremented but the CL (which is the > CA received from the receiver) will not be incremented such that the > apparent size of the available space in the receive buffer will decrease > with no mechanism to correct itself. Am I correct? > > >Article: 115203
I drove a plotter head with Bresenham's line and circle algorithms. They require very simple math and could be easily implemented with FPGAs either. "bharat_in" <ecbharat@gmail.com> wrote in message news:1170428025.546689.44520@h3g2000cwc.googlegroups.com... > Hi, > Does anyone know how to implemtent circle generation algorithm in > verilog? > i want to implement it in spartan 3 kit,for VGA pattern generator. > i don't want to use ROM and RAM. > please, reply as soon as possible >Article: 115204
Hi all, ISE9.1i is faster than ISE8.2i and I noticed improvement for gate count (improvement of XST). Smart Guide is interesting but partition still have bug (like ISE8.2 with the "horrible" port.main.h crash !). Anyway, no hesitation, forget 8.2 and use 9.1i.Article: 115205
Seems to work on quartus 6.1 http://home.comcast.net/~mike_treseler/transmitter.pdfArticle: 115206
I've just started using ISE 9.1 sp1 and have mixed results. I don't have a lot of hours on it yet, but so far it seems to be a bit better than 8.1, but it still has serious bugs. a) the 'compile' time seems to be a bit faster, my V4 design used to take about 3 hours, now its down to 2++ hours. b) SmartGuide appears to be broken for my design. I get various system crashes or unable to route messages. If I do a pass without SmartGuide, it took about 2++ hours to Synthesize, Build, Map, Par, and Generate programming file. With SmartGuide, it died after over *** 5 Hours *** c) Impact appears to have bugs in changing th target directory for ACE files. d) I'm still seeing various complaints from the s/w about bad database or internal errors. Xilinx still needs to do SERIOUS bug fixing. John ProvidenzaArticle: 115207
On Feb 2, 5:42 am, Andreas Ehliar <ehl...@isy.liu.se> wrote: > timer <= timer+1; > > if ((stage=waiting)) then > timer<="0000"; > stage<=start; (unrelated portion removed) > end if; > > if reset='1' then > timer<="0000"; > stage<=waiting; > end if; It doesn't seem to solve the problem, and there may be some obscure language "rule" for disambiguation, but I don't like seeing what appear to be three different attempts to assigned a value to the timer register. Wouldn't it be better practice to "else" them? If (reset)... elsif(waiting)... elseArticle: 115208
By the way - the new "Project | Source Control" menu item looks compelling. I was able to generate a .tcl script which may be able to fully recreate the .ise file. I haven't tried to completely recreate a project from scratch, but the idea is compelling. I did export just the .tcl files without the extra suggested files and was able to import from that _impot.tcl script into a different directory to include all the paths I specified originally. I like it. 9.1.01i has at least one more bell or whistle! "John_H" <newsgroup@johnhandwork.com> wrote in message news:12s6olo782c4084@corp.supernews.com... > I've had no problems so far, 9.1.01i. > > My design isn't huge - less than half an XC3S1600E - so my compile times > aren't what are focused on with the speed improvements. Things did appear > a little faster but that may also be because of my tuning the timing > numbers recently to make things cleaner in my design. > > One thing I did notice that looked different (maybe is was, maybe it > wasn't) is when the timing was met (Timing Score 0) another quick step was > also executed (Timing Score 0) perhaps as a visit to a "cleanup pass" that > used to be a good part of the Place & Route. It's only an extra 15 > seconds in my 8 minutes or so of Place & Route time. If it's a cleanup, > it's much appreciated. > > I don't use XST so I don't have any indication there. My flow comes in > from SynplifyPro Edif and goes out with a promgen-generated .bin file. I > had more of a hiccup (small as it was) with SynplifyPro 8.8 than with ISE > 9.1.01i. > > - John_H > > > "Francesco" <francesco_poderico@yahoo.com> wrote in message > news:1170427827.806443.94060@q2g2000cwa.googlegroups.com... >> Hi, I'm just wondering how many people here are using ISE 9.1. >> Could you post your experience here? >> Antii what do you think? >> Is really 6 time faster? >> >> I tryed unsuccesfully to use ISE 9.1 SP1...unfortunately in my case >> the tool crashed with the message error: "Runtime error" >> I tryed a few time unsuccesfully.... Now I'm back on ISE 8.2 >> >> >> Thanks eveybody, >> Francesco >> >> PS: please post here even if you are using Webpack 9.1 >> > >Article: 115209
On Feb 2, 5:42 am, Andreas Ehliar <ehl...@isy.liu.se> wrote: > I was a TA for an introductory VHDL lab yesterday and > I encountered a very weird problem. In the source code > included below I get the following interesting messages > from XST when I try to synthesize the file: seems okay in Synplicity and PrecisionRTL under ispLEVER - -Article: 115210
On Feb 2, 3:36 am, "Niv (KP)" <kev.pars...@mbda.co.uk> wrote: > I'm about to use an APA1000 with Actels implementation of dual port > RAMs. These require the use of the PLL to create a X2 clock. > > My input clock is 33MHz, but this goes to another FPGA as well, and > the skew between the two chips must be kept to a minimum. So, will > the PLL output of 66MHz have its rising edges coincident with the > edges of the 33MHz clock? > > Anyone had experience of using these PLLs, good or bad. > > Regards, Niv. never tried one - but the datasheet shows reasonable ability to control skew by controlling timing in the feedback path - and there are several appnotes pointed to in the body of the datasheetArticle: 115211
Hey All... Is there a way to decode the interconnect/Routing algorithm used by Xilinx???? I see that the XDL file gives information on the routing details. However, the interconnect/Routing details are given as numbers. Also, It gives info on PIPs, but I really dunno how to decode it. Could somebody help me out..... Thanx in advance! Mr.BArticle: 115212
cs_posting@hotmail.com wrote: > On Feb 2, 5:42 am, Andreas Ehliar <ehl...@isy.liu.se> wrote: > >> timer <= timer+1; >> >> if ((stage=waiting)) then >> timer<="0000"; >> stage<=start; > (unrelated portion removed) >> end if; >> >> if reset='1' then >> timer<="0000"; >> stage<=waiting; >> end if; > > > It doesn't seem to solve the problem, and there may be some obscure > language "rule" for disambiguation, but I don't like seeing what > appear to be three different attempts to assigned a value to the timer > register. > > Wouldn't it be better practice to "else" them? If (reset)... > elsif(waiting)... else > Within a process (as this is), that's explicitly valid VHDL. The statements are defined to execute sequentially, leaving the signal set to the value given by the last statement executed.Article: 115213
There have been some previous threads concerning problems with the OCM
bus, like these two:
http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/ce10f6d6187f5c41/da855826eda1b897?lnk=gst&q=OCM+BRAM&rnum=2&hl=en#da855826eda1b897
-- "Sharing BRAM between Xilinx PowerPC's (on data-OCM ports)"
http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/ee202caf22a1cbeb/3b6678222f17bda9?lnk=gst&q=OCM+BRAM&rnum=4&hl=en#3b6678222f17bda9
- also titled ""Sharing BRAM between Xilinx PowerPC's (on data-OCM
ports)"
To echo what has been discussed in these threads, our research team
has experienced several issues with the OCM bus. Specifically, we have
been using the BRAMs connected to the OCM bus with an EDK-provided OCM
Controller version 3.00.a on the Virtex 2 Pro family. While these
issues did not manifest themselves on the XC2VP30 part (on the XUP
board) for this project (http://tcc.stanford.edu/publications/
tcc_atlas_warfp2006.pdf), we experienced them on the XC2VP70 parts (on
the BEE2 board). To get an understanding of how we have our design is
structured, please refer to page 4, figure 4a of this paper: http://
tcc.stanford.edu/publications/tcc_atlas_fpga2007.pdf (more info about
our project is http://tcc.stanford.edu/prototypes/). In all we saw
three bugs:
Bug 1
====
PowerPC 405 pseudo code
....
store @ address A with data B to OCM BRAM
couple ALU ops (setting up load/store base addresses in registers)
store @ address C with data D to OCM BRAM
some ALU ops (setting up load/store base addresses in registers)
store @ address E to PLB to our PLB pcore (300 cycles - TCC cache in
our design)
load @ address A, returns data D from OCM BRAM
Issue: In this scenario that the OCM load returns the last OCM store,
regardless of the address that was written and read. For some reason,
the OCM bus and/or BRAM controller is buffering/caching the last value
stored. We have only observed this buffering taking place when we have
the 300-cycle PLB store. A shorter PLB store does not reproduce this
effect.
Workaround: We inserted a synch instruction after the PLB store.
Bug 2
====
>From time-to-time, a load or store with an address within the address
range for the OCM BRAM would appear on the PLB bus. Unfortunately,
since there is no slave device on the PLB bus within that address
range, we get a PLB bus error. We discovered this problem using
ChipScope.
Workaround: We could not find a software-based workaround as for Bug
1, so we moved the OCM BRAMs to the PLB bus.
Bug 3
=====
pseudo-code
loop_start:
data = load from A # port A of BRAM connected to OCM
controller
if(data == flag) goto exit # write is done thru port B,
connected to our pcore
goto loop_start
exit:
Issue: Sometimes the processor is stuck in this loop forever, even
though the BRAM entry at address A has been written by our pcore using
the BRAMs other port with the flag (user_switch in figure 4 a in this
paper: http://tcc.stanford.edu/publications/tcc_atlas_fpga2007.pdf).
Both ports are using the same clock (100 MHz) and clock edge.
Moreover, we have conflict resolution logic in our pcore such that if
the pcore detects the assertion of the port A's enable signal, it
stalls the write going to port B until port A's enable signal is de-
asserted. In spite of this, 1 out of a million setting of the flag
variable does fails (i.e. the processor is stuck in this infinite
loop). At first, we suspected that the datapath to our pcore or the
pcore was failing, but we verified that the datapath was bug-free. Bug
1 led us to suspect that that in the cases that there is a failure,
the OCM bus or BRAM controller is buffering variable data so that it
misses the update from our pcore.
Workaround: We implemented a high-level software time-out mechanism
such that after the processor loops for a certain period of time, it
sends a retry notification to flag-setter. This solution works
reliably.
Summary: Eventually, we removed all the OCM buses from our design and
then we migrated the BRAMs to the PLB buses. Using PLB BRAMs removed
all three bugs without the insertion of the software workarounds we
previously developed. While we cannot comment about the OCM interface
on Virtex 4 or 5's, we recommend against using the OCM BRAMs on the
Virtex 2 Pro family (especially on the XC2VP70 parts).
Performance Note: We initially chose to use the OCM bus because of its
short latency as compared to the PLB. To compare the latencies of
using BRAMs on the two buses, we wrote the following test code in
PowerPC assembly:
turn on instruction cache (use PLB BRAM to store code) # loop code
fits inside PowerPC cache
set loop iterator register # 32k iterations
set base address
start PowerPC timer
loop_start:
load
...
load # 100th load
bdnz loop_start # decrement loop iterator and goto loop_start if not
less than zero
read PowerPC timer
cycles per load = timed cycles / (number of iterations * 100)
The following are the results of OCM and PLB BRAM controllers:
OCM load = 2 cycles
OCM store = 2 cycles
PLB load = 11 cycles
PLB store = 8 cycles
Stores take less time on the PLB since the ack is asserted as soon as
the data arrives at the controller, whereas for the load the ack takes
place when the data is read from BRAM. Also, turning on the
instruction cache shortens the latencies.
Article: 115214Francesco wrote: > Hi, I'm just wondering how many people here are using ISE 9.1. > Could you post your experience here? I just got my full version of ISE (not webpack) and tried routing my current design. As part of the design, I use the DCM Standby workaround. I can import all the DCM Standby code into the GUI, but XST gives an error saying that there are missing modules. I opened a webcase, and my tech support person gets the same error that I do. --- Joe Samson Pixel VelocityArticle: 115215
On 2=D4=C23=C8=D5, =C9=CF=CE=E75=CA=B150=B7=D6, bharadwaj...@gmail.com wrot= e: > Hey All... > > Is there a way to decode the interconnect/Routing algorithm used by > Xilinx???? I see that the XDL file gives information on the routing > details. However, the interconnect/Routing details are given as > numbers. Also, > It gives info on PIPs, but I really dunno how to decode it. Could > somebody help me out..... > > Thanx in advance! > > Mr.B I want to know it too.Article: 115216
This is a very complicated subject, with many hundred man-years of development behind it. Tell us: Why do you want to know, or why do you need to know? Peter Alfke, Xilinx On Feb 2, 10:02=C2=A0pm, "2mao" <zhouh...@gmail.com> wrote: > On 2=E6=9C=883=E6=97=A5, =E4=B8=8A=E5=8D=885=E6=97=B650=E5=88=86, bharadw= aj...@gmail.com wrote: > > > Hey All... > > > Is there a way to decode the interconnect/Routing algorithm used by > > Xilinx???? =C2=A0I see that the XDL file gives information on the routi= ng > > details. However, the interconnect/Routing details are given as > > numbers. Also, > > It gives info on PIPs, but I really dunno how to decode it. Could > > somebody help me out..... > > > Thanx in advance! > > > Mr.B > > I want to know it too.Article: 115217
bharat_in wrote: > Hi, > Does anyone know how to implemtent circle generation algorithm in > verilog? > i want to implement it in spartan 3 kit,for VGA pattern generator. > i don't want to use ROM and RAM. > please, reply as soon as possible > Have a look at the algorithm in "Computer Principles and Practices" Foley, Van Dam, et al. The circle drawing algorithm is implemented in the C programming language but you should be able to convert it into verilog.Article: 115218
On Feb 2, 3:53 pm, "bharat_in" <ecbha...@gmail.com> wrote: > Hi, > Does anyone know how to implemtent circle generation algorithm in > verilog? > i want to implement it in spartan 3 kit,for VGA pattern generator. > i don't want to use ROM and RAM. > please, reply as soon as possible Hi, I got it working OK with my Spartan-3 Starter Kit-200K a while ago when I was experimenting with VGA graphics and the start of a vector engine. I was really outside the timing limits but it looked good anyway. The advise I could give you to follow my example (not to blow the actual joy of implementing it) is to do Pyhtagoras Thorem: http://www.cut-the-knot.org/pythagoras/index.shtml using the hardware multiplier.. Well I'm just a newbie so someone can probably think of a more effective way..Article: 115219
Hi, On Feb 1, 4:46 am, <carshie> wrote: > > Some questions: > > > 1) are you saying that clka is toggling in the simulation, > > but clkb goes high and stays high? > > Yes!!! > > > > > 2) whatsimulator? > > ISE8.2 Test Bench Waveform - Generate Expected Simulation > Do not run this flow. This is a flow with Known Issues and that is why Xilinx has removed it in the 9.1i version. Try this in the behavioral simulation flow and see if it works. If it does, then use that flow. > > 3) did you look at the simulation model for buf? Are you sure the > > order of the module ports is correct in your instantiation? Buf is just a verilog construct. It should not use the simulation model. > > No I didn't look at this, but I believe with and/or/not/buf the convention > is output comes before the input. Thanks DuthArticle: 115220
As an update on the two threads linked below (that I started), I never did find a way to use the OCM successfully in my project. I just attach everything to the PLB and have to live with the increased latency. The Xilinx Answer Record #14052 (Virtex-II Pro PowerPC 405 errata) has some interesting details on this problem. This is the problem I experienced, and it sounds like the same issue for the Stanford TCC group as well. See Solution 11 (CPU_212) on the page, which has the following description: -- While waiting for a Data Side PLB (DSPLB) load to complete, the PPC405 Core might ignore a valid store completion from Data Side OCM (DSOCM) when a particular sequence of operations occurs. This condition can occur in a system using both DSPLB and DSOCM interfaces. This condition can cause the PPC405 to hang or can result in incorrect values for registers in these operations. -- You can also see the IBM version of the errata at ftp://ftp.xilinx.com/pub/documentation/misc/ppc405f6v5_2_0.pdf which has different details on the same problem. It's a shame the OCM's are buggy in this regard. It really makes them unusable for any kind of serious project that uses both the PLB and OCM. As I recall, the same errata note is present in the Virtex-4 parts. Perhaps the Virtex-5 FX will finally fix this? Jeff Shafer http://www.cs.rice.edu/CS/Architecture/ricenic/ "Nju Njoroge" <njoroge@stanford.edu> wrote in message news:1170456694.770818.198020@a75g2000cwd.googlegroups.com... > There have been some previous threads concerning problems with the OCM > bus, like these two: > > http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/ce10f6d6187f5c41/da855826eda1b897?lnk=gst&q=OCM+BRAM&rnum=2&hl=en#da855826eda1b897 > -- "Sharing BRAM between Xilinx PowerPC's (on data-OCM ports)" > > http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/ee202caf22a1cbeb/3b6678222f17bda9?lnk=gst&q=OCM+BRAM&rnum=4&hl=en#3b6678222f17bda9 > - also titled ""Sharing BRAM between Xilinx PowerPC's (on data-OCM > ports)"Article: 115221
I was just evaluating 9.1 (Webpack). I'm using small S3 and I have to
wonder if Xilinx is just doing optimization(s) for high end parts. For
my design, running in XC3S50, performance (both area and speed)
degraded. I'm using a "make" driven flow and the settings (command
line args and files) are the same for both 9.1/8.2 runs (actually I
use a flow that I put togheter in 7.1 days or so).
Data from *syr:
8.2.03i - xst I.34:
Number of Slices: 713 out of 768 92%
Number of Slice Flip Flops: 428 out of 1536 27%
Number of 4 input LUTs: 1306 out of 1536 85%
Number used as logic: 1258
Number used as RAMs: 48
9.1i - xst J.30:
Number of Slices: 696 out of 768 90%
Number of Slice Flip Flops: 428 out of 1536 27%
Number of 4 input LUTs: 1268 out of 1536 82%
Number used as logic: 1220
Number used as RAMs: 48
Data from *par:
8.2.03i par I.34
Number of RAMB16s 4 out of 4 100%
Number of Slices 699 out of 768 91%
Number of SLICEMs 24 out of 384 6%
9.1i par J.30
Number of RAMB16s 4 out of 4 100%
Number of Slices 753 out of 768 98%
Number of SLICEMs 24 out of 384 6%
Data from *twr:
8.2.03i:
Timing errors: 0 Score: 0
Constraints cover 100721 paths, 0 nets, and 5844 connections
Design statistics:
Minimum period: 19.976ns (Maximum frequency: 50.060MHz)
9.1i:
Timing errors: 1 Score: 325
Constraints cover 101771 paths, 0 nets, and 5659 connections
Design statistics:
Minimum period: 20.650ns (Maximum frequency: 48.426MHz)
Run time for my flow:
8:2
420.14 real 343.23 user 6.20 sys
9.1
420.73 real 343.84 user 6.07 sys
I did not spend a lot of time in reading the new documentation for xst/
map/par to look for new switches/setting. If you are aware of eny
please comment.
It seems the bit stream generated with 9.1 is running just fine in my
applications (one data point, no temp/voltage/corners).
---
Regards,
mmihai
Article: 115222bharat_in wrote: > Hi, > Does anyone know how to implemtent circle generation algorithm in > verilog? > i want to implement it in spartan 3 kit,for VGA pattern generator. > i don't want to use ROM and RAM. > please, reply as soon as possible Seems like you could use a CORDIC, giving it the angle as an input and getting the coordinates of the circle out. Check out: http://my.execpc.com/~geezer/embed/cordic.htm There are several decent free sources for CORDIC IP out there. TomArticle: 115223
tdillon@dilloneng.com wrote: > bharat_in wrote: > >>Hi, >>Does anyone know how to implemtent circle generation algorithm in >>verilog? >>i want to implement it in spartan 3 kit,for VGA pattern generator. >>i don't want to use ROM and RAM. >>please, reply as soon as possible > > > Seems like you could use a CORDIC, giving it the angle as an input and > getting the coordinates of the circle out. > > Check out: > > http://my.execpc.com/~geezer/embed/cordic.htm > > There are several decent free sources for CORDIC IP out there. > > Tom > Bresenham's circle drawing algorithm is far simpler to implement. It was originally developed for exactly this application. Google "bresenham circle" to get all the info you'll need.Article: 115224
On Feb 3, 1:17 am, "Peter Alfke" <a...@sbcglobal.net> wrote: > This is a very complicated subject, with many hundred man-years of > development behind it. > Tell us: > Why do you want to know, or why do you need to know? > Peter Alfke, Xilinx > > On Feb 2, 10:02 pm, "2mao" <zhouh...@gmail.com> wrote: > > > On 2=E6=9C=883=E6=97=A5, =E4=B8=8A=E5=8D=885=E6=97=B650=E5=88=86, bhara= dwaj...@gmail.com wrote: > > > > Hey All... > > > > Is there a way to decode the interconnect/Routing algorithm used by > > > Xilinx???? I see that the XDL file gives information on the routing > > > details. However, the interconnect/Routing details are given as > > > numbers. Also, > > > It gives info on PIPs, but I really dunno how to decode it. Could > > > somebody help me out..... > > > > Thanx in advance! > > > > Mr.B > > > I want to know it too. I know It is way too complicated..... :-) I am working on partial reconfiguration ryte now....my prof wanted me to dig deep dwn into it......if I get to know abt the routing details, I may b able to work on different benchmark ckts.... Thank you pete..... Mr.B
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