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Messages from 115300

Article: 115300
Subject: Re: help with Design Compiler -> Quartus
From: Mike Treseler <mike_treseler@comcast.net>
Date: Tue, 06 Feb 2007 08:11:39 -0800
Links: << >>  << T >>  << A >>

>> On Jan 30, 8:04 am, "Sebastian Schüppel" wrote:
>>> I have a source code which is compiled by the Design Compiler from
>>> Synopsys. I also mapped my technology library to that, so it will
>>> generate a VHDL netlist.

It sounds like you have a vendor netlist
for Synopsys libraries, not source code.

>>> My problem is that there are Components declarations and
>>> instantiations in the netlist with no architecture.
>>> And I'd like to use this netlist as a component of my design in
>>> Altera's Quartus software.
>>> Can someone tell me how I get this fixed.

Buy the source code or write your own.

> Yes, the reson why I use the design compiler (better to say I use a gui 
> which sits on top of it. called coreConsultant) is because it is a 
> designware source which is encrypted.

I would not expect that a black box by Synopsys
would work with any tools not specified by Synopsys.

       -- Mike Treseler

Article: 115301
Subject: Re: DDR FPGA Design
From: nico@puntnl.niks (Nico Coesel)
Date: Tue, 06 Feb 2007 18:18:54 GMT
Links: << >>  << T >>  << A >>
"Tommy Thorn" <tommy.thorn@gmail.com> wrote:

>Having read through a bunch of Xilinx DDR app notes, I'm confused. It
>seems that the only way to use DDR with a Spartan-3 at high speed is
>to deal with a carefully constructed LUT-delay chain, subject to
>manual routing and other nightmares. Other competing products, such as

I wouldn't go that route. It will require regular delay calibrations
because of temperature changes and aging. Worse, it will make your
design behave different in every product you make because each fpga
will have different delays. An FPGA which is just within spec may
trigger a bug in your design! The best way in a Spartan3 and similar
devices is using a shifted clock to feed the IOB flipflops.

>the Cyclone I & II have programmable delays in some of the IOBs,
>making centering on the DQS trivial in comparison.

You can use the IOB delay in the Spartan3 to center the DQS, but the
routing of the DQS clock to the IOB flipflops is very restricted and
not (well) documented. You'll need to design the FPGA first and then
the PCB. Also, the timing is more critical then when using a shifted
clock! I posted some messages in this newsgroup on this topic before.

Expect a Spartan3 DDR design to run at 100MHz in speedgrade 4 and at
125MHz in a speedgrade 5 device.


-- 
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

Article: 115302
Subject: regarding the usage of embedded ethernet MAC on Virtex4
From: "bachimanchi@gmail.com" <bachimanchi@gmail.com>
Date: 6 Feb 2007 12:33:48 -0800
Links: << >>  << T >>  << A >>
Hi all,
I started working on interfacing PC with Virtex4 FPGA through Ethernet
Embedded MAC which is there on Virtex4 FPGA. I am kind of new to this
task and I am really not sure how to start of with.My problem is I
don't know anything else other than VHDL. When I was going through the
documentation it has some C files.One question is ,if I have a design
which is totally described in VHDL and I would like to have a ethernet
wrapper around it which can be done by using ip core.I am using
Virtex4 FX12 mini module from memec. What is the next step to do if I
want to observe the data on the monitor,what is the next step? How to
use XPS to generate all these,in particular how to include the VHDL
files so that the bit stream will be generated?Can someone suggest me
anyplace where it has a good example which is clearly explained.Thanks
for the help.

Thanks,

Ramakrishna


Article: 115303
Subject: Re: Xilinx Virtex5 board
From: "mike_la_jolla" <mdini@dinigroup.com>
Date: 6 Feb 2007 14:02:11 -0800
Links: << >>  << T >>  << A >>
On Feb 5, 9:14 pm, "vssumesh" <vssumesh_a...@yahoo.com> wrote:
> Hi,
>     We are trying to implemnt a very huge design. For that we need a
> v5lx330 fpga. Also we need video in/out, AD/DA converter greter than
> 128 MB DDR ram, expansion slot by which we can connect a daughter
> board with atleast 200 signals. We serached on the net but no reday
> avialble borads suits our requirement. Is there any way to modify the
> design of existing boards and a make a custom board which suits our
> requirement. If any boady knows about firms doing this type of
> activity please send me a link. Thanks in adavance.
> regards
> Sumesh V S

Try this:
   http://www.dinigroup.com/index.php?product=DN9000k10PCI
   http://www.dinigroup.com/DNMEG_ADDA.php


Article: 115304
Subject: Re: 9.1i in Red Hat Enterprise Linux AS 64-bit
From: "Edoardo Causarano" <edoardo.causarano@gmail.com>
Date: 6 Feb 2007 16:36:51 -0800
Links: << >>  << T >>  << A >>
On 5 Feb, 16:16, xingzhi <xingzhi...@hotmail.com> wrote:
> I was trying to installing Xilinx ISE 9.1i full version on RHEL 4 AS 64-bit and I got following errors:
>
> error while loading shared libraries: libstdc++.so.5: cannot open shared object file: No such file or directory
>
> The Xilinx Webpage says RHEL 4 WS 64-bit is supported. Does this mean only WS not AS is supported? Any one succeed on installing 9.1i on AS/ES ?
>
> Thanks

check the executable (file <executable>) and verify if it's 32 bit or
64, then check if the libstdc++ libraries installed are 32 or 64 bit
The library paths are different for the two archs and you need the
appropriate kind for the program to run. Probably you only have the
EM64T version installed, so rpm -ivh <lib>.i386.rpm and you're set.

e


Article: 115305
Subject: Question about programming a FPGA using Modelsim Designer instead of ISE?? can it be done?
From: "tony.uniquify@gmail.com" <tony.uniquify@gmail.com>
Date: 6 Feb 2007 17:47:20 -0800
Links: << >>  << T >>  << A >>
HI All,

I am confused. I have the free version of ISE 9.1

>From what I understand, the free version limits me to the low end
FPGAs that I can download my designs onto.
If I wanted to use higher end FPGAs, then I would have to buy Xilinx
ISE full version.

Is Xilinx ISE the only tool I can use to program my FPGA (eg. Virtex 5
LX330) ?
Same with Alter's FGPA, Quartus?
Do you have to use vender specific tools to program that specific
FPGA?

Will Mentor's Graphics Modelsim Designer, also a FPGA software tool,
be able to program my design onto any FPGAs? From what I understand,
no. It only does simulation, synthesis, and place and route.  I still
have to implement the design (constraints) and program the FPGA
(iMPACT). Please correct me if I am mistaken.

Thanks,
-Tony


Article: 115306
Subject: Multiple MicroBlaze based Multiprocessor system
From: "Shant" <shantchandrakar@gmail.com>
Date: 6 Feb 2007 19:36:04 -0800
Links: << >>  << T >>  << A >>
Hello All,

Is it possible to instantiate multiple MicroBlaze through Base System
Builder in anyways, The tutorial says that
"BSB does not support multi-processor systems". I want to instantiate
more than one MicroBlaze communicating with each other through FSLs.

In my previous post I mentioned about the UNKNOWN Processor problem,
but now that problem has been solved, and I am getting

"ERROR:MDT - MicroBlaze Pipeline Stalled executing Instruction at >>
PC:  0x00000000
   Try Resetting the Processor to Continue..

While debugging my helloworld code through GNU and XMD.

I Started implementing my embedded system right from scratch i.e.
chose Blank project while creating a new project.

If any one of you can suggest me something regarding instantiation of
multiple MicroBlazes for creating multiprocessor system, that will be
a great help to me...

Thanks and Regards,
Shant Chandrakar


Article: 115307
Subject: Re: Multiple MicroBlaze based Multiprocessor system
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Wed, 07 Feb 2007 15:33:44 +1000
Links: << >>  << T >>  << A >>
Hi Shant,

Shant wrote:

> Is it possible to instantiate multiple MicroBlaze through Base System
> Builder in anyways, The tutorial says that
> "BSB does not support multi-processor systems". I want to instantiate
> more than one MicroBlaze communicating with each other through FSLs.

BSB is intended to quickly get you to a simple working system.  For this 
reason it can only create a single processor designs.

However, once you pass through BSB and have your "starting point", then 
you can use platform studio (XPS) to add multiple microblaze CPUs like 
any other core.  Just select CPU->MicroBlaze from the IP core catalog on 
the left hand side of the screen, right click to add, and then 
connect/configure as required.

My experience says if you are doing multiprocessor designs you will be 
more effective if you work directly on the MHS files in a text editor - 
they give much better visibility and control when doing compilcated 
systems.

Regards,

John

Article: 115308
Subject: Spartan-3E starter kit : trouble with configuration from NOR Flash
From: "Saqib" <engr.saqib.riaz@gmail.com>
Date: 6 Feb 2007 23:52:34 -0800
Links: << >>  << T >>  << A >>
Hi, I have recently purchased the Spartan-3E starter kit and I am
having trouble to

configure the FPGA with what is in the NOR Flash.

I am using the RS-232 programmer for NOR Flash available as Reference
Design.

Reading back the data showed me that the NOR Flash is indeed loaded
with the program but it just can't get that into the FPGA on startup.

Can anyone provide me with any help on this issue?

Does i need to send the hardware back??

I am running ISE 8.2i.


Article: 115309
Subject: Re: Spartan-3E starter kit : trouble with configuration from NOR Flash
From: "Pablo" <pbantunez@gmail.com>
Date: 7 Feb 2007 00:42:53 -0800
Links: << >>  << T >>  << A >>
On Feb 7, 8:52 am, "Saqib" <engr.saqib.r...@gmail.com> wrote:
> Hi, I have recently purchased the Spartan-3E starter kit and I am
> having trouble to
>
> configure the FPGA with what is in the NOR Flash.
>
> I am using the RS-232 programmer for NOR Flash available as Reference
> Design.
>
> Reading back the data showed me that the NOR Flash is indeed loaded
> with the program but it just can't get that into the FPGA on startup.
>
> Can anyone provide me with any help on this issue?
>
> Does i need to send the hardware back??
>
> I am running ISE 8.2i.

Are you configuring the "Jumper Settings"???


Article: 115310
Subject: Re: Question about programming a FPGA using Modelsim Designer instead of ISE?? can it be done?
From: Colin Paul Gloster <Colin_Paul_Gloster@ACM.org>
Date: 7 Feb 2007 08:45:17 GMT
Links: << >>  << T >>  << A >>
Anthony wrote:

"[..]

Is Xilinx ISE the only tool I can use to program my FPGA (eg. Virtex 5
LX330) ?
Same with Alter's FGPA, Quartus?"

They are the only free synthesis tools which can be used to program
those FPGAs, but if you have many thousands of dollars you can buy
another synthesis tool to program them, e.g. from Synopsys and Synplicity.

"Do you have to use vender specific tools to program that specific
FPGA?"

No.

"Will Mentor's Graphics Modelsim Designer, also a FPGA software tool,
be able to program my design onto any FPGAs? From what I understand,
no. It only does simulation, synthesis, and place and route.  I still
have to implement the design (constraints) and program the FPGA
(iMPACT). Please correct me if I am mistaken."

Modelsim is only for simulations.

Article: 115311
Subject: Re: Xilinx Virtex5 board
From: bijoy <pbijoy@rediffmail.com>
Date: Wed, 7 Feb 2007 00:58:29 -0800
Links: << >>  << T >>  << A >>
Hi sumesh

Could you please tell me more details of your requirement, like do you need to make new boards or fpga design or etc. so that i can suggest some companies working in this area.

rgds bijoy

Article: 115312
Subject: question about power dissipation
From: "Geronimo Stempovski" <geronimo.stempovski@arcor.de>
Date: Wed, 7 Feb 2007 10:07:21 +0100
Links: << >>  << T >>  << A >>
I just read an interesting paper about high-speed I/O's power dissipation.
Unfortunately there is an equation I don't quite understand. Maybe someone 
is in the mood for discussing and explaining the correctness of the equation 
to me.
The formula I am talking about is (1) in the paper [ 
http://www.ee.ucla.edu/faculty/papers/yang-ckk_ieeeTransCircSystems2_nov2006.pdf ]

For high-common mode signaling (which standard would that be, anyway? TTL? 
CMOS? SSTL?) it is assumed
P = V*Vswing/Z0 = V*Vrx/Z0*H(f)

For low-common mode signaling (LVDS? CML? LVPECL?) it states
P = Vswing^2/2*Z0 = Vrx^2/2*Z0*H(f)^2

What I don't understand is the factor 2 (2*Z0) in the calculation of the 
low-common mode signaling. Furthermore I'm not sure if the H(f)^2 is 
correct.

Any help is highly appreciated! Thanks a lot in advance!

Regards, Gero 



Article: 115313
Subject: Re: Question about programming a FPGA using Modelsim Designer instead
From: Sean Durkin <news_feb07@durkin.de>
Date: Wed, 07 Feb 2007 10:11:27 +0100
Links: << >>  << T >>  << A >>
tony.uniquify@gmail.com wrote:
> Is Xilinx ISE the only tool I can use to program my FPGA (eg. Virtex 5
> LX330) ?
> Same with Alter's FGPA, Quartus?
> Do you have to use vender specific tools to program that specific
> FPGA?
"Program" is not very specific. If you want to use an FPGA, you need
several tools:

1. An editor to write your HDL code in. You could use Xemacs, Eclipse,
Notepad++, jedit,... or the editor included in ModelSim.
2. A simulator to test your Verilog/VHDL code. This could be ModelSim,
but there are alternative.
3. A synthesis tool that translates your VHDL code into a netlist. I.e.
out of "counter <= counter + 1" it constructs an adder and so on. There
are numerous synthesis tools from different vendors. There's Synplify,
Precision Synthesis, Synplicity... Xilinx ISE and Altera's Quartus also
include synthesis tools.
4. Backend tools that do place and route and in the end convert your
netlist into a configuration file that can be loaded into the FPGA.
Since the architecture of the FPGAs is the vendor's biggest secret,
there are no third-party tools for this. Place and Route and bitfile
generation has to be done with the tools offered from the FPGA vendor.
That means, you need ISE for Xilinx FPGAs and Quartus for Altera FPGAs
and so on. Plus, you need a version of the tools that supports the
specific device you're targetting. That means, if you want to use a
Virtex5LX330, you need the full version of ISE. There are no alternatives.
5. A tool to download the configuration file to the FPGA after power-up
(this is what you usually call "programming an FPGA"). You can do this
via JTAG, using ISE's iMPACT for example, but there are third-party
tools that can do this as well.

Xilinx ISE and Altera's Quartus are tool suites that include everything
from 1. to 5.

> Will Mentor's Graphics Modelsim Designer, also a FPGA software tool,
> be able to program my design onto any FPGAs? From what I understand,
> no. It only does simulation, synthesis, and place and route.
ModelSim Designer itself doesn't do anything but compile and simulate
the design. For everything else, it calls external programs. So you
still need a synthesis tool, a tool that does place&route, and something
to download the configuration. You can maybe start up these programs
from the Designer GUI, but you still need to have them.
I'm not familiar with ModelSim Designer, but I assume you can create
scripts to start external programs, so you could make one to execute the
entire synthesis and place and route flow and have iMPACT download the
bitstream.

-- 
My email address is only valid until the end of the month.
Try figuring out what the address is going to be after that...

Article: 115314
Subject: Re: Multiple MicroBlaze based Multiprocessor system
From: Philip Herzog <phd@arcor.de>
Date: Wed, 07 Feb 2007 10:29:35 +0100
Links: << >>  << T >>  << A >>
Shant wrote:
> Is it possible to instantiate multiple MicroBlaze 

It is possible to add two microblaze to a system within EDK and connect
them through OPB - I had this up and running for a test. Debugging is
not very comfortable though. You can connect XMD to one of the
processors but you always influence the other somehow (stopping only one
did not work, or serial output got mixed up...)

It is not possible to instatiate a microblaze-based system two times.

-   Philip
-- 
while (!asleep()) sheep++;



Article: 115315
Subject: Re: Spartan-3E starter kit : trouble with configuration from NOR Flash
From: "Saqib" <engr.saqib.riaz@gmail.com>
Date: 7 Feb 2007 01:30:21 -0800
Links: << >>  << T >>  << A >>
On Feb 7, 1:42 pm, "Pablo" <pbantu...@gmail.com> wrote:
> On Feb 7, 8:52 am, "Saqib" <engr.saqib.r...@gmail.com> wrote:


> Are you configuring the "Jumper Settings"???- Hide quoted text -
>
> - Show quoted text -

if you are talking about mode jumper settings, yes i have configured
them for BPI-UP mode.



Article: 115316
Subject: Re: or1k on spartan 3, 400K gate version
From: "Sandro" <sdroamt@netscape.net>
Date: 7 Feb 2007 02:25:55 -0800
Links: << >>  << T >>  << A >>
On Feb 5, 3:25 pm, "CMOS" <manu...@millenniumit.com> wrote:

>...
> are there any other free processor cores available which would fit in
> to spartan 3, 400K version with GNU toolchain support?
>...

I'm playing with Plasma - most MIPS I(TM) opcodes
   http://www.opencores.org/projects.cgi/web/mips/overview
It fit in a spartan3 XC3S200
the author provides a cross gcc compiler for windows or You can
recompile (as me) a cross gcc for linux

Sandro


Article: 115317
Subject: Re: : Is Digilent still in business ???
From: "Sandro" <sdroamt@netscape.net>
Date: 7 Feb 2007 02:32:14 -0800
Links: << >>  << T >>  << A >>
On Feb 5, 9:44 pm, Kosta Xonis <ChaosKo...@web.de> wrote:
> ...
> Same for the 2nd & 3rd try...
>
> Are they still in business ??
> ...

I sent  an e-mail to the digilent support  20/01/2007 (Yes Saturday)
and received an answer 22/01/2007...
I'll suggest you to retry

Sandro



Article: 115318
Subject: Re: question about power dissipation
From: "operator jay" <none@none.none>
Date: Wed, 7 Feb 2007 04:41:48 -0600
Links: << >>  << T >>  << A >>

"Geronimo Stempovski" <geronimo.stempovski@arcor.de> wrote in message 
news:45c996d0$0$30311$9b4e6d93@newsspool1.arcor-online.net...
>I just read an interesting paper about high-speed I/O's power 
>dissipation.
> Unfortunately there is an equation I don't quite understand. Maybe 
> someone is in the mood for discussing and explaining the correctness 
> of the equation to me.
> The formula I am talking about is (1) in the paper [ 
> http://www.ee.ucla.edu/faculty/papers/yang-ckk_ieeeTransCircSystems2_nov2006.pdf ]
>
> For high-common mode signaling (which standard would that be, 
> anyway? TTL? CMOS? SSTL?) it is assumed
> P = V*Vswing/Z0 = V*Vrx/Z0*H(f)
>
> For low-common mode signaling (LVDS? CML? LVPECL?) it states
> P = Vswing^2/2*Z0 = Vrx^2/2*Z0*H(f)^2
>
> What I don't understand is the factor 2 (2*Z0) in the calculation of 
> the low-common mode signaling. Furthermore I'm not sure if the 
> H(f)^2 is correct.
>
> Any help is highly appreciated! Thanks a lot in advance!
>
> Regards, Gero
>

I don't know the topic or the equation in question, however,

P = Vpeak/sqrt(2) * Vpeak/sqrt(2) / R = Vpeak^2 / 2 * R
would give power for a simple AC voltage applied to an R.  Here the 
factor of 2 is 'changing' the voltages to their RMS values.  Could it 
be similar in the equation you are looking at?



Article: 115319
Subject: Re: Question about programming a FPGA using Modelsim Designer instead of ISE?? can it be done?
From: "tony.uniquify@gmail.com" <tony.uniquify@gmail.com>
Date: 7 Feb 2007 02:46:39 -0800
Links: << >>  << T >>  << A >>
Thank you Sean and Colin, I have a better understanding now.

Actually, I was told that ModelSim Designer (not modelsim LE, PE, SE)
is suppose to have steps 1-5 (above), but according to their website,
it is all the same.

http://www.model.com/products/products_designer.asp

"ModelSim Designer only seems supports easy interface with synthesis
and place and route tools."

It seems like I still have to buy my steps 3-5 elsewhere. Correct?

Thanks again.
-Tony







Article: 115320
Subject: Re: question about power dissipation
From: "Geronimo Stempovski" <geronimo.stempovski@arcor.de>
Date: Wed, 7 Feb 2007 11:49:03 +0100
Links: << >>  << T >>  << A >>

"operator jay" <none@none.none> schrieb im Newsbeitrag 
news:D2iyh.66715$sE7.14995@newsfe21.lga...
>
> factor of 2 is 'changing' the voltages to their RMS values.  Could it be 
> similar in the equation you are looking at?

Thank you, Jay. Unforutnately not. Could I mail you the paper and you have a 
look at it? What's your email adress? My email adress is valid, by the way. 



Article: 115321
Subject: Modelsim SE 6.2c trying to use Xilinx ISE 9.1i simulation libraries... not working.
From: "Tony Thai" <tony.uniquify@gmail.com>
Date: 7 Feb 2007 03:34:28 -0800
Links: << >>  << T >>  << A >>
Hi All,

Hopefully this is a simple fix...
I complied Xilinx simulation libraries with COMPXLIB... and it seemed
to worked fine.
The modelsim.ini was changed to point to the new libraries. I checked
ModelSim to
see if xilinx libraries were in the library window (panel/tab), and
they were as expected.

When I start to compile my design, I see this message (not warning or
error):

# Referenced (but uncompiled) modules or primitives:
# 	IBUFG
# 	BUFG
# 	DCM

So it seem to compile file, until I try to simulate my design, I see
this error:

# ** Error: C:/XXX: Module 'IBUFG' is not defined.
# ** Error: C:/XXX:: Module 'BUFG' is not defined.
# ** Error: C:/XXX: Module 'BUFG' is not defined.
# ** Error: C:/XXX: Module 'DCM' is not defined.
# ** Error: C:/XXX: Module 'IBUFG' is not defined.

I cheked the UNISIM_VER library.. and I see all three modules... but
for some reason, the tool doesn't pick up the library.

I have "-y C:/Xilinx91i/verilog/mti_se/unisims_ver +libext+.v" but
this doesn't seem to work..
Under that directory... all i see are folders with
"@a@f@i@f@o36_@i@n@t@e@r@n@a@l" instead of seeing DCM.v or BUFG.v or
IBUFG.v.

any clue?

Thanks for reading this.
-Tony


Article: 115322
Subject: Re: Question about programming a FPGA using Modelsim Designer instead
From: Sean Durkin <news_feb07@durkin.de>
Date: Wed, 07 Feb 2007 12:46:50 +0100
Links: << >>  << T >>  << A >>
tony.uniquify@gmail.com wrote:
> Thank you Sean and Colin, I have a better understanding now.
> 
> Actually, I was told that ModelSim Designer (not modelsim LE, PE, SE)
> is suppose to have steps 1-5 (above), but according to their website,
> it is all the same.
> 
> http://www.model.com/products/products_designer.asp
> 
> "ModelSim Designer only seems supports easy interface with synthesis
> and place and route tools."
> 
> It seems like I still have to buy my steps 3-5 elsewhere. Correct?
Yes. Judging from the site you posted, ModelSim Designer is simply
ModelSim with a few code developing tools, e.g. something to make
creating state machines and so on easier. But there are no FPGA tools
included. It just offers the possibility to control the tools via its
GUI. So you can write your code, simulate it, and start synthesis all
from the ModelSim Designer GUI, that's all.

-- 
My email address is only valid until the end of the month.
Try figuring out what the address is going to be after that...

Article: 115323
Subject: Re: generating VHDL code from Matlab code for DSP - wavelet image compression
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Wed, 07 Feb 2007 11:51:16 +0000
Links: << >>  << T >>  << A >>
"EEngineer" <maricic@gmail.com> writes:

> Is there a way of generating VHDL code from Matlab code for DSP, more
> precisely image processing using wavelet transform?
> I want to implement a small 8X8 image processing layout that will use
> wavelet transform and it is not easy to come up with the VHDL code for
> that. Any help would be highly appreciated!

If you're targetting Xilinx AccelDSP may be of use.

Otherwise, write a spec, and give it to a human VHDL-code-generator
:-)

You don't say how fast you need it to run and on what image sizes -
this may affect the feasibility of the conversion.

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

   

Article: 115324
Subject: Compile uCLinux for Spartan 3e
From: "Pablo" <pbantunez@gmail.com>
Date: 7 Feb 2007 04:32:09 -0800
Links: << >>  << T >>  << A >>
Does anyone Know how can I compile uClinux-dist for Spartan 3E. I have
done the next:

download uClinux-dist
download uClinux-2.4.x
cd uClinux-dist
ln -s ../uClinux-2.4.x linux-2.4.x
copy auto-config.in to arch/microblaze/platform....
PATH=$PATH:/usr/local/microblaze-elf-tools

make clean (an error occurr with images/CVS, I have to delete
manually)
make menuconfig

I can pass this. I have an error in arch/microblaze/config.in

Does I need to do something else????




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