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On Sat, 21 Oct 2006 11:39:31 +0100, Brian Drummond <brian_drummond@btconnect.com> wrote: >Any asynchronous signals or clocks in this design? Wasn't that, but almost as dumb. I forgot that some of my I/Os had explicit pullups in the RTL, and I added keepers in the UCF. The RTL sims worked, but the netlist ended up with keepers instead of pullups, and failed the sims. The sdf stuff all appears to be Ok. >Unfortunately I can't remember the >attribute. ASYNC_REG Thanks - EvanArticle: 110826
Yestarday I manage to compile the kernel! it is working now!!! As first attempt I don't have the 10/100 MAC yet. My next step will be to add a 10/100 MAC and try some network applications. ScottNortman wrote: > Yes, I am using mb 4.0. > > I built the kernel using xconfig. > > Please do keep me posted if you make progress. > > Thanks, > Scott > > Francesco wrote: > > Thanks Scott. > > I'm usimg the ml403 (ISE8.1) > > your link is very interesting. > > I just started to debbug the kernel. > > If I'll make any progress I'll send you an email. > > Do you use xconfig to menuconfig to build the kernel? > > I'm using xconfig... it should make any difference, but I have a friend > > with experience in Linux and he suggested to use menuconfig. > > > > I also read that people has fixed this problem using microblaze 3.0 > > (I'm using microblaze 4.0) > > But I do not think this is the "real" problem, because the kernel is > > running... what I need to do is "only" mount the root in the RAM. > > Maybe using microblaze 3.0 we "mask" the problem... some setting will > > be different and this errod does not happen...I want to go in deep and > > fix it properly and then "share" my results with you. > > > > > > Francesco. > > > > > > ScottNortman wrote: > > > I had the same problem... what FPGA are you using? I am using the > > > spartan 3e starter kit. > > > > > > I spent some time looking around the web and I found a site which > > > explains how to append the "root=" command properly; here is a link: > > > > > > http://www.ucdot.org/article.pl?sid=03/01/11/1049210&mode=thread > > > > > > However, even though I followed the instructions, I still got a new > > > error: > > > > > > ********* location > > > VFS test name = </dev/root> > > > Micr > > > VFS fs_name = <ext2>ash probe(0x21000000 > > > > > > VFS fs_name = <romfs> 21000000 > > > VFS root name <1f:01> > > > ********* > > > arena open of 1 failed!evice at location zero > > > > > > VFS: tried fs_name = <ext2> err = -19 > > > > > > > > > > > > Hope this helps; if you make any progress please let me know. > > > > > > Thanks, > > > Scott Nortman > > > > > > > > > David Ashley wrote: > > > > Francesco wrote: > > > > > Hi I'm trying to porting uclinux using microblaze 4.0. > > > > > When I try to run the OS I've got the following error message. > > > > > > > > > > Kernel panic: VFS: Unable to mount root fs on 1f:00 > > > > > > > > > > Does anybody had a similar problem? > > > > > > > > > > Thanks in advance, > > > > > Francesco > > > > > > > > > > > > > Linux is up but it can't mount the root > > > > partition. What is your kernel command line? > > > > What is the "root=xxx" specifically. That device > > > > number 1f:00 seems screwy. It's not listed in > > > > include/linux/major.h. > > > > > > > > -Dave > > > > > > > > -- > > > > David Ashley http://www.xdr.com/dash > > > > Embedded linux, device drivers, system architectureArticle: 110827
Hi, > -- > ARCHITECTURE blkram_ROM OF BLOCKROM_Coeffs IS > > type rom_type is array(255 downto 0) of std_logic_vector(15 downto 0); > > BEGIN > process(clk) > begin > if (clk'event and clk = '1') then > if (en = '1') then > data <= ROM(conv_integer(addr)); > end if; > end if; > end process; > END ARCHITECTURE blkram_ROM; > > As far as I know, I think it is because I have not used the Block_ram > attribute in the code..but i've seen a couple of code examples in the > newsgroup and on the internet and no where have i come accross such an > attribute for inferriing a ROM out of Block RAMs. I don't think there's anything wrong with your template for inferring the rom in block ram. I don't even think you will require the attributes you added, though I doubt they hurt. I think the problem is simply that the rom contents you specified are all zero, therefore the synthesizer optimises all this logic to a constant and removes it. > Second question: > Ive seen two major methods when inferring memory. One of them talks > about using library primitives in which there is no definition for the > architecture of the memory (or may be it is defined somewhere else)..It > directly instantiates a component for ex. a library primitive for > inferring a ROM which has a data bus which is 1 bit wide and has a 16 > bit long word is called ROM16X1 > (http://toolbox.xilinx.com/docsan/xilinx8/books/data/docs/lib/lib0363_...). > Does it mean that if I instantiate a component using this library > primitive then I dont need to worry about the internal architecture > right? Just use it directly and all works fine and gets synthesized all > right..isnt it? > Additionally some of them are called macros whereas some of them are > called primitives..could some one please shed some light into this. > (heres the xilinx link abt memory elements : > http://toolbox.xilinx.com/docsan/xilinx8/books/data/docs/lib/lib0039_... > ) > > The second one is directly writing HDL code which is more of a > behavioral description of what the memory does.. > > Whats the difference between the two methods? Additionally do these > methods work with synthesis tools.. Both methods work fine. Using RAM inferred from HDL is my preferred solution when ever possible. Doing so leads to faster simulation and generic code that applies equally to various different FPGAs (both in terms of vendors and families). On the other hand you cannot always infer a RAM which covers all the many features of, say, a Xilinx a block RAM from HDL code so on occasion it is necessary to get down and dirty and instantiate them yourself. > I've even heard that one has to do different kinds of memory > initialisations when simulating and when synthesizing.. > Like it would be different when i wanna simulate the behavior using > modelsim and when Im synthesizing it. I cant say I have ever needed the feature, but that may well be the case. The libraries guide should tell you all you need to know. Cheers, AndyArticle: 110828
> How about your PCB layout? Or your PDS? Got enough juice and decoupling > caps? The regualtors are PTH05000 (6 Amps) and they deliver the correct voltage (they are not yet at the limit) I was pretty confident about the layout but the ripple on my supply voltages is +- 100mV (on 2.5V and 1.5V) ... I guess that might be too much for 300 MHz operation? bye, MichaelArticle: 110829
> I don't know much about PPC's, but here's some > thoughts on DCM problems: wow - that is a pretty long list - thanks! I'm pretty sure we didn't looked at all of that I'll let you know when I find out ... A1) the topology is simply a 100MHz LVDS-oscillator feeding one DCM for 50/100/300 A2) I'm loading with JTAG or cclk - same problem A3) the markings on my V2P are hidden under a heat sink (I'll check if there is one board without it) A4) we did some tests on 4 boards - all of them show the same problem bye, MichaelArticle: 110830
Andy Ray wrote: > Hi, > >> -- >> ARCHITECTURE blkram_ROM OF BLOCKROM_Coeffs IS >> >> type rom_type is array(255 downto 0) of std_logic_vector(15 downto 0); > >> >> BEGIN >> process(clk) >> begin >> if (clk'event and clk = '1') then >> if (en = '1') then >> data <= ROM(conv_integer(addr)); >> end if; >> end if; >> end process; >> END ARCHITECTURE blkram_ROM; >> >> As far as I know, I think it is because I have not used the Block_ram >> attribute in the code..but i've seen a couple of code examples in the >> newsgroup and on the internet and no where have i come accross such an >> attribute for inferriing a ROM out of Block RAMs. > > > I don't think there's anything wrong with your template for inferring > the rom in block ram. I don't even think you will require the > attributes you added, though I doubt they hurt. I think the problem is > simply that the rom contents you specified are all zero, therefore the > synthesizer optimises all this logic to a constant and removes it. > > >> Second question: >> Ive seen two major methods when inferring memory. One of them talks >> about using library primitives in which there is no definition for the >> architecture of the memory (or may be it is defined somewhere else)..It >> directly instantiates a component for ex. a library primitive for >> inferring a ROM which has a data bus which is 1 bit wide and has a 16 >> bit long word is called ROM16X1 >> (http://toolbox.xilinx.com/docsan/xilinx8/books/data/docs/lib/lib0363_...). >> >> Does it mean that if I instantiate a component using this library >> primitive then I dont need to worry about the internal architecture >> right? Just use it directly and all works fine and gets synthesized all >> right..isnt it? >> Additionally some of them are called macros whereas some of them are >> called primitives..could some one please shed some light into this. >> (heres the xilinx link abt memory elements : >> http://toolbox.xilinx.com/docsan/xilinx8/books/data/docs/lib/lib0039_... >> ) >> >> The second one is directly writing HDL code which is more of a >> behavioral description of what the memory does.. >> >> Whats the difference between the two methods? Additionally do these >> methods work with synthesis tools.. > > > Both methods work fine. Using RAM inferred from HDL is my preferred > solution when ever possible. Doing so leads to faster simulation and > generic code that applies equally to various different FPGAs (both in > terms of vendors and families). > > On the other hand you cannot always infer a RAM which covers all the > many features of, say, a Xilinx a block RAM from HDL code so on occasion > it is necessary to get down and dirty and instantiate them yourself. > > >> I've even heard that one has to do different kinds of memory >> initialisations when simulating and when synthesizing.. >> Like it would be different when i wanna simulate the behavior using >> modelsim and when Im synthesizing it. > > > I cant say I have ever needed the feature, but that may well be the > case. The libraries guide should tell you all you need to know. > It used to be that simulators required ROM content as generics, & the synthesiser (XST, anyway) needed the same data as attributes. I believe (haven't tried) that the latest XST can read the data from an external file, using standard VHDL statements which any simulator will accept. (Of course, 3rd-party synthesisers probably can't do this: reading a file is generally not synthesisable). I had a project some time back that ran into this: it was a royal PITA. I ended up writing a perl script to generate code for this & several other artifacts (PLA's, etc.)Article: 110831
I think it depends on what you want... The Picoblaze is a very small 8-bit microcontroller while the NIOS is a 32-bit general purpose CPU (by most accounts). Both Altera and Xilinx provide an easy way to build a base-system using any of their processors (NIOS and/or Microblaze) however there is no base system builder for Picoblazes, so getting output from the processor into the real-world may be harder (unless you like looking at LEDs, and trying to hook up a UART to a picoblaze). Additionally, NIOS and Microblaze come with quite a few software libraries that you can use to your advantage. What exactly are you planning on doing with your system? Do you really need an FPGA or could you just buy a gumstix? The reason I ask is that the toolsets from both Xilinx and Altera have a learning curve, and it may be easier to bypass the need to build a base system, synthesize, place-and-route, etc. etc. -Jason University of Kansas. Mark McDougall wrote: > Chris wrote: > > > I would be curious to know any of your experiences with SOPC/Nios-II. I > > have very limited R&D time for this project. > > I guess it depends on *what* you want to interface to the NIOS. > > Avalon is compatible with Wishbone, so if you're going to be interfacing > wishbone components then it's a no-brainer. Otherwise, it's no more > difficult than writing wishbone wrappers for your non-wishbone component. > > Of course some components already exist, such as an SDRAM controller for > example. You also get I/O blocks such as registers and GPIO that can > have associated NIOS interrupts, UARTS, etc. > > Putting it all together is quite straight-forward in the SOPC interface. > You get a visual representation of the bus interconnects and can massage > the memory map as you see fit. Arbitration for multiple bus-masters is > automagically taken care of. You also get to choose the size/complexity > of the NIOS itself - IIRC the smallest is 600-700 LEs?!? > > Once you've decided on your architecture, you 'generate' the system > which produces a mass of HDL files in your main project directory. Then > instantiate the top level in your Quartus design and you're good to go. > > The software is written from within the NIOS-II IDE. You simply build a > 'system library' for your design and then start on your application. > Personally I hate Eclipse with a passion so I do all my editing outside > the IDE, and use it solely for the big red 'RUN' button. > > uCOS is also an option, or you can go bare-bones with the HAL library. > You get drivers for all system components and isr hooks etc. If you > actually already know what you're looking for, you can usually find it > in the doco! ;) > > There's also nice things like a JTAG UART which allows you to spit debug > messages directly to the IDE console. During development you can target > your CODE sections to (SD)RAM and download/run everything via JTAG so > there's no need for ROM emulators etc. I haven't used the debugger > extensively, but it kinda works. > > Overall, it's relatively "painless" once you get the hang of things. > That certainly can't be said for a lot of embedded systems, let-alone > soft-cores running in FPGAs.... > > I can't comment on Xilinx/PicoBlaze... > > Regards, > > -- > Mark McDougall, Engineer > Virtual Logic Pty Ltd, <http://www.vl.com.au> > 21-25 King St, Rockdale, 2216 > Ph: +612-9599-3255 Fax: +612-9599-3266Article: 110832
On 23 Oct 2006 16:39:30 -0700, "Skyrunner" <dom.hewett@gmail.com> wrote: The Windriver6 "Installer exit code=1" followed by "Success" is suspicious, especially repeated for each port. It looks like a failure to install Windriver; can you check this instllation outside Impact? >I did intend to get the Parallel IV cable but I couldn't get one with >my development board order (so I am using the bundled 3) and they seem >to be quite hard to source in the UK. Available from the online store at www.xilinx.com, and they do ship to the UK. Check if currently in stock... I try to work with UK distributors, but when they quote a 6 week leadtime for something ex-stock (or even a software download, and I'm not kidding!) it's VERY good to have that option. - BrianArticle: 110833
> I was pretty confident about the layout but the ripple on > my supply voltages is +- 100mV (on 2.5V and 1.5V) ... > I guess that might be too much for 300 MHz operation? all the beginner's problems ... with a differential probe the ripple is just +-20 mV bye, MichaelArticle: 110834
Brad Smallridge wrote: > How do you set up a differential DDR output clock? > > In the Spartans there was a DDR register where you > would tie one data to 1 and the other to 0 at the > output pin flipflop. > > The Virtex4 has OSERDES modules, do I use them? Well, you "could" but, the old spartan method works fine. You can also use only one output DDR flip flop connected to a OBUFDS that will output a differential signal on two pins. SylvainArticle: 110835
My system has arrived and I did a quick benchmark: my lab-system: P4, 2.6 GHz, 2GBytes RAM another system: P4, 3 GHz, 2GBytes RAM my new machine: Core 2 Duo, E6700, 2GBytes RAM with Asus P5LD2 Deluxe a full run with ISE 6.3 (from synthesize to bitgen) with a recent design takes: my lab-system: 30 minutes another system: 28 minutes my new machine: 14 minutes I would say it is worth the money and I guess we'll buy some more of those machines ... bye, MichaelArticle: 110836
On Oct 21, 1:41 pm, PeteS <peter.smith8...@ntlworld.com> wrote: <snip> >Another very simple option is to use DOS2UNIX / UNIX2DOS and post process the file. I agree. Curious, have you ever used the program "conv" instead? It is part of the Cygwin toolset on XP. It automagically detects the current format and changes it to the other. PeteArticle: 110837
Sylvain Munaut <SomeOne@SomeDomain.com> schrieb: > Brad Smallridge wrote: > > How do you set up a differential DDR output clock? > > > > In the Spartans there was a DDR register where you > > would tie one data to 1 and the other to 0 at the > > output pin flipflop. > > > > The Virtex4 has OSERDES modules, do I use them? > > Well, you "could" but, the old spartan method works fine. > You can also use only one output DDR flip flop connected to a OBUFDS > that will output a differential signal on two pins. > > Sylvain Sylvain what you wrote is an 'uups' ? most DDR memory do not use differential signalling? Antti http://groups.google.com/group/virtex5Article: 110838
Hi all, I'm working on a Virtex-4 FX12LC Design with PPC405 Core, SDRAM and Multiport Memory Controller 2 (MPMC2 release 2006/08/31). The Memec Development Board contains the Infineon DDR SDRAM HYB25D512160BC-6 (64 Mbyte, Databus 16 bit). I started the Design with BSB and OPB_DDR_CNTLR, then replaced the DDR_CNTLR with the MPMC2 Core of from "ml403_ddr_p_100mhz" and changed the Memory Width to 16 bit, Pin Constraints etc. The MPMC2 is configured to hold only one PLB connection, the remaining 7 ports are set to "None". After the project was built, I tried to access the SDRAM Memory via a simple C Application or XMD. The problem now is, that the memory content seems to be mirrored every 32 bit. For example, when I write at address 0x00000000 a 32 bit value 0xA5A5A5A5, the same value appears at address 0x00000008. The same behavior between addresses 0x00000004 and 0x0000000C. It looks like: 0x00000000: 0xA5A5A5A5 0x00000000 0xA5A5A5A5 0x00000000 0x00000010: 0x00000000 0xDEADBEEF 0x00000000 0xDEADBEEF 0x00000020: 0x00001111 0x00002222 0x00001111 0x00002222 0x00000030: 0x00000000 0x00000000 0x00000000 0x00000000 The MPMC Part in system.mhs: BEGIN mpmc2_ddr_p_100mhz_x16_hyb25d512160bc_6 PARAMETER INSTANCE = mpmc2_ddr_p_100mhz_x16_hyb25d512160bc_6_0 PARAMETER HW_VER = 1.04.a PARAMETER C_PLB_0_BASEADDR = 0x0000_0000 PARAMETER C_PLB_0_HIGHADDR = 0x03ff_ffff PARAMETER C_PLB_0_PLB_NUM_MASTERS = 2 PARAMETER C_PLB_0_PLB_MID_WIDTH = 1 PARAMETER C_PLB_0_PI_TO_MPMC2_CLK_RATIO = 1 PARAMETER C_PLB_0_MPMC2_TO_PI_CLK_RATIO = 1 PARAMETER C_PLB_0_BRIDGE_TO_PI_CLK_RATIO = 1 BUS_INTERFACE PLB_S_0 = plb PORT MPMC2_0_Rst = sys_bus_reset PORT PLB_0_PLB_SlClk = CLK_100MHz PORT MPMC2_0_Clk0_2X = net_gnd PORT MPMC2_Slowest_Clk = CLK_100MHz PORT MPMC2_0_Clk0 = CLK_100MHz PORT MPMC2_0_Clk90 = CLK_100MHz_90 PORT MPMC2_0_Clk_Cal = CLK_100MHz PORT MPMC2_0_Clk_200MHz = CLK_200MHz PORT MPMC2_0_Clk_Mem = CLK_100MHz_90 PORT MPMC2_0_DDR_Clk_O = DDR_Clk PORT MPMC2_0_DDR_Clk_n_O = DDR_Clkn PORT MPMC2_0_DDR_CE_O = DDR_CKE PORT MPMC2_0_DDR_BankAddr_O = DDR_BA PORT MPMC2_0_DDR_Addr_O = DDR_Addr PORT MPMC2_0_DDR_CS_n_O = DDR_CSn PORT MPMC2_0_DDR_RAS_n_O = DDR_RASn PORT MPMC2_0_DDR_CAS_n_O = DDR_CASn PORT MPMC2_0_DDR_WE_n_O = DDR_WEn PORT MPMC2_0_DDR_DQ = DDR_DQ PORT MPMC2_0_DDR_DQS = DDR_DQS PORT MPMC2_0_DDR_DM = DDR_DM END The MPMC parameters are equal to the reference design "v4fx12lc_ddr_idpp_100mhz", except the parameters which setup the number of master/slaves, and of course the datawidth of memory. I checked the pin constraints, they are ok. So where could be the mistake? Are there any MPMC Parameters which I forgot to set correctly? Do I need to modify PLB Settings? Are there any suggestions or hints? Thanks in advance. MackArticle: 110839
Hi all, I'm evaluating the porting of uclinux on microblaze. now I'm performing a ping between a laptop PC and microblaze and what I can see is that the averange delay is about 6.8ms... that is a lot of time !.... with a point to point connection I'm expecting less then 1 msec.! 64 bytes from 10.0.0.1: icmp_seq=475 ttl=128 time=6.9 ms 64 bytes from 10.0.0.1: icmp_seq=476 ttl=128 time=6.8 ms 64 bytes from 10.0.0.1: icmp_seq=477 ttl=128 time=6.6 ms 64 bytes from 10.0.0.1: icmp_seq=478 ttl=128 time=6.3 ms 64 bytes from 10.0.0.1: icmp_seq=479 ttl=128 time=6.9 ms Does anybody has better performance? Thanks in advance, FrancescoArticle: 110840
is that a known bug ? ISE 8.2 / win XP seems to freeze while synthesing design (no more mouse or menu/button action event response... looks like a threading bug) at the end of computation, it comes back to normal execution.Article: 110841
Antti wrote: > Sylvain Munaut <SomeOne@SomeDomain.com> schrieb: > > > Brad Smallridge wrote: > > > How do you set up a differential DDR output clock? > > > > > > In the Spartans there was a DDR register where you > > > would tie one data to 1 and the other to 0 at the > > > output pin flipflop. > > > > > > The Virtex4 has OSERDES modules, do I use them? > > > > Well, you "could" but, the old spartan method works fine. > > You can also use only one output DDR flip flop connected to a OBUFDS > > that will output a differential signal on two pins. > > > > Sylvain > Sylvain > > what you wrote is an 'uups' ? > > most DDR memory do not use differential signalling? The OP question was "How do you set up a differential DDR output clock?" So I guessed what he wanted to do is send the clock from the FPGA to the DDR, using the internal clock driving a DDR IOB flip flop. And most DDR chips have a differential clock, so either you use two DDR flip flops with inverted inputs, or a single one and a differential iob driver. SylvainArticle: 110842
Brad Smallridge wrote:
> How do you set up a differential DDR output clock?
Here's a Verilog implementation to output my PClk (Virtex 4):
ODDR pclkff(.Q(PClkO), .C(PClk), .CE(1'b1), .D1(1'b1), .D2(1'b0),
.R(1'b0), .S(1'b0));
OBUFDS pclk0 (.O(PClkOP), .OB(PClkON), .I(PClkO));
I assign the IO attributes in the .ucf
---
Joe Samson
Pixel Velocity
Article: 110843Hi all, I have done a project in which FPGA implementation is done.I have used Xilinx7.1i FPGA tool. I have written code in Verilog. So,I just wanted to know the type of questions that can be asked in interviews on FPGA's. Is the knowledge of VIRTEX II architecture enough? What type of questions could be asked on the synthesis report? What are the things I should be thorough enough to answer? May be this kind of questions should not be posted in this forum. I'm sorry for that. But please help me regarding this. Hoping for the positive response. Thanks a lot in advance. Regards, RaghuArticle: 110844
Francesco wrote:
>...
> 64 bytes from 10.0.0.1: icmp_seq=479 ttl=128 time=6.9 ms
>
> Does anybody has better performance?
> ...
Sorry I not tried but I would like to buy the same board (I sow in
other post you are using an ml403) and play with the ethernet...
If your laptop is linux... you can try
ping -f 10.0.0.1
and after a while if you interrupt (Ctrl-c) you can see some other
statistics.
If your screen fill with dots during the ping then there are very poor
performances and/or some cable problem and/or some negotiation
problem....
Sandro
Article: 110845Is it just me, or are we having a sense of deja vu? Cheers PeteSArticle: 110846
I've written Verilog for over 10 years and the design for the logic portion is already done. However this is the first time using a soft core CPU. Basically this is a backplane bus interface. Address decode and 32 bit porting. But I need RAM for a fast buffer and also a little CPU for converting serial I2C DACs and ADCs into parallel data. So a little embedded CPU with I2C core would probably do it. Perhaps SPI so I can update calibration constants in config Flash. PicoBlaze seems very easy to hook your own logic to. Nios seems much more involved since you have to go through the SOPC arch. It also appears the size of the gates will be 2X higher using Nios than PicoBlaze. The chip size could be twice the price. Chris. "Jason Agron" <jagron@gmail.com> wrote in message news:1161684703.158078.90950@f16g2000cwb.googlegroups.com... > I think it depends on what you want... > > The Picoblaze is a very small 8-bit microcontroller while the NIOS is a > 32-bit general purpose CPU (by most accounts). Both Altera and Xilinx > provide an easy way to build a base-system using any of their > processors (NIOS and/or Microblaze) however there is no base system > builder for Picoblazes, so getting output from the processor into the > real-world may be harder (unless you like looking at LEDs, and trying > to hook up a UART to a picoblaze). > > Additionally, NIOS and Microblaze come with quite a few software > libraries that you can use to your advantage. What exactly are you > planning on doing with your system? Do you really need an FPGA or > could you just buy a gumstix? The reason I ask is that the toolsets > from both Xilinx and Altera have a learning curve, and it may be easier > to bypass the need to build a base system, synthesize, place-and-route, > etc. etc. > > -Jason > University of Kansas. > > > Mark McDougall wrote: > > Chris wrote: > > > > > I would be curious to know any of your experiences with SOPC/Nios-II. I > > > have very limited R&D time for this project. > > > > I guess it depends on *what* you want to interface to the NIOS. > > > > Avalon is compatible with Wishbone, so if you're going to be interfacing > > wishbone components then it's a no-brainer. Otherwise, it's no more > > difficult than writing wishbone wrappers for your non-wishbone component. > > > > Of course some components already exist, such as an SDRAM controller for > > example. You also get I/O blocks such as registers and GPIO that can > > have associated NIOS interrupts, UARTS, etc. > > > > Putting it all together is quite straight-forward in the SOPC interface. > > You get a visual representation of the bus interconnects and can massage > > the memory map as you see fit. Arbitration for multiple bus-masters is > > automagically taken care of. You also get to choose the size/complexity > > of the NIOS itself - IIRC the smallest is 600-700 LEs?!? > > > > Once you've decided on your architecture, you 'generate' the system > > which produces a mass of HDL files in your main project directory. Then > > instantiate the top level in your Quartus design and you're good to go. > > > > The software is written from within the NIOS-II IDE. You simply build a > > 'system library' for your design and then start on your application. > > Personally I hate Eclipse with a passion so I do all my editing outside > > the IDE, and use it solely for the big red 'RUN' button. > > > > uCOS is also an option, or you can go bare-bones with the HAL library. > > You get drivers for all system components and isr hooks etc. If you > > actually already know what you're looking for, you can usually find it > > in the doco! ;) > > > > There's also nice things like a JTAG UART which allows you to spit debug > > messages directly to the IDE console. During development you can target > > your CODE sections to (SD)RAM and download/run everything via JTAG so > > there's no need for ROM emulators etc. I haven't used the debugger > > extensively, but it kinda works. > > > > Overall, it's relatively "painless" once you get the hang of things. > > That certainly can't be said for a lot of embedded systems, let-alone > > soft-cores running in FPGAs.... > > > > I can't comment on Xilinx/PicoBlaze... > > > > Regards, > > > > -- > > Mark McDougall, Engineer > > Virtual Logic Pty Ltd, <http://www.vl.com.au> > > 21-25 King St, Rockdale, 2216 > > Ph: +612-9599-3255 Fax: +612-9599-3266 >Article: 110847
> Well, you "could" but, the old spartan method works fine. > You can also use only one output DDR flip flop connected to a OBUFDS > that will output a differential signal on two pins. I guess my confusion is that when you go to the FPGA Editor one sees an OSERDES box near the output pin and not the set of registers you see in a Spartan. This is a differential output for an xclk Camera Link interface, if that matters. Not a memory device. Brad Smallridge aivisionArticle: 110848
Just a thought - I remember having to play with the EPP ECP port configuration in the BIOS to get the cable to work properly. Maybe that was just for the high-speed though... Ben "Brian Drummond" <brian_drummond@btconnect.com> wrote in message news:jirrj2hao92ekqvju3l635544dq8lofibm@4ax.com... > On 23 Oct 2006 16:39:30 -0700, "Skyrunner" <dom.hewett@gmail.com> wrote: > > The Windriver6 "Installer exit code=1" followed by "Success" is > suspicious, especially repeated for each port. It looks like a failure > to install Windriver; can you check this instllation outside Impact? > >>I did intend to get the Parallel IV cable but I couldn't get one with >>my development board order (so I am using the bundled 3) and they seem >>to be quite hard to source in the UK. > > Available from the online store at www.xilinx.com, and they do ship to > the UK. Check if currently in stock... > > I try to work with UK distributors, but when they quote a 6 week > leadtime for something ex-stock (or even a software download, and I'm > not kidding!) it's VERY good to have that option. > > - Brian >Article: 110849
Sylvain Munaut <SomeOne@SomeDomain.com> schrieb: > Antti wrote: > > Sylvain Munaut <SomeOne@SomeDomain.com> schrieb: > > > > > Brad Smallridge wrote: > > > > How do you set up a differential DDR output clock? > > > > > > > > In the Spartans there was a DDR register where you > > > > would tie one data to 1 and the other to 0 at the > > > > output pin flipflop. > > > > > > > > The Virtex4 has OSERDES modules, do I use them? > > > > > > Well, you "could" but, the old spartan method works fine. > > > You can also use only one output DDR flip flop connected to a OBUFDS > > > that will output a differential signal on two pins. > > > > > > Sylvain > > Sylvain > > > > what you wrote is an 'uups' ? > > > > most DDR memory do not use differential signalling? > > The OP question was "How do you set up a differential DDR output > clock?" > So I guessed what he wanted to do is send the clock from the FPGA to > the DDR, > using the internal clock driving a DDR IOB flip flop. > > And most DDR chips have a differential clock, so either you use two DDR > flip flops > with inverted inputs, or a single one and a differential iob driver. > > > Sylvain uups I need a vaccation. clk pins are different story, I missed that in oringal post Antti
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