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Not written for the S3E starter kit but might be useful is our EDK lab here http://www.enterpoint.co.uk/techitips/techitips.html. John Adair Enterpoint Ltd. Antti wrote: > jrbattin@gmail.com wrote: > > Hello, > > > > I've recently acquired a Spartan-3E Starter Kit (RevD) and am new to > > the world of FPGAs and logic design. I've been experimenting with EDK > > trying to get a test design working on my board when I ran into a > > problem. I can use the wizard to create a simple MicroBlaze design > > with a small amount of cache and a DDR SDRAM memory controller that > > builds and downloads to the device without a problem. > > > > However, when I attempt to run the either the memory or peripheral test > > applications, built in the TestApp_(name) folders, the debugger > > reports a pipeline stall. The memory testapp reports the stall when > > the PC is at 0x000004bc. I investigated the contents of this address > > and its the LWI opcode. The peripheral test stalls at 0x22000000, > > which contains a zero. > > get some working reference design and proceed from there > the wizard generated systems dont always work > > you find some designs at xilinx website > and www.petalogix.com > has an uclinux ready MB system design for the se3sk board > > Antti > http://groups.google.com/group/virtex5Article: 110776
John Adair wrote: > Not written for the S3E starter kit but might be useful is our EDK lab > here http://www.enterpoint.co.uk/techitips/techitips.html. > > John Adair > Enterpoint Ltd. the OP had issues with DDR RAM, I dont see any help for that issue at your pages, or do you? Antti http://groups.google.com/group/virtex5Article: 110777
Hello, I came accross what I think is a bug in virtex4 debug bitstream generation. In this mode, the two pad frames (82 bytes) which are needed at the end of each row configuration are written *after* the LOUT write of the FAR, while they are expected to take place in the previous FDRI write. I don't know if this really is a bug or some specific quirk in virtex4 bitstream handling -- I don't have a virtex4 at hand, so I cannot really test whether the hardware is happy with this or not. JBArticle: 110778
I would have a peek at the MachXO (Lattice) www.latticesemi.com It's an FPGA CPLD crossover, and it's around 90 eur. It's a small board with LED's, Switches, and a small prototyping area. Martin. "samiam" <samiamSPAMTHIS@spamalert.com> wrote in message news:vHsZg.77479$p86.25317@fe05.news.easynews.com... > Figured this was the place to ask (comp.arch.embedded or comp.arch.fpga) > > Whats the cheapest board to study VHDL on? > > Ideally Id like an FPGA based board with a few inputs (dip > switches,toggles?), some outputs (parallel or serial connector, some > leds) < $100 > > I am looking on ebay now, and I see one or two boards well above $100. > Any suggestions? > > Thanks in advanceArticle: 110779
Hi Francesco, Francesco wrote: > Hi I'm trying to porting uclinux using microblaze 4.0. > When I try to run the OS I've got the following error message. > > Kernel panic: VFS: Unable to mount root fs on 1f:00 How are you booting your system? The most common cause of this error is trying to use XMD to download the image.elf file, instead of the image.bin file. Instead of XMD> dow images/image.elf you should do XMD> dow -data images/image.bin 0xdeadbeef XMD> con 0xdeadbeef (where 0xDEADBEEF is the memory start address) For various reasons, XMD does not download the .romfs segment when you do the ELF download - you must download the binary image.bin instead. Regards, JohnArticle: 110780
Subject says it all really. I'd like to erase a number of EMP7064SLC44's that have been programmed with JTAG disabled. Anyone have the 'secret formula' or the special programmer equipment that can do it ?Article: 110781
Jaime Andrés Aranguren Cardona wrote: > Hi, > > I installed XPS - EDK 8.1i in my WinXP machine. When I try to call XPS > the DPS window appears, and dissapears within a few seconds and nothing > else happens. Reviewing the C:\EDK folder, a file bash.exe.stackdump > appears, which contents are: > > Exception: STATUS_ACCESS_VIOLATION at eip=00000000 > eax=00000000 ebx=0247ED28 ecx=0247EB64 edx=7C91EB94 esi=0247ED2C > edi=00000000 > ebp=0247ED30 esp=0247ED08 program=C:\EDK\cygwin\bin\bash.exe, pid 1680, > thread main > cs=001B ds=0023 es=0023 fs=003B gs=0000 ss=0023 > Stack trace: > Frame Function Args > End of stack trace > > How could I fix this? > > Regards. > Did you also installed ISE 8.1?! ISE and EDK must have the same version numbers. FrankArticle: 110782
Al wrote: > I found some free servers which keep some months of posts, is there > anyone who knows some others which give better access? > Thanks a lot I use them: http://news.individual.net/ Not free, but they charge only 10EUR/year, which is very affordable and the service is well worth it. Payment is via Firstgate Click&Buy, not sure if that's available in Switzerland you'd have to check. cu, SeanArticle: 110783
I know that memory address for OPB_DDR is not generated properly for rev D board. Rev D board has 64MB of DDR, but the address is set to 32MB (as for rev C)! Edit manually the system.mhs at opb_ddr, for example: PARAMETER C_MEM0_BASEADDR = 0x22000000 PARAMETER C_MEM0_HIGHADDR = 0x23ffffff I don't know if this is your problem, but it is definatelly an error produced by BSB. Cheers, Guru jrbattin@gmail.com wrote: > Hello, > > I've recently acquired a Spartan-3E Starter Kit (RevD) and am new to > the world of FPGAs and logic design. I've been experimenting with EDK > trying to get a test design working on my board when I ran into a > problem. I can use the wizard to create a simple MicroBlaze design > with a small amount of cache and a DDR SDRAM memory controller that > builds and downloads to the device without a problem. > > However, when I attempt to run the either the memory or peripheral test > applications, built in the TestApp_(name) folders, the debugger > reports a pipeline stall. The memory testapp reports the stall when > the PC is at 0x000004bc. I investigated the contents of this address > and its the LWI opcode. The peripheral test stalls at 0x22000000, > which contains a zero. > > Pastebin link to memory test: http://pastebin.com/810943 > > My question is: should I be concerned at all that my wizard-create > microblaze configuration isn't working? I have a feeling its not a > drop-in and go type of deal, and I need to modify the HDL, but the fact > that everything worked fine until the design actually ran real software > has me a bit paranoid that perhaps my board is defective somehow. > > I am really just looking for something that would let me test out the > board's capabilities, so if anyone wants to point me in the right > direction it would be much appreciated.Article: 110784
Sorry this is not the right: > PARAMETER C_MEM0_BASEADDR = 0x22000000 > PARAMETER C_MEM0_HIGHADDR = 0x23ffffff This are the original settings. Do it like: > PARAMETER C_MEM0_BASEADDR = 0x00000000 > PARAMETER C_MEM0_HIGHADDR = 0x03FFFFFF Cheers, GuruArticle: 110785
Thank you John, yes I'm downloading the image.bin file with XMD dow -data image.bin 0x24000000 con 0x24000000 I'm using the ml403 and I've got ISE 8.1. I'm happy that I have "only" this problem.... The kernel is running and the only problem I've got is to mount the root.... I will try to insert some debbugging code to see why I can't mount the VFS on the RAM. Thanks, Francesco John Williams wrote: > Hi Francesco, > > Francesco wrote: > > > Hi I'm trying to porting uclinux using microblaze 4.0. > > When I try to run the OS I've got the following error message. > > > > Kernel panic: VFS: Unable to mount root fs on 1f:00 > > How are you booting your system? The most common cause of this error is trying > to use XMD to download the image.elf file, instead of the image.bin file. > > Instead of > > XMD> dow images/image.elf > > you should do > > XMD> dow -data images/image.bin 0xdeadbeef > XMD> con 0xdeadbeef > > (where 0xDEADBEEF is the memory start address) > > For various reasons, XMD does not download the .romfs segment when you do the > ELF download - you must download the binary image.bin instead. > > Regards, > > JohnArticle: 110786
Thanks Scott. I'm usimg the ml403 (ISE8.1) your link is very interesting. I just started to debbug the kernel. If I'll make any progress I'll send you an email. Do you use xconfig to menuconfig to build the kernel? I'm using xconfig... it should make any difference, but I have a friend with experience in Linux and he suggested to use menuconfig. I also read that people has fixed this problem using microblaze 3.0 (I'm using microblaze 4.0) But I do not think this is the "real" problem, because the kernel is running... what I need to do is "only" mount the root in the RAM. Maybe using microblaze 3.0 we "mask" the problem... some setting will be different and this errod does not happen...I want to go in deep and fix it properly and then "share" my results with you. Francesco. ScottNortman wrote: > I had the same problem... what FPGA are you using? I am using the > spartan 3e starter kit. > > I spent some time looking around the web and I found a site which > explains how to append the "root=" command properly; here is a link: > > http://www.ucdot.org/article.pl?sid=03/01/11/1049210&mode=thread > > However, even though I followed the instructions, I still got a new > error: > > ********* location > VFS test name = </dev/root> > Micr > VFS fs_name = <ext2>ash probe(0x21000000 > > VFS fs_name = <romfs> 21000000 > VFS root name <1f:01> > ********* > arena open of 1 failed!evice at location zero > > VFS: tried fs_name = <ext2> err = -19 > > > > Hope this helps; if you make any progress please let me know. > > Thanks, > Scott Nortman > > > David Ashley wrote: > > Francesco wrote: > > > Hi I'm trying to porting uclinux using microblaze 4.0. > > > When I try to run the OS I've got the following error message. > > > > > > Kernel panic: VFS: Unable to mount root fs on 1f:00 > > > > > > Does anybody had a similar problem? > > > > > > Thanks in advance, > > > Francesco > > > > > > > Linux is up but it can't mount the root > > partition. What is your kernel command line? > > What is the "root=xxx" specifically. That device > > number 1f:00 seems screwy. It's not listed in > > include/linux/major.h. > > > > -Dave > > > > -- > > David Ashley http://www.xdr.com/dash > > Embedded linux, device drivers, system architectureArticle: 110787
I'm trying to configure a Spartan 3 via Slave Serial mode at power up. I'm storing the configuration file in SPI Flash and using a uP to read the Flash and send the configuration bit stream (and clock) to the FPGA. (I've considered using the FPGA Master Serial mode to clock the SPI Flash, and just using the uP to initiate the flash read instruction, but the hardware is not currently configured that way, so I want to get it working in the Slave Serial mode first on my current hardware.) I've read Xapp 502 but it still leaves me confused on a couple of points. 1. The app note says a .bit file contains header info that should not be downloaded to the FPGA, so I'm trying to use a .bin file. However, I thought the header information allowed the clock rate to be increased in the Master Serial mode. Does the .bin file also include that information? (If I try to use Master Serial mode later.) 2. When I serialize the .bin file bytes into a bit stream, do I load the bits from each byte MSB or LSB first into the FPGA? 3. When I finish loading the entire .bin file I wait for DONE to go high, and while waiting test if INIT is low (which indicates a CRC error). So far I never get a DONE high or an INIT low. Seems like I should get one or the other? Configuration works fine using Platform Cable USB (JTAG). M0,M1,M2 are configured correctly in Slave Serial mode. Thanks for answers/suggestions.Article: 110788
greg@accupel.com.nospam schrieb: > I'm trying to configure a Spartan 3 via Slave Serial mode at power up. > I'm storing the configuration file in SPI Flash and using a uP to read > the Flash and send the configuration bit stream (and clock) to the FPGA. > (I've considered using the FPGA Master Serial mode to clock the SPI > Flash, and just using the uP to initiate the flash read instruction, but > the hardware is not currently configured that way, so I want to get it > working in the Slave Serial mode first on my current hardware.) > > I've read Xapp 502 but it still leaves me confused on a couple of points. > > 1. The app note says a .bit file contains header info that should not be > downloaded to the FPGA, so I'm trying to use a .bin file. However, I > thought the header information allowed the clock rate to be increased in > the Master Serial mode. Does the .bin file also include that > information? (If I try to use Master Serial mode later.) > > 2. When I serialize the .bin file bytes into a bit stream, do I load > the bits from each byte MSB or LSB first into the FPGA? > > 3. When I finish loading the entire .bin file I wait for DONE to go > high, and while waiting test if INIT is low (which indicates a CRC > error). So far I never get a DONE high or an INIT low. Seems like I > should get one or the other? Configuration works fine using Platform > Cable USB (JTAG). M0,M1,M2 are configured correctly in Slave Serial mode. > > Thanks for answers/suggestions. there is "File header" present in BIT file and BITstream header present in BIT and BIN (and other files) it actually doesnt care if you dont strip the FILE header, the simplest is usually just take the .BIT file, and: 1 send it as is to the DIN, DONE=1? you are lucky 2 reverse bits in BIT, send to DIN DONE=1, if not something is wrong one of 2 should work AnttiArticle: 110789
In article <1161605132.571315.149550@k70g2000cwa.googlegroups.com>, "Antti" <Antti.Lukats@xilant.com> wrote: > greg@accupel.com.nospam schrieb: > > > I'm trying to configure a Spartan 3 via Slave Serial mode at power up. > > I'm storing the configuration file in SPI Flash and using a uP to read > > the Flash and send the configuration bit stream (and clock) to the FPGA. > > (I've considered using the FPGA Master Serial mode to clock the SPI > > Flash, and just using the uP to initiate the flash read instruction, but > > the hardware is not currently configured that way, so I want to get it > > working in the Slave Serial mode first on my current hardware.) > > > > I've read Xapp 502 but it still leaves me confused on a couple of points. > > > > 1. The app note says a .bit file contains header info that should not be > > downloaded to the FPGA, so I'm trying to use a .bin file. However, I > > thought the header information allowed the clock rate to be increased in > > the Master Serial mode. Does the .bin file also include that > > information? (If I try to use Master Serial mode later.) > > > > 2. When I serialize the .bin file bytes into a bit stream, do I load > > the bits from each byte MSB or LSB first into the FPGA? > > > > 3. When I finish loading the entire .bin file I wait for DONE to go > > high, and while waiting test if INIT is low (which indicates a CRC > > error). So far I never get a DONE high or an INIT low. Seems like I > > should get one or the other? Configuration works fine using Platform > > Cable USB (JTAG). M0,M1,M2 are configured correctly in Slave Serial mode. > > > > Thanks for answers/suggestions. > > there is "File header" present in BIT file and > BITstream header present in BIT and BIN (and other files) > > it actually doesnt care if you dont strip the FILE header, > the simplest is usually just take the .BIT file, and: > > 1 send it as is to the DIN, DONE=1? you are lucky > 2 reverse bits in BIT, send to DIN DONE=1, if not something is wrong > > one of 2 should work > > Antti I don't understand what you are saying. Do you send the LSB first, or the MSB? GregArticle: 110790
fsdg...@spone.com schrieb: > In article <1161605132.571315.149550@k70g2000cwa.googlegroups.com>, > "Antti" <Antti.Lukats@xilant.com> wrote: > > > greg@accupel.com.nospam schrieb: > > > > > I'm trying to configure a Spartan 3 via Slave Serial mode at power up. > > > I'm storing the configuration file in SPI Flash and using a uP to read > > > the Flash and send the configuration bit stream (and clock) to the FPGA. > > > (I've considered using the FPGA Master Serial mode to clock the SPI > > > Flash, and just using the uP to initiate the flash read instruction, but > > > the hardware is not currently configured that way, so I want to get it > > > working in the Slave Serial mode first on my current hardware.) > > > > > > I've read Xapp 502 but it still leaves me confused on a couple of points. > > > > > > 1. The app note says a .bit file contains header info that should not be > > > downloaded to the FPGA, so I'm trying to use a .bin file. However, I > > > thought the header information allowed the clock rate to be increased in > > > the Master Serial mode. Does the .bin file also include that > > > information? (If I try to use Master Serial mode later.) > > > > > > 2. When I serialize the .bin file bytes into a bit stream, do I load > > > the bits from each byte MSB or LSB first into the FPGA? > > > > > > 3. When I finish loading the entire .bin file I wait for DONE to go > > > high, and while waiting test if INIT is low (which indicates a CRC > > > error). So far I never get a DONE high or an INIT low. Seems like I > > > should get one or the other? Configuration works fine using Platform > > > Cable USB (JTAG). M0,M1,M2 are configured correctly in Slave Serial mode. > > > > > > Thanks for answers/suggestions. > > > > there is "File header" present in BIT file and > > BITstream header present in BIT and BIN (and other files) > > > > it actually doesnt care if you dont strip the FILE header, > > the simplest is usually just take the .BIT file, and: > > > > 1 send it as is to the DIN, DONE=1? you are lucky > > 2 reverse bits in BIT, send to DIN DONE=1, if not something is wrong > > > > one of 2 should work > > > > Antti > > I don't understand what you are saying. Do you send the LSB first, or > the MSB? > > Greg I try first either LSB or MSB, and the the other one. so I dont have to figure out what is the right one, within 2 trial attempts it must work. its better approuch then selecting one of options and being sure its the correct one, then trying 23 times to figure out the bits need to be swapped. if you write mydesign.bit on SD card in original not swapped form, then read it back then the bit order is the same as it needed to push into FPGA, if you get your bits from some other media (SPI flash, something else) you may have to swap bits. Again simplest method is not try fogure out the correct one, but just try 2 times, with both swap and noswap. AnttiArticle: 110791
greg@accupel.com.nospam wrote: > I'm trying to configure a Spartan 3 via Slave Serial mode at power up. > I'm storing the configuration file in SPI Flash and using a uP to read > the Flash and send the configuration bit stream (and clock) to the FPGA. > (I've considered using the FPGA Master Serial mode to clock the SPI > Flash, and just using the uP to initiate the flash read instruction, but > the hardware is not currently configured that way, so I want to get it > working in the Slave Serial mode first on my current hardware.) > > I've read Xapp 502 but it still leaves me confused on a couple of points. > > 1. The app note says a .bit file contains header info that should not be > downloaded to the FPGA, so I'm trying to use a .bin file. However, I > thought the header information allowed the clock rate to be increased in > the Master Serial mode. Does the .bin file also include that > information? (If I try to use Master Serial mode later.) Yes, the header is included in the .bit. > > 2. When I serialize the .bin file bytes into a bit stream, do I load > the bits from each byte MSB or LSB first into the FPGA? send byte by byte with LSB first > > 3. When I finish loading the entire .bin file I wait for DONE to go > high, and while waiting test if INIT is low (which indicates a CRC > error). So far I never get a DONE high or an INIT low. Seems like I > should get one or the other? Configuration works fine using Platform > Cable USB (JTAG). M0,M1,M2 are configured correctly in Slave Serial mode. add more free CCLK edges until Done comes high ! > > Thanks for answers/suggestions. Regards, Laurent www.amontec.comArticle: 110792
Hi, I want to use the FSL bus to connect two microblazes together. Because I am not familiar with the FSL bus, I first added a peripheral core using the configure coprocessor wizzard, to instantiate a default paripheral, together with the FSL drivers. However, when I run the SW application it stalls when writing to the FSL bus. I don't get any response afterwards. First, I did not made any changes to the instantiation of the fsl bus. Later on, I changed the clock connections (later on, also in the fsl's mpd file). Unfortunately, none o these measurements made any difference. Is there anyone that can provide me an example design that successfully uses the FSL bus, together with the application software (or a stripped version)? I can not find any satisfying reference designs on the web, nor on the Xilinx site. All help would be welcome!! Thanks, GerdArticle: 110793
<greg@accupel.com.nospam> wrote in message news:greg-B7B360.03470823102006@nntp0.pdx.net... > 3. When I finish loading the entire .bin file I wait for DONE to go > high, and while waiting test if INIT is low (which indicates a CRC > error). So far I never get a DONE high or an INIT low. Seems like I > should get one or the other? Configuration works fine using Platform > Cable USB (JTAG). M0,M1,M2 are configured correctly in Slave Serial mode. Remember to clock some extra cycles to initiate the fpga..Article: 110794
Does anyone know is this big FPGA is still being used in production? Thank you!Article: 110795
Hi ... I've got a Virtex2P-30 (sg6) and I'm trying to use one of the PowerPC-cores at 300 MHz (in a system much like xapp640). The Processor runs at 300 MHz, PLB 100 MHz, OPB 50 MHz, our clock source is a low-jitter 100 MHz oscillator. Sometimes the system behaves wierd and it all looks like the processor crashes. Running the system at only 200 MHz (instead of 300) seems to solve all those problems ... but is this really the solution? or is the problem just hidden? what am I doing wrong? I think 300 MHz is still within the specs .. are there any issues at that speed? is the DCM placement critical at 300 MHz? The system is built with EDK/ISE 6.3 and our DCM has DLL_FREQUENCY_MODE = "LOW" and DFS_FREQUENCY_MODE = "HIGH" and meets all the constraints. thanks for any hints ... bye, MichaelArticle: 110796
Michael Schöberl wrote: > Hi ... > > I've got a Virtex2P-30 (sg6) and I'm trying to use one > of the PowerPC-cores at 300 MHz (in a system much like > xapp640). The Processor runs at 300 MHz, PLB 100 MHz, > OPB 50 MHz, our clock source is a low-jitter 100 MHz > oscillator. > > > Sometimes the system behaves wierd and it all looks > like the processor crashes. Running the system at > only 200 MHz (instead of 300) seems to solve all > those problems ... > > but is this really the solution? > or is the problem just hidden? > > what am I doing wrong? > I think 300 MHz is still within the specs .. > are there any issues at that speed? > is the DCM placement critical at 300 MHz? > > > The system is built with EDK/ISE 6.3 and our DCM has > DLL_FREQUENCY_MODE = "LOW" and DFS_FREQUENCY_MODE = "HIGH" > and meets all the constraints. > > > thanks for any hints ... > > > bye, > Michael Hi Michael, How about your PCB layout? Or your PDS? Got enough juice and decoupling caps? HTH,Syms.Article: 110797
Michael Sch=F6berl wrote: > Hi ... > > I've got a Virtex2P-30 (sg6) and I'm trying to use one > of the PowerPC-cores at 300 MHz (in a system much like > xapp640). The Processor runs at 300 MHz, PLB 100 MHz, > OPB 50 MHz, our clock source is a low-jitter 100 MHz > oscillator. > > > Sometimes the system behaves wierd and it all looks > like the processor crashes. Running the system at > only 200 MHz (instead of 300) seems to solve all > those problems ... > > but is this really the solution? > or is the problem just hidden? > > what am I doing wrong? > I think 300 MHz is still within the specs .. > are there any issues at that speed? > is the DCM placement critical at 300 MHz? > > > The system is built with EDK/ISE 6.3 and our DCM has > DLL_FREQUENCY_MODE =3D "LOW" and DFS_FREQUENCY_MODE =3D "HIGH" > and meets all the constraints. > > > thanks for any hints ... > > > bye, > Michael Hello Michael, Are you generating the clock with a DCM? I had a problem with a V4FX and EDK/ISE 8.1 that sounds related to yours. The timing analyzer will propagate your jitter constraints through a DCM, but does not account for the jitter introduced by the DCM, which at 300 MHz is not trivial. I worked around the issue by increasing the jitter spec on my clock, so that after it had been propagated through the DCM it accounted for both the jitter of my clock, and the jitter introduced by the DCM. Regards, John McCaskillArticle: 110798
Hi All, I have a project to get the image data by camera and want to convert them as grayscale information. The camera has Camera Link output. It can be connected directly to universal frame grabber. I am trying to replace the frame grabber by FPGA. Does somebody know or has information how to get camera link specification ? The document which I found mostly only dealed with the pin configuration and didn't tell how to obtain the image pixel. I plan to use DS90CR288A to convert from LVDS to parallel. After that I don't know what should I do with parallel signal. Thanks in advance, -ivanArticle: 110799
"ivan@gmail.com" <ivanlimansyah@gmail.com> wrote in message news:1161622951.384907.99930@m73g2000cwd.googlegroups.com... > Hi All, > > I have a project to get the image data by camera and want to convert > them as grayscale information. The camera has Camera Link output. It > can be connected directly to universal frame grabber. I am trying to > replace the frame grabber by FPGA. Does somebody know or has > information how to get camera link specification ? > > The document which I found mostly only dealed with the pin > configuration and didn't tell how to obtain the image pixel. I plan to > use DS90CR288A to convert from LVDS to parallel. After that I don't > know what should I do with parallel signal. > > > Thanks in advance, > > -ivan > The standard document is available from many camera manufacturers including: http://www.alacron.com/downloads/vncl98076xz/CameraLink20v113.pdf which tells you everything you need to know. Slurp
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