Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
> Moving the design to hardware I find a seemingly random > delay by comparing the output of an OSERDES to a > framing clock (CLKDIV) outputted by an ODDR. > > Only by outputting the CLKDIV signal by another OSERDES > did I find any synchonization between CLKDIV and the > data: > > cam_oserdes_xclk: cam_link_out_sdr_oserdes > port map( > clk => cam_clk_280, -- in > clkdiv => clkdiv, -- in > data => "1100011", -- in 7 bits > q => xclk ); -- out Brad I am also interested in this, as I am just completing a design using OSERDES in Virtex 4 right now - haven't fully simulated yet though. In your case, where is you clk coming from? Is it coming from a clock capable input pin, through IBUFDS and BUFIO (then BUFR to create clkdiv), or is it coming from an internal global clock (eg through a DCM?) The latter seems to be allowed but I can't see much documentation, so that may be the cause of the skew... Also, whenyou say "random delay", do you mean a random skew between the delay of several OSERDES (e.g. several pins on a fast parallel output bus), or that the delay varies from one hardware trial to the next, or just seems non-deterministic wrt the ODDR output? Not many answers so far I'm afraid, but I will post my own results soon if it is helpful. TomArticle: 112101
I never said that the IC manufacuterers don't _guarantee_ their specifications on every device they ship! But unless you are buying really simple ICs, and/or paying lots of extra $, every single device is not 100.000% _tested_ to meet every one of those specs. The vendor still guarantees that every device will meet every spec, and will replace a defective device for free. Xilinx and others do a fantastic job of testing as many of the specs, over as much of the device, as they can, but they (and we) cannot afford 100.000% testing over every spec on every device delivered. Austin even states this. So they use _statistics_ to cover the untested specifications/devices, to make sure that the probability that you will receive a bad device is acceptably small. This is not news, folks. I have never had an FPGA fail due to not meeting its specifications either. But I design in margin to make sure, again to a statistical level, that they don't fail. Andy PeteS wrote: > Austin Lesea wrote: > > John, > > > > I, too, have a problem with people making assumptions about our product > > quality. > > > > If you are interested, we do publish what our criteria are, and the > > probability that a part is a test escape of some sort, or fails upon > > first insertion, etc. is something we do document, and care deeply about. > > > > http://www.xilinx.com/products/quality/ > > > > Obviously, we strive like most companies for a '0 defect' goal, and like > > all companies, we somehow are unable to ship only perfect components > > (funny how the real world conspires against perfection). > > > > Since every bitstream is different for each application, and we don't > > know any of them, it makes assuring 100% perfection a daunting task, yet > > one that we willingly accept and strive towards. > > > > In fact, if you really want a component that is absolutely best tested > > for exactly your bitstream (design), then you should be using the > > EasyPath(tm) program, as that program has a customer program for the > > FPGA that exercises the paths and logic that you actually are going to > > depend on (based on your design). > > > > Austin > > In further defence of IC manufacturers and in particular FPGA vendors, I > have _never_ had a failure due to FPGA timing with Xilinx (and others) > parts except for my own failure to properly analyse the system. > > I have designed with others, but Quicklogic was 12 years ago and any > issues from then would be unfiar, to say the least. I've also used > Lattice and Altera parts and provided I used the tools properly, they > worked as expected as well. > > The key (as I note elsewhere) is that provided I get guaranteed > characteristics, (which I _do_ insist on, whatever they may be) I can > use them as part of an overall budget; and it is _my_ responsibility to > make sure I give the tools sufficient information to give me the > information I need, to say nothing of taking all external effects into > account. > > I wouldn't normally buy parts that are statistically characterised (AQL) > *unless* it's a mature part with a track record of not having issues on > the particular tests that are AQL only. > > Both the vendor and designer has responsibilities, and although I expect > quite a bit from the vendor, I am perfectly willing to assume my part of > those responsibilities. > > Cheers > > PeteSArticle: 112102
Without looking at a 8080 datasheet properly we may have a platform for you to play on if that is what you need. Craignell1/2/3 info and maybe even some pictures will be up our website next week, or possibly week after that if we get delayed. They are in manufacture currently. You may have to do a minor rewire using stripboard for the power pins as Craignell modules follow standard 5V DIL pinout for which I think the 8080 varies. Before anyone asks the module uses 5V as power I/P, pins are 5V tolerant, and it even has 5V pullups to make 5V CMOS levels to the outside world. It's designed as an obsolete component replacement but equally good for hobby or student electronic projects with 0.1 inch leg pitch. Standard offerings will have 100K gate Spartan-3E on-board but 250K and 500K gate varieties can also be made. John Adair Enterpoint Ltd. - Home of Craignell1/2/3. The DIL Spartan-3E Development Module. http://www.enterpoint.co.uk "logjam" <grant@stockly.com> wrote in message news:1163620507.857303.28820@m73g2000cwd.googlegroups.com... >I would like to eventually make an 8080 out of Field Solderable Gate > Arrays. ;) (trasistors) > > First, I want to design the whole thing in an FPGA for logic proofing > There will be a LOT of circuit boards required for this and I want to > limit failure... My idea was to create small macro blocks that emulate > standard TTL chips and use those TTL chips (or customized versions) to > build the processor. > > Any recomendations on how to proceed? I want to make the core I/O > compatible with the 8080, which means full status signal support and a > 2 phase clock. > > Thanks, > Grant > From Iwo.Mergler@soton.sc.philips.com Thu Nov 16 07:20:28 2006 Path: newsdbm05.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!news.linkpendium.com!news.linkpendium.com!newspeer1.nwr.nac.net!colt.net!news-lond.gip.net!news.gsl.net!gip.net!lon04-news-philips!53ab2750!not-for-mail Message-Id: <s6cu24-r7f.ln1@c2968.soton.sc.philips.com> From: Iwo Mergler <Iwo.Mergler@soton.sc.philips.com> Subject: Re: USB and AHB Newsgroups: comp.arch.fpga References: <1163633657.029718.142070@f16g2000cwb.googlegroups.com> Lines: 40 Organization: Not organised User-Agent: KNode/0.9.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Date: Thu, 16 Nov 2006 15:20:28 +0000 NNTP-Posting-Host: 161.85.127.140 X-Complaints-To: newsmaster@rain.fr X-Trace: lon04-news-philips 1163692154 161.85.127.140 (Thu, 16 Nov 2006 15:49:14 GMT) NNTP-Posting-Date: Thu, 16 Nov 2006 15:49:14 GMT Xref: prodigy.net comp.arch.fpga:123106 terabits wrote: > Hi > > I am very new to usb, I have some basic questions reagarding usb with > ahb . > > Suppose i have a ahb structure like 2 masters and 2 slaves. > i want to have 2usb devices .....will this usb (usb 2.0 device) sit on > the slave side ? Unless you want to implement a lot of buffer memory on the device, it's probably more useful to integrate a DMA controller into the USB block and run it as a AHB master. But otherwise, yes, it could be a AHB slave. > what will be on the master side ? suppose one dma as a master i have > will the another master be arm processor or can it be some other usb > device ? if so what could it be ? > why at all usb has to interface with ahb ? only to interact with > memories and arm processors ? Yes. There would be no point having the USB device, unless you can move data to and from it. > can you give me a real time example like take a usb pen drive where > will ahb comes into picture when i am connecting it to the computer ? USB pen drives are simpler devices and unlikely to use a ARM processor. A typical ARM-with-USB-device application would be a MP3 player, like the iPod. A software stack on the processor would then use the USB device to implement the mass storage protocol. Kind regards, IwoArticle: 112103
logjam wrote: > > Do you also want this voltage compatible ? > > What is the target of this project ? > > I want to be able to use it in place of a real 8080. I don't care > about the 12 and -5v power supply. The whole project is just for fun. > > The reason I thought TTL would be a good place to start is because of > the AMD 2901 9080 emulator book. Also, if standard TTL devices were > replicated using transistors then each "module" of the processor could > possibly be tested with an IC tester. > > I figure it will have a few thousand LEDs too. Like an LED for every > register, microcode bit, etc. I guess you can build an 8080 out of TTL logic blocks, but that will not be the way it was designed in the NMOS technology of the day. When I was in high school we were given an old (even for 1967) weather computer that did not use ICs. Each logic function; NAND gate, NOR gate, FF, etc; was made from transistors using RTL logic technology. But the main thing to consider was that it was made in modules about 2" square with edge pin connectors based on standard functions. If you are going to build your own 8080 from transistors, it is going to be large and you need to modularize it to make it practical. Other than very low level primatives such as AND/OR/FF, you might consider building large functions such as registers or perhaps even a 22V10 type module. It could be designed to provide the full functionality of a 22V10 with jumpers or even just solder bridges for programming. I'd be willing to bet you can make an 8080 out of just a few dozen 22V10 modules. With today's packaging technology, this could be smaller than the 2" square modules in the old weather computer my high school had. What will you be using for memory, diode arrays? The weather computer used a magnetic drum as its memory. Timing is everything! BTW, if you want to start a little smaller, you might consider the 8008. It had similar registers, but used an 8 bit multiplexed address/memory bus and was quite a bit smaller inside with fewer instructions. But then that would give you a pretty limited CPU wouldn't it? ;^)Article: 112104
Thomas Reinemann wrote:
> PeteS schrieb:
> > At bottom:
> >
> > PeteS wrote:
> >
> > You are obviously clocking things from somewhere. A margin of 300 ps or
> > so can get lost in the rise/fall times of a hot clock source. Have you
> > characterised your clock inputs properly for post-PAR analysis?
>
> Yes, four FPGAs shall work synchronous, therefore an external PLL comes
> into operation. The clock frequency has been characterized within the ucf.
>
> I solved the problem, simply by increasing this characterized frequency.
>
> Is there a guide line, to avoid such problems before they emerge? Where
> can I specify the jitter of an external clock source?
>
> Tom
Hello Tom,
Jitter for an external clock can be specified with the period
constraint. Here is an example from the Xilinx constraints guide
provided with XST:
1. Create Period
NET CLK TNM_NET = CLK_GRP;
TIMESPEC "TS_CLK" = PERIOD "CLK_GRP" 10 ns INPUT_JITTER 1;
If you are running your clock through a DCM, the jitter introduced by
the DCM is not added to your specified jitter as of the 8.1 tools, and
you need to increase your jitter spec to compensate.
Regards,
John McCaskill
Article: 112105John, Right you are. Spartan 2 is like "classic Coca-Cola", it is really hard to improve upon. Even the original Spartan (4KXLA derivative) is still going strong. Austin John Adair wrote: > Whilst FPGA families have an average life of 2 years as the lead family > in appropriate sector (low cost sector, or high performance sector), > they usually have a very long lifetimes. I wouldn't be surprised if > most of the Sparatan-II family are still around in 10 years time going > by past history. > > For price/performance though it is always hard to beat whatever the > latest family is and unless you need the a special feature like 5V > tolerance (without resistors or bus switches), or less power supply > rails, it is usually worth going to the latest. > > John Adair > Enterpoint Ltd. > > zwsdotcom@gmail.com wrote: >> John_H wrote: >>> If you inherited a box of the "pocket PCs" mid-2001, would you use those in >>> your systems? >> Maybe :) It depends how big the box was. >> >>> If your need is limited to stock on hand and the performance you get from >>> them is sufficient, I'd say "go for it" but if you end up purchasing more of >>> these devices in the long run, you'll probably be MUCH better with a current >> I just did a quick price compare vs. Spartan-III and I see what you >> mean. I don't have a specific need for these parts right now; nothing I >> build uses FPGAs. I was planning to lay down some footprints in "spare" >> space and wire the FPGA to the footprint of the 8-bit micro I use in an >> existing design, for experiments. But if I can't be sure of getting >> these parts on an ongoing basis, there's no point. >Article: 112106
Tom, Increase the period constraint (reduce the time) by 1/2 the overall expected system jitter value. If the clock input has 100 ps P-P, and the I/O switching adds 100 ps P-P, and a DCM CLKFX adds 400 ps P-P, one adds quadratically: square root of [100 squared + 100 squared + 400 squared] to get the total peak to peak system jitter. Take one half of that value and subtract it from the clock period for your constraint (worst clock pulse is shorter by half the P-P jitter). Each generation of the tools has improved upon the automatic calculation of jitter, and constraining the period for you. We have not reached perfection yet in the prediction of total system jitter (all we account for is DCM jitter, and ask the customer for their "system jitter" as calculated above). AustinArticle: 112107
rickman: > I guess you can build an 8080 out of TTL logic blocks, but that will > not be the way it was designed in the NMOS technology of the day. When > I was in high school we were given an old (even for 1967) weather > computer that did not use ICs. Each logic function; NAND gate, NOR > gate, FF, etc; was made from transistors using RTL logic technology. > But the main thing to consider was that it was made in modules about 2" > square with edge pin connectors based on standard functions. As I recall, that's how DEC got started. If you decide to go with the 2900, Mick and Brick has a complete worked-through design, though not for an 8080. The book is worth buying (second hand only) for the alliterative authors' names.Article: 112108
On 16 Nov 2006 07:47:35 -0800, "rickman" <gnuarm@gmail.com> wrote: >I guess you can build an 8080 out of TTL logic blocks, but that will >not be the way it was designed in the NMOS technology of the day. When There was a Schottky TTL chip slice implementation of the 8080 by Plessey. Size was several DoubleEuro-Cards and speed abt. 20 MHz(?), probably for the military market or who else could afford it. Name was Miproc or sth. like that. regards, GerhardArticle: 112109
Hi all, i'm new to boundary scan and want to make it work in the xilinx starter board, which contains a spartan-3 FPGA (xc3s200) and a platform flash PROM (xcF02s). i'd like to make just a simple test, independantly of any design, just to become familiar with this protocol: monitor the value of one of the 8 switches of the board. here is what i did: i entered an instruction: 000001 11111111 to put the PROM in bypass mode and the fpga in SAMPLE mode. then i shift data out but the expected value doen't appear on TDO after the expected number of clock edges, it seems that the capture state doesn't work. i've read that during configuration, I/Os are not connected, maybe this is my problem: i intentionnally changed the jumpers to prevent configuration otherwise once configured, boundary scan features aren't available any more. but maybe the system stays in configuration mode, waiting for configuration and disabling I/Os until configuration is done...can you help about this fact? and if i give up and try to instantiate the BSCAN_SPARTAN3 component in a design in order to make the boundary scan feature available after configuration, i just don't undertand at all how to instantiate it: what should i link the pins of the symbol to? thanks a lot in advance, i'm very interested in this technology and it would be a shame to give up.. florentArticle: 112110
Thanks a lot for your replies and clarifications... so let me summarize what i have understood. suppose i have a usb device with dma controller integrated that can sit on ahb bus as a master and slave can be some memory device or if it doesn't have any dma inside it it is still a slave and only host controller can be master on it (with ahb interface) right ? >>>>>> USB Pen drive = USB Device = Slave. >>>>>>=> you have to control it with a USB HOST IP >>>>>>=> this IP should be integrated on the AHB Bus as a ....Slave >>>>>>To do list : ->>>>>> integrate the USBHOSTSLAVE IP , host part , ( available at o>>>>>>pencores.org ) . This IP is Wishbone Slave Well in this above case let us think usb device is a slave then usb host ip has to be master right ? , are u saying some hoscontroller or some cpu which will be driving this "slave host ip" ???? on the bus..so host ip acts as both master and slave ? Regards On Nov 16, 7:20 am, Iwo Mergler <Iwo.Merg...@soton.sc.philips.com> wrote: > terabits wrote: > > Hi > > > I am very new to usb, I have some basic questions reagarding usb with > > ahb . > > > Suppose i have a ahb structure like 2 masters and 2 slaves. > > i want to have 2usb devices .....will this usb (usb 2.0 device) sit on > > the slave side ?Unless you want to implement a lot of buffer memory on the > device, it's probably more useful to integrate a DMA controller > into the USB block and run it as a AHB master. > > But otherwise, yes, it could be a AHB slave. > > > what will be on the master side ? suppose one dma as a master i have > > will the another master be arm processor or can it be some other usb > > device ? if so what could it be ? > > why at all usb has to interface with ahb ? only to interact with > > memories and arm processors ?Yes. There would be no point having the USB device, unless you > can move data to and from it. > > > can you give me a real time example like take a usb pen drive where > > will ahb comes into picture when i am connecting it to the computer ?USB pen drives are simpler devices and unlikely to use > a ARM processor. A typical ARM-with-USB-device application > would be a MP3 player, like the iPod. > > A software stack on the processor would then use the USB > device to implement the mass storage protocol. > > Kind regards, > > IwoArticle: 112111
<florent.peyrard@gmail.com> schrieb im Newsbeitrag news:1163696998.857615.68930@h54g2000cwb.googlegroups.com... > Hi all, > > i'm new to boundary scan and want to make it work in the xilinx starter > board, which contains a spartan-3 FPGA (xc3s200) and a platform flash > PROM (xcF02s). > > i'd like to make just a simple test, independantly of any design, just > to become familiar with this protocol: monitor the value of one of the > 8 switches of the board. here is what i did: i entered an instruction: > 000001 11111111 to put the PROM in bypass mode and the fpga in SAMPLE > mode. then i shift data out but the expected value doen't appear on TDO > after the expected number of clock edges, it seems that the capture > state doesn't work. i've read that during configuration, I/Os are not > connected, maybe this is my problem: i intentionnally changed the > jumpers to prevent configuration otherwise once configured, boundary > scan features aren't available any more. but maybe the system stays in > configuration mode, waiting for configuration and disabling I/Os until > configuration is done...can you help about this fact? > > and if i give up and try to instantiate the BSCAN_SPARTAN3 component in > a design in order to make the boundary scan feature available after > configuration, i just don't undertand at all how to instantiate it: > what should i link the pins of the symbol to? > > thanks a lot in advance, i'm very interested in this technology and it > would be a shame to give up.. > > florent > you are doing something wrong, boundary scan *IS* available before configuration and it works. AnttiArticle: 112112
Göran Bilski wrote: > MicroBlaze don't have a store buffer but some memory controllers has it. > But from MicroBlaze point of view, it will stall until it get an acknowledge > (doesn't have to be really stored in the memory). > If you using the XCL interface for caches, it has a built-in store buffer. > For MicroBlaze when using XCL a store will take 2 clock cycles if there is > room in the store buffer independent on when the word actually get written > into memory. > > Göran Thanks - This clears a lot of things. -Murali > > "mk" <kal*@dspia.*comdelete> wrote in message > news:3fsnl2li7tkdeitee4jm24shrakulhcs9s@4ax.com... >> On Wed, 15 Nov 2006 22:06:46 -0500, Murali <vmurali@mit.edu> wrote: >> >>> mk wrote: >>>> On Wed, 15 Nov 2006 09:06:17 +0100, "Göran Bilski" >>>> <goran.bilski@xilinx.com> wrote: >>>> >>>>> Hi Murali, >>>>> >>>>> It can never proceed until the memory access is finished. >>>>> MicroBlaze currently don't have an out-of-order exexcution. >>>>> >>>>> Göran >>>>> >>>>> "Murali" <vmurali@mit.edu> wrote in message >>>>> news:455a9e33$0$558$b45e6eb0@senator-bedfellow.mit.edu... >>>>>> Hi all >>>>>> >>>>>> Does Microblaze (v 5.00) stall on store (to a non-BRAM memory) till it >>>>>> receives an ack, or can it process other instructions while this store >>>>>> is >>>>>> on fly? >>>> A write buffer is different from OOE. You don't necessarily have to >>>> wait for the N number of writes to succeed (where N is the size of >>>> your write buffer) before executing the next instruction(s) perfectly >>>> in order. >>> So then, does Microblaze does have a store/write buffer? The reference >>> guide doesn't mention about it and I saw somewhere that some older >>> version of Microblaze in fact didnt have a store buffer. >> This documents http://www.xilinx.com/ise/embedded/mb_ref_guide.pdf >> says it's possible to configure the processor with a write-through >> datacache but it's not clear if the writes stall the processor or the >> cache controller can complete the write on its own. If latter the data >> cache can be used as a write buffer with additional features. > >Article: 112113
thanks for your answer, Antti; yes it is, but is it available for CAPTURE DURING configuration? Antti Lukats a =E9crit : > <florent.peyrard@gmail.com> schrieb im Newsbeitrag > news:1163696998.857615.68930@h54g2000cwb.googlegroups.com... > > Hi all, > > > > i'm new to boundary scan and want to make it work in the xilinx starter > > board, which contains a spartan-3 FPGA (xc3s200) and a platform flash > > PROM (xcF02s). > > > > i'd like to make just a simple test, independantly of any design, just > > to become familiar with this protocol: monitor the value of one of the > > 8 switches of the board. here is what i did: i entered an instruction: > > 000001 11111111 to put the PROM in bypass mode and the fpga in SAMPLE > > mode. then i shift data out but the expected value doen't appear on TDO > > after the expected number of clock edges, it seems that the capture > > state doesn't work. i've read that during configuration, I/Os are not > > connected, maybe this is my problem: i intentionnally changed the > > jumpers to prevent configuration otherwise once configured, boundary > > scan features aren't available any more. but maybe the system stays in > > configuration mode, waiting for configuration and disabling I/Os until > > configuration is done...can you help about this fact? > > > > and if i give up and try to instantiate the BSCAN_SPARTAN3 component in > > a design in order to make the boundary scan feature available after > > configuration, i just don't undertand at all how to instantiate it: > > what should i link the pins of the symbol to? > > > > thanks a lot in advance, i'm very interested in this technology and it > > would be a shame to give up.. > > > > florent > > > > you are doing something wrong, boundary scan *IS* available before > configuration and it works. >=20 > AnttiArticle: 112114
Ans are you using the same board as me? if yes, can you disable configuration? Antti Lukats a =E9crit : > <florent.peyrard@gmail.com> schrieb im Newsbeitrag > news:1163696998.857615.68930@h54g2000cwb.googlegroups.com... > > Hi all, > > > > i'm new to boundary scan and want to make it work in the xilinx starter > > board, which contains a spartan-3 FPGA (xc3s200) and a platform flash > > PROM (xcF02s). > > > > i'd like to make just a simple test, independantly of any design, just > > to become familiar with this protocol: monitor the value of one of the > > 8 switches of the board. here is what i did: i entered an instruction: > > 000001 11111111 to put the PROM in bypass mode and the fpga in SAMPLE > > mode. then i shift data out but the expected value doen't appear on TDO > > after the expected number of clock edges, it seems that the capture > > state doesn't work. i've read that during configuration, I/Os are not > > connected, maybe this is my problem: i intentionnally changed the > > jumpers to prevent configuration otherwise once configured, boundary > > scan features aren't available any more. but maybe the system stays in > > configuration mode, waiting for configuration and disabling I/Os until > > configuration is done...can you help about this fact? > > > > and if i give up and try to instantiate the BSCAN_SPARTAN3 component in > > a design in order to make the boundary scan feature available after > > configuration, i just don't undertand at all how to instantiate it: > > what should i link the pins of the symbol to? > > > > thanks a lot in advance, i'm very interested in this technology and it > > would be a shame to give up.. > > > > florent > > > > you are doing something wrong, boundary scan *IS* available before > configuration and it works. >=20 > AnttiArticle: 112115
> Well in this above case let us think usb device is a slave then usb > host ip has to be master right ? > , are u saying some hoscontroller or some cpu which will be > driving this "slave host ip" ???? on the bus..so host ip acts as both > master and slave ? Not exactly : i meant USB Host is slave on AMBA Bus and is connected to the USB Device via USB Cable , through a PHY (transceiver circuit) To control the USB device, "you" have to be Master on the AMBA Bus and access the memory range affected to the "USB Host AMBA Slave " (sic!) which in turn will control the USB Slave with USB Cmds. AMBA USB USB MASTER HOST IP **** PHY ***USB Cable********* DEVICE | | | | ==== AMBA BUS =========Article: 112116
Hello! I'm trying to design in a V5, which will be sharing a memory bus
with a DSP and some peripherals. However, the V5 consumes a lot of
power (350 mW) when not doing anything, and so it would be nice to
power it down (ala the Spartan-3L) in this mode.
Having looked at the app note and the comp.arch.fpga archives, it seems
that simply shutting off all power to the FPGA could be problematic as
this will leave the IO pins in an unknown state. So one suggested
solution was :
1. tristate all IOBs
2. remove Vccaux and VCCint power
3. leave Vcco
thus keeping the IOs in a tri-state configuration.
>From the XPower Estimator for the V5 it seems that quiescent power is
all made up of Vccint (239 mW) and VCCaux (118 mW) -- nothing for IO.
Similarly, page 3 of DS202 (the DC/Switching data sheet for the V5)
shows a XC5VLX30 sucking down a mere 1.5 mA @ VCCo (~ 5mW).
Is that -for the entire device- or per-bank? If per bank (ouch!) then
I'm going to investigate using a coolrunner between the bus and the
FPGA -- while it might hurt SI, it seems the only way.
What other schemes have people tried to reduce high-density device
power consumption?
Thanks,
...Eric
Article: 112117Gabor schrieb: > I'm seeing some strange behavior when trying to program > a Spartan 2e (XC2S150E) directly via JTAG. In the system > it is normally programmed using master serial mode from > the XCF02S "platform flash" part. The JTAG chain starts > with the XCF02S and then ends at the XC2S150E - no > other parts. I can program the XCF02S without problem > using JTAG. I can also program the XC2S150E without > problems via JTAG _IF_ the XCF02S is blank. Once the > FPGA has been programmed from the XCF02S using > master serial mode, which is the normal case after > power-up, attempts to re-program the FPGA using JTAG > fail. This does not seem to be a problem with the > FPGA running. I can re-program the FPGA via JTAG > when it is running _IF_ the FPGA was originally configured > via JTAG. I have opened a web case on this, but I thought > someone here may have some insight on this issue. I > saw in an old thread the following note: > > David Kinsell wrote: > > We've seen different problems with an XCF02S in the chain ahead of a > Spartan 2 part. Done never goes high on the Spartan when attempting > JTAG programming. Take the XCF02 out of the chain and it works. > Discovered that if the XCF02 is blank, then we can program the Spartan > OK. Xilinx has some answer records (18644 and others) on related > issues, but that didn't seem to apply to us. this issue can cause problems for different parts, no matter if there is an Xilinx AR or not the thing is that if any non-JTAG config interface shifts in valid SYNC word during some specifig time in the JTAG config process then the JTAG configuration will fail. happens with XCFxx master serial mode, happens with Se3 BPI mode (at least early silicon) etc, etc.. so just make sure the config is blank anttiArticle: 112118
Thanks for the tips Daniel, I'll keep my extra registers to two levels then. I finally achieved timing, by using register balancing but also by using truncated rounding instead of the "correct" rounding for the floating point operations. I also had my fair share of xst crashes (even with v8.2 SP3) with the new VHDL-200x librairies... PatrickArticle: 112119
thank you for that,so as i said im new..i may be having silly doubts. so here it goes .let us think im connecting my camera to the computer to download some stuff to the computer. here my camera is a slave to computer.from outside world may be because of its size or something. but let us think camera has dma controller so dma of host device (camera) will be master and will control the so called host ip (usb host's memory) as a ahb master here host is a slave. if above case is correct. i got it..and i am asking about the other case..in what cases other than dma transfers (in this case it is host ) the devices will be as a USB slave and what kind of Master it needs ?? what will be the master. ?? regards > Not exactly : i meant USB Host is slave on AMBA Bus and is connected to the > USB Device via USB Cable , through a PHY (transceiver circuit) > To control the USB device, "you" have to be Master on the AMBA Bus and > access the memory range affected to the "USB Host AMBA Slave " (sic!) > which in turn will control the USB Slave with USB Cmds. > > > AMBA USB > USB > MASTER HOST IP **** PHY ***USB Cable********* > DEVICE > | | > | | > ==== AMBA BUS =========Article: 112120
Thomas Reinemann wrote: > PeteS schrieb: >> At bottom: >> >> PeteS wrote: >> >> You are obviously clocking things from somewhere. A margin of 300 ps or >> so can get lost in the rise/fall times of a hot clock source. Have you >> characterised your clock inputs properly for post-PAR analysis? > > Yes, four FPGAs shall work synchronous, therefore an external PLL comes > into operation. The clock frequency has been characterized within the ucf. > > I solved the problem, simply by increasing this characterized frequency. > > Is there a guide line, to avoid such problems before they emerge? Where > can I specify the jitter of an external clock source? > > Tom The added jitter is given as the rise / fall time within the indeterminate region of the input FF. Let's assume the FF is TTL, then the indeterminate region is from 0.8V (max guaranteed low) to 2.0V (min guaranteed high). If your clock takes (again, as an arbitrary for instance) 250ps to traverse that region, then you should add that as a jitter factor. Although the typical switching threshold in TTL mode is about 1.3V, it can (and will, depending on temperature and other things) switch at any point between the guaranteed input levels. CMOS is 1/3 -> 2/3 Vcc. Cheers PeteSArticle: 112121
Jonas, The static IO current is per bank (for 3.3V), in tristate, with pullups/pulldowns disabled. 2.5V, or 1.5V IO bank powering will be much less static current. As soon as the Vccint, Vccaux, or Vcco_config supplies are below the power ON reset threshold, configuration memory (including BRAM is cleared), the device forces all IOs tristate (if there is a remaining Vcco supply). The IOs remain tristate until the POR is released when all of the three power supplies pass above their POR thresholds, the device has cleaned out, has configured, and the customer pattern has taken over control of the IOs (DONE goes high and it is all under your control). If there is no power at all on any supply pins, then there is a diode from ground to an IO pin, and a diode from the IO pin to the Vcco pin (intrinsic self protecting output structure - ie "plain old CMOS totem pole" output structure). Austin jonas@mit.edu wrote: > Hello! I'm trying to design in a V5, which will be sharing a memory bus > with a DSP and some peripherals. However, the V5 consumes a lot of > power (350 mW) when not doing anything, and so it would be nice to > power it down (ala the Spartan-3L) in this mode. > > Having looked at the app note and the comp.arch.fpga archives, it seems > that simply shutting off all power to the FPGA could be problematic as > this will leave the IO pins in an unknown state. So one suggested > solution was : > > 1. tristate all IOBs > 2. remove Vccaux and VCCint power > 3. leave Vcco > > thus keeping the IOs in a tri-state configuration. > >>From the XPower Estimator for the V5 it seems that quiescent power is > all made up of Vccint (239 mW) and VCCaux (118 mW) -- nothing for IO. > Similarly, page 3 of DS202 (the DC/Switching data sheet for the V5) > shows a XC5VLX30 sucking down a mere 1.5 mA @ VCCo (~ 5mW). > > Is that -for the entire device- or per-bank? If per bank (ouch!) then > I'm going to investigate using a coolrunner between the bus and the > FPGA -- while it might hurt SI, it seems the only way. > > What other schemes have people tried to reduce high-density device > power consumption? > Thanks, > > ...Eric >Article: 112122
Ray Andraka wrote: > PeteS wrote: > > >> Now come, Austin. If the tool tells me I have positive margin (however >> small) I expect that to be true. I've done designs where I calculated >> the worst case and had a _guaranteed_ margin of 8 ps. Note the word >> guaranteed. I thought the post-PAR analysis tools gave me guaranteed >> timings. >> >> > > That is true provided you have a jitter-free clock. The tools do not > know, nor can they predict how much jitter is on your clock. You need > to consider a jitter margin in your clock constraints, as any jitter > erodes the minimum clock period. Keep in mind that you not only have > the jitter introduced by the DCMs if you use them, but also jitter > inherent in your clock source plus jitter added by noise on the board > and more importantly by modulation of the VCC-IOs of the clock pins by > other pins switching on the bank or by fluctuations in the power rails. > If you subtract your cycle-to-cycle max jitter from the clock > constraint, then you wind up with guaranteed operation. > > In a lab environment, you can usually get away with ignoring the jitter, > as you usually won't be anywhere near the slow corner of voltage, > process and temperature. In the field though, not allowing for > sufficient jitter tolerance is likely to come back and bite you hard in > the shorts. See my other posts. I assume jitter of the transition time through the indeterminate region and add it in. As I have noted, I still am responsible for adding those things in (because the tool can not possibly know about them). In this case, I was referring to the tool itself. I expect it to give me something I can rely on *for the area it is supposed to be authoritive for*. I do not expect it to add in external clock jitter. I _do_ expect it to add in internal jitter in the FPGA, provided said jitter source is within the device. Failing that, guidance is helpful (as has actually been provided in another response on this thread). It is indisputable that jitter and delay will be induced internally in the FPGA due to routing and loading (just as it would be for any other circuitry) - I simply want the tool to report what that is. If it must err on the conservative side, so be it. Cheers PeteSArticle: 112123
PeteS wrote: > Inline > > Austin Lesea wrote: > > PeteS, > > > > See below, > > > > Austin > > > > -snip- > > > > > Now come, Austin. If the tool tells me I have positive margin > (however > > > >> small) I expect that to be true. I've done designs where I calculated > >> the worst case and had a _guaranteed_ margin of 8 ps. Note the word > >> guaranteed. I thought the post-PAR analysis tools gave me guaranteed > >> timings. > >> > > Sure. For whatever you constrained. Did everything get constrained > > properly? This is not a trivial task: > > No it isn't. I have spent days on end making sure I have considered > everything involved. > > > verifying timing closure may > > sometimes take up huge amounts of time (to verify every critical path > > has sufficient slack, and was properly constrained). And 8ps of margin > > means that if you have 16 ps P-P of jitter, you have no slack left, and > > errors may occur if the jitter increases by even one ps... > > > > But if you have a clock with 400 ps P-P of jitter (not uncommon), and > > you have lots of IOs switching, and you have power supply variations, > > and so on, you might be at the edge, or over the edge. (Probably > > are...as was obvious in this case) > > > > > > I am anal about my constraints. I've done really high speed stuff > (10Gb/s) but even the marginal things (DDR above 200/400 comes to mind) > will bite you if you haven't properly constrained the design. The last > time I did that I even added the delays (and filter effect) of the bond > wires from the pad to the die. Perhaps the OP is not so anal about it > but needs to be. My design worked first time for that, for what it's worth. > > > > >> I agree with Austin that your margin is sorta > >> small. > >> > > Yes, it is. I recommend having at least the peak to peak worst case > > measured jitter as margin (slack). That means you have a factor of two > > for safety. Considering peak to peak jitter is unbounded (14 sigma > > enough? 16 sigma? 20 sigma?), you really do not want to cut things too > > close (or you will eventually fail in some > > process/voltage/temperature/jitter 'corner'. > > > > > > > > Deterministic jitter will kill a design, but it's predictable (see my > comments about being anal). PCB tracks can add enough jitter to swamp > 300ps of margin, especially if there are vias involved. There are > techniques to alleviate this, of course (maybe I should publish how I > did it ;) > One can not, however, eliminate it. > > > >> I would also check to see if you are adding the signal rise/fall (which > >> can get quite high for non-rocket IO pins) as temperatures increase. > >> > > True, if the rise time is long, then you probably also have a lot of > > jitter (as a long slow rise time leads to imprecise transitions). > > > > > > > > > > That's my point. A FF will clock at some point in the active region. The > indeterminacy of this region *must* be added to the error budget if you > want guaranteed timing. > > Cheers > > PeteS > > Please don't take comments such as 'come now' personally. They are meant to open dialogue, not constrain it. Although I lived in the states for well over 20 years, there remain some language issues ;) My only point was to say I want the tools to report what they *should* be able to report; not to be a replacement for solid engineering. Cheers PeteSArticle: 112124
Hi,
I am a student, without much experience of synthesis. My task was to
make some modifications (i.e. insert faults) to the ISCAS benchmark
circuits and synthesize them to the FPGAs. I read the circuits using
the ISCAS benchmark format - made my changes to the circuit structure
and dumped out the VHDL.
My problem is that I cannot get this to synthesize with the standard
tools for medium sized circuits i.e. they either run out of memory or
they complain that my file is too long or something like that.
(Circuits with a few hundred gates work fine - so I dont have a problem
with syntax or somehting like that.) I wonder if there is a way out for
me.
Initially I dumped each of the faults that I had inserted as separate
entities. This made the number of entities that I used too large e.g.
for a 10K gate circuit - I had a little more than 10K entities. Note
that I did not increase the number of gates - but I just added
additional Muxs (multiplexers) and some control lines. I was surprised
that this modified circuit would not synthesize.
XST (8.2) complained that it ran out of 4 GB of memory, Synopsis
complained that the number of lines in my file were more than 1 million
- this made me move some entities to separate files - but finally it
also crashed.
Somebody then came along and told me that the synthesis tools require
a lot of overhead for the entities. So I decided now to just put
everything in one big global entity. Here also XST crashes after
hitting the 4GB memory error.
A code sample showing one of my gates (with the associated Mux) is
Nand_2_0_0 : forg_node_16_Cell_0 <= not (input_2_Cell_0 and
node_11_Cell_0);
SEL_node_16_Cell_0(1) <= ctrl_fault_4_Cell_0;
SEL_node_16_Cell_0(2) <= ctrl_fault_5_Cell_0;
MUX_Gate_3_1node_16_Cell_0 : process (SEL_node_16_Cell_0,
insert_faults_Cell_0, forg_node_16_Cell_0, fault_4_node_16_Cell_0,
fault_5_node_16_Cell_0)
begin
if (insert_faults_Cell_0 = '0') then
node_16_Cell_0 <= forg_node_16_Cell_0;
elsif (insert_faults_Cell_0 = '1') then
case SEL_node_16_Cell_0 is
when "01" => node_16_Cell_0 <=
fault_4_node_16_Cell_0;
when "10" => node_16_Cell_0 <=
fault_5_node_16_Cell_0;
when others => node_16_Cell_0 <=
forg_node_16_Cell_0;
end case;
else
node_16_Cell_0 <= forg_node_16_Cell_0;
end if;
end process MUX_Gate_3_1node_16_Cell_0;
(Just imagine that I do this 10K times - including final signal
mapping.)
I hope you can tell me what is the size of the circuits that you guys
synthesize? Am I trying something impossible here? - I thought 10K was
a small size. I would be glad to hear of any ideas you may have on how
to get this to synthesize. I am not so much concerned about the run
time - but that it works without crashing.
Thanks a lot.
O.O.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z