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Tim, 47% of all statistics are made up on the spot. AustinArticle: 113176
davidc@ad-holdings.co.uk wrote: > Hi, > > I'm trying to create a Count Leading Zero (CLZ) in VHDL for a project > but i'm having difficulty in finding any information what so ever apart > from an explanation as to what it does, can anyone help? > > Can anyone explain what logic would be required to create a CLZ, i've > only found one point of reference on the web which uses a number of > nested multiplexers with the output of one being fed back into the > select line of the next. Any information regarding the hardware/ schema > would be greatly appreciated. > > Thanks, Dave > Perhaps you might find this useful: http://tima-cmp.imag.fr/~guyot/Cours/Oparithm/english/Flottan.htm Cheers, AndyArticle: 113177
Hi Peter Alfke, I think we are describing the same thing. In the first picture (http://www.topweaver.com/doc/tad/images/ov1.jpg), the "Clock Out" has only the length of 5 and 6, which is you wanted. And sometimes people may need a large jitter clock, or just a flag of some time slot (not used for clock), they can drag the waveform to anything they want in the manual mode. TAD "Peter Alfke =D0=B4=B5=C0=A3=BA " > Let me explain what I mean with n and n-1. > > If you want to reduce the number of pulses per unit time (that's what > you are doing) you do that by eliminating pulses from the input stream. > You can achieve ANY desired result by a pattern of eliminated pulses. > I claim that this pattern can achieve the desired result best when the > number of adjacently eliminated pulses never varies by more than one. > If you must eliminate 4 adjacent pulses, then mix that with 3 adjacent > pulses. Or for a lower "frequency" mix it with 5 adjacent pulses, but > never with a mixture of 3, 4, and 5 adjacent pulses. There is no need > for it mathematically. > Peter AlfkeArticle: 113178
Hi Gabor, Thanks very much for your suggestion. Maybe I can fulfill it at this weekend. Before the new release, I will post the sample generated verilog code here. TAD "Gabor =D0=B4=B5=C0=A3=BA " > Very interesting program. I have a suggestion for code implementation > to work better in Xilinx (and possibly other) FPGA's. Your code uses > clock gating to generate narrow pulses. At least in Xilinx FPGA's it > is > not a good assumption that the Q output of a flip-flop has a longer > delay to the gate input than the clock does. In fact, depending on the > placement, a route from a global clock to a LUT input can be several > nanoseconds. This can cause glitches even when you use the > "correct" phase of the clock in your output logic. I would suggest > using only flip-flop outputs to generate the module output, using > XOR functions as necessary to generate outputs using both clock > edges. The global clock routing to the flip-flop clocks is much better > than you can do routing a global clock to a LUT input (or flip-flop D). > > For waveforms that change on both input clock edges, It should > be possible to generate the output as the XOR of just two flip-flops, > one clocked on each edge. One of the flip-flops would toggle at each > edge in the output waveform. At higher input clock rates this method > also gives improved duty cycle accuracy, as the clock to output path > on each edge looks like one flip-flop clock to Q delay followed by one > LUT delay. Differences in clock-to-Q for rising vs falling edge > flip-flops > are small compared to routing delays in the FPGA. >=20 > Regars, > GaborArticle: 113179
Does synplify support recursive component instantiation, i.e. a component which instantiate its own entity within its architecture...Article: 113180
You are right. Your second example (4/7) only seems to demonstrate that the user can deliberately create a sub-optimal solution. But you should still indicate that your solution is (in the general case) not an alternative to a DCM or PLL solution which can achieve far lower jitter values. Peter Alfke On Dec 7, 8:56=C2=A0am, topwea...@hotmail.com wrote: > Hi Peter Alfke, > I think we are describing the same thing. > In the first picture (http://www.topweaver.com/doc/tad/images/ov1.jpg), > the "Clock Out" has only the length of 5 and 6, which is you wanted. > And sometimes people may need a large jitter clock, or just a flag of > some time slot (not used for clock), they can drag the waveform to > anything they want in the manual mode. > TAD > > "Peter Alfke =E5=86=99=E9=81=93=EF=BC=9A > " > > > Let me explain what I mean with n and n-1. > > > If you want to reduce the number of pulses per unit time (that's what > > you are doing) you do that by eliminating pulses from the input stream. > > You can achieve ANY desired result by a pattern of eliminated pulses. > > I claim that this pattern can achieve the desired result best when the > > number of adjacently eliminated pulses never varies by more than one. > > If you must eliminate 4 adjacent pulses, then mix that with 3 adjacent > > pulses. Or for a lower "frequency" mix it with 5 adjacent pulses, but > > never with a mixture of 3, 4, and 5 adjacent pulses. There is no need > > for it mathematically. > > Peter AlfkeArticle: 113181
rponsard@gmail.com wrote: > I am new to fpga design... and don't know the good practice to handle > differential I/O. > > I am right using OBUFDS and IBUFDS component ? > > I have errors with ISE8.2 and my differential pairs (rx_pin and tx_pin) > : > > I greatly appreciate any helps... or a link to example for S3E starter > kit > [... snip ...] There are a few coding examples in the following E-mail that might prove useful. The code applies for Spartan-3, Spartan-3E, and the new Spartan-3A. XAPP491: Inverting LVDS Signals for Efficient PCB Layout in Spartan-3 Generation FPGAs http://www.xilinx.com/bvdocs/appnotes/xapp491.pdf You can download the design examples directly from the following link. http://www.xilinx.com/bvdocs/appnotes/xapp491.zip --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3 Generation FPGAs http://www.xilinx.com/spartan3a http://www.xilinx.com/spartan3e E-mail: steve.knapp@xilinx.com --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 113182
Interesting.. I didn't know that fact about DSP48's. Indeed I am using asynchronous resets, so I'll try changing the registers before and after the multiplier to synch reset. Much thanks to all. -Brandon Jim Wu wrote: > > Is ISE smart about dealing with the BUFR's? What if you have too many > > slices for a given BUFR region and they can't fit? Will it burp? > > You would just get an error saying the design is unroutable if that > happens. > > > Is there anyway to improve timing with any of the Virtex 4 > > capabilities? > > You can try to see if you can abosorb some of the registers into DSP48. > If DSP48s are infereed, first thing to check if you have asynchrounous > reset. Registers can not be pushed into DSP48 if you do. > > Cheers, > Jim > http://home.comcast.net/~jimwu88/tools/Article: 113183
Patrik Eriksson wrote: > Does synplify support recursive component instantiation, i.e. a > component which instantiate its own entity within its architecture... Yes, and it has since at least 4.2, although there have been occasionally some hiccups with some versions. If you run into a problem,however, don't expect to get much help from their tech support regarding recursion. I never was able to get their hotline engineer to understand why I wanted to recurse and not just construct with direct instantiation.Article: 113184
davidc@ad-holdings.co.uk wrote: > Hi, > > I'm trying to create a Count Leading Zero (CLZ) in VHDL for a project > but i'm having difficulty in finding any information what so ever apart > from an explanation as to what it does, can anyone help? > > Can anyone explain what logic would be required to create a CLZ, i've > only found one point of reference on the web which uses a number of > nested multiplexers with the output of one being fed back into the > select line of the next. Any information regarding the hardware/ schema > would be greatly appreciated. > > Thanks, Dave > The best way depends on what you intend to do with the count. If it will be used to left-justify the data, then the best approach is to use a series of 2:1 muxes with each layer controlled by the previous layer's output. The control function is easiest if you use sign-magnitude notation rather than two's complement, since that makes it strictly leading zeros rather than redundant sign. The mux on the last layer shifts by 1 bit or passes unchanged, the previous layer by 2 bits or unchanged, the one before that 4 bits or unchanged and so on. The select decision for each layer forms 1 bit of the leading zero count, which is the same as the number of positions the data was shifted left. If, on the other hand, you are not also shifting the data, then you need some form of priority encoder to encode the position of the first 1. The Xilinx 4000 series was nice for this because the carry chain could go up or down the chip, so you could set it up to propagate down and use it as a first '1' detect (a one-hot signal), which is very easy to encode into a leading zero count without having to propagate a 'carry' in the encoder.Article: 113185
Steve: You forget to mention the transmission speed requirement. Is 10/100 MBPs or 1000 MBPs, you would need to make some trade off depending on the data rate. -James Steve wrote: > Hi all, > > I want to add an Ethernet interface to my FPGA board for data transmission. > But I'm not sure which scheme I should use. > > A) There's a PHY on the FPGA board, but I don't have much knowledge or > experience on MAC. The protocol seems complicated and not easy to implement > in a short time. Is it possible to develop a small and simple MAC? My idea > is packing data to form a standard TCP or UDP packet and using the PHY to > send out or receive it. Another reason I don't want using a full MAC is it > costs too much resources (~2000 slices). If I use MicroBlaze+OPB MAC, I > can't afford the license fee. > > B) Using another external Ethernet micro-controller, such as Rabbit > microprocessor. I can develop an interface between FPGA and uC for data > transmission. But I'm wondering how fast the speed is? > > C) Using micro-controller + (MAC+PHY Ethernet single chip). Then porting > uClinux or lwip to the uC and hanging FPGA to the address/data bus of the > uC. > > Any suggestions? Thank you. > > JJArticle: 113186
> I agree 100% ... this core is a huge time saver and offers some nice > flexibility. I am curious to see what performance is like :)! The performance benefit is amazing as you will found out. The only drawback is significant logic and BRAM consumption. Cheers, GuruArticle: 113187
It's probably caused by some funny characters added to the command line. I use Makefile all the time on a linux box and have never seen such issues. Cheers, Jim http://home.comcast.net/~jimwu88/tools/ johnp wrote: > I'm trying to get the PAR tool to run using makefiles and it > consistently crashes with the message: > > > Starting Placer > > Phase 1.1 > Phase 1.1 (Checksum:98ee53) REAL time: 32 secs > > Phase 2.7 > Phase 2.7 (Checksum:1312cfe) REAL time: 32 secs > > Phase 3.31 > Phase 3.31 (Checksum:1c9c37d) REAL time: 32 secs > > FATAL_ERROR:Place:PlXil_GClkDD.c:234:1.1.4.4 - in file "" Line 0, > Column 0, Message: Process will terminate. To resolve this error, > please consult the Answers Database and other online resources at > http://support.xilinx.com. If you need further assistance, please open > a Webcase by clicking on the "WebCase" link at > http://support.xilinx.com > > If I run PAR from the command line, it runs OK. If I use nmake or > wmake and my makefile, > it crashes. I've opened a WebCase, but I've little hope that they > will resolve anything. > > Has anyone else run across this? > > Thanks! > > John PArticle: 113188
I don't wish to hijack your thread, but what would you use recursive component instantiation for? are you instantiating within an instantiation? Cheers davidArticle: 113189
> I am trying to connect a variable latency memory to microblaze. I would > like to use the LMB bus since the interface looks simple. But from the > timing diagrams in the reference guide, it looks like the ready signal > is not used in microblaze. I just want to clarify that - whether the > microblaze LMB interface is a synchronous (read non variable-latency) > interface, which doesnt look at the ready signal in the bus. > I'm not sure about the details of the LMB bus. Maybe someone else would comment on that. Personally I think you should be using XCL if you want to connect a memory core to MicroBlaze. The XCL connection feeds into the caches of MB. Interface-wise, its extremely simple - an FSL bus with some protocol on top of it. You could look at any of the mch_* memcons in EDK. /SivaArticle: 113190
thanks, I already got xapp941.pdf but I still have trouble configuring those diff. I/O, now with VCC0 = 3.3V and diff LVDS2.5 ISE can't place : Phase 1.1 ERROR:Place:311 - The IOB tx_pin_p is locked to site PAD17 in bank 0. This violates the SelectIO banking rules. Other incompatible IOBs may be locked to the same bank, or this IOB may be illegally locked to a Vref site. Phase 1.1 (Checksum:98d76b) REAL time: 5 secs xilinx answer database tells : Solution 1: This is a legal placement in hardware. However, the software currently does not allow this placement. LVCMOS15, LVCMOS18, and LVCMOS25 inputs must be in a bank with a matching VCCO level. These overly restrictive banking rules will be fixed in 9.1i, which is scheduled to be released in Winter 2006. In the meantime, if you want to place one of these standards in a bank with a higher VCCO level (for example, an LVCMOS25 input in a bank with VCCO=3.3V, or an LVCMOS15 input in a bank with VCCO = 2.5V), you can modify the IOSTANDARD in the FPGA Editor and run BitGen without the DRC check (bitgen -d). could you be more verbose about this solution ; aka - how use FPGAEditor to change IOSTANDARD - where can I configure bitgen w/o DRCArticle: 113191
On Wed, 29 Nov 2006 14:25:09 GMT, "sjb" <sjb@mindspring.com> wrote:
>Hi all,
>
>Would anyone be able to direct me to (or provide me with) any materials
>related to this board that I've got.
>
>http://trifs.dyndns.org/xilinx%20board.jpg
What you have is a standard Xilinx XC3000 demo/eval board, and
it dates back to prior to 1989. (somewhere in my garage I have
about 30 of them) The amount of effort it would take to use
this board could not possibly be worth it.
http://www.fpga-faq.org/FAQ_Pages/0009_Xilinx_sw_versions.htm
Since your goal is to add to your education, I would highly
recommend that you get a current board with something like a
Spartan 3 on it, and use the current free software from
Xilinx: WebPack.
You can start your shopping expedition here:
http://www.fpga-faq.org/FPGA_Boards.shtml
Enjoy!
Philip Freidin
===================
Philip Freidin
philip.freidin@fpga-faq.org
Host for WWW.FPGA-FAQ.ORG
Article: 113192
Thanks for the info guys it's starting to make sense.
On Dec 7, 6:49 pm, Ray Andraka <r...@andraka.com> wrote:
> dav...@ad-holdings.co.uk wrote:
> > Hi,
>
> > I'm trying to create a Count Leading Zero (CLZ) in VHDL for a project
> > but i'm having difficulty in finding any information what so ever apart
> > from an explanation as to what it does, can anyone help?
>
> > Can anyone explain what logic would be required to create a CLZ, i've
> > only found one point of reference on the web which uses a number of
> > nested multiplexers with the output of one being fed back into the
> > select line of the next. Any information regarding the hardware/ schema
> > would be greatly appreciated.
>
> > Thanks, DaveThe best way depends on what you intend to do with the count. If it
> will be used to left-justify the data,
There is no practicle intention, it's more of an exercise to understand
how it works, so i'm mearly try to count the number of leading zeros
starting at the most significant bit.
> then the best approach is to use
> a series of 2:1 muxes with each layer controlled by the previous layer's
> output.
Similar to the CLZ diagram in the link provided by Andy above:
http://tima-cmp.imag.fr/~guyot/Cours/Oparithm/english/Flottan.htm
The diagram in the following link uses muxes, but they have multiple
outputs why is this? or are they adders in the diagram?
> The control function is easiest if you use sign-magnitude
> notation rather than two's complement, since that makes it strictly
> leading zeros rather than redundant sign. The mux on the last layer
> shifts by 1 bit or passes unchanged, the previous layer by 2 bits or
> unchanged, the one before that 4 bits or unchanged and so on. The
> select decision for each layer forms 1 bit of the leading zero count,
> which is the same as the number of positions the data was shifted left.
>
OK, so the output of each mux is fed into the "next layer's" input mux
and in addition to this the select line SEL forms the total output of
the circuit.
So if I had an 8 bit input, the output would be 4 bits. so on the first
layer which is uses 2 bit muxes on the input, for an 8 bit CLZ the
first layer would have 4 SEL lines, are these just connect together to
form the first bit of the output?
something like:
0 1 2 3 4 5 6 7
| | | | | | | |
-------- S -------- S -------- S -------- S
| |----| | |----| | |----| |
|----| 2's
-------- -------- -------- --------
| |
|_____ ___|
| |
--------
| |
4's
--------
I this instance for output bit 0 all the "S" would be connected
together, is this coreect?
Is there any additional digital circuity required or is it all done
using muxes and "not" gates for the inputs.
Is there any way of doing this using Karnaugh maps, i've had experience
before with them, but where would I start on something like this?
Thanks,
Dave
> If, on the other hand, you are not also shifting the data, then you need
> some form of priority encoder to encode the position of the first 1.
> The Xilinx 4000 series was nice for this because the carry chain could
> go up or down the chip, so you could set it up to propagate down and use
> it as a first '1' detect (a one-hot signal), which is very easy to
> encode into a leading zero count without having to propagate a 'carry'
> in the encoder.
Article: 113193Given that synplify (and any other synthesis tool that supports recursion) requires the recursion to be staticly bound, there is always a way to describe a recursive solution with loops. Often the recursive form is easier to understand. They have to be staticly bound so that synthesis can unroll the recursion to a determinately finite end. Recursion can be done with instantiating using if-generate statements that conditionally instantiate themself, which by definition are staticly bound. Recursion can also be done with function or procedure calls that conditionally call themself. Andy googlinggoogler@hotmail.com wrote: > I don't wish to hijack your thread, but what would you use recursive > component instantiation for? are you instantiating within an > instantiation? > > Cheers > > davidArticle: 113194
googlinggoogler@hotmail.com wrote: > I don't wish to hijack your thread, but what would you use recursive > component instantiation for? are you instantiating within an > instantiation? > > Cheers > > david > Sometimes a parameterized component is easiest to generate with recursion. For example an adder tree can be generated by recursively calling a component that adds two vectors.Article: 113195
Siva Velusamy wrote: >> I am trying to connect a variable latency memory to microblaze. I >> would like to use the LMB bus since the interface looks simple. But >> from the timing diagrams in the reference guide, it looks like the >> ready signal is not used in microblaze. I just want to clarify that - >> whether the microblaze LMB interface is a synchronous (read non >> variable-latency) interface, which doesnt look at the ready signal in >> the bus. >> > > I'm not sure about the details of the LMB bus. Maybe someone else would > comment on that. > > Personally I think you should be using XCL if you want to connect a > memory core to MicroBlaze. The XCL connection feeds into the caches of > MB. Interface-wise, its extremely simple - an FSL bus with some protocol > on top of it. You could look at any of the mch_* memcons in EDK. > > /Siva I dont want to use microblaze's caches, atleast for now. Thats why I am not using XCL. I want microblaze to be oblivious of how I manage memory.Article: 113196
"johnp" <johnp3+nospam@probo.com> writes: > If I run PAR from the command line, it runs OK. If I use nmake or > wmake and my makefile, > it crashes. I've opened a WebCase, but I've little hope that they > will resolve anything. Could it be that you set some environment variables (including PATH) differently in your makefile? Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 113197
Hi all, It seems that run-time reconfigurations are only available in DCM and RocketIO blocks. Concerning about partial reconfiguration, can every functional block be partially reconfiged? thanksArticle: 113198
At least 10Mbps, desiralbly 100Mbps. "dexue" <yangdexue@gmail.com> ??????:1165518730.953912.148850@79g2000cws.googlegroups.com... > Steve: > You forget to mention the transmission speed requirement. > Is 10/100 MBPs or 1000 MBPs, you would need to make some trade off > depending on the data rate. > -James > Steve wrote: >> Hi all, >> >> I want to add an Ethernet interface to my FPGA board for data >> transmission. >> But I'm not sure which scheme I should use. >> >> A) There's a PHY on the FPGA board, but I don't have much knowledge or >> experience on MAC. The protocol seems complicated and not easy to >> implement >> in a short time. Is it possible to develop a small and simple MAC? My >> idea >> is packing data to form a standard TCP or UDP packet and using the PHY to >> send out or receive it. Another reason I don't want using a full MAC is >> it >> costs too much resources (~2000 slices). If I use MicroBlaze+OPB MAC, I >> can't afford the license fee. >> >> B) Using another external Ethernet micro-controller, such as Rabbit >> microprocessor. I can develop an interface between FPGA and uC for data >> transmission. But I'm wondering how fast the speed is? >> >> C) Using micro-controller + (MAC+PHY Ethernet single chip). Then porting >> uClinux or lwip to the uC and hanging FPGA to the address/data bus of the >> uC. >> >> Any suggestions? Thank you. >> >> JJ >Article: 113199
I finally checked what happens when using an LMB with microblaze. Looks like it is waits for a ready in the bus as the programs hang if they contain a load/store. So now my question is: how does the microblaze issue the next load/store when the first is in flight (according to the timing diagram in the spec). Does it issue a maximum of two instructions before looking at the ready? Checking this involves more work, so I would be happier if someone knows and can tell :) Thanks Murali
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