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Robert Scott wrote: > On Sun, 10 Dec 2006 22:39:35 -0500, Ray Andraka <ray@andraka.com> wrote: > > >>..Getting the data back into natural order requires an additional memory buffer >>which adds to the latency and increases the hardware complexity. > > > Well, it does add latency, but the bit-reversal transformation can be done in > place with no additional buffer. > > > > Robert Scott > Ypsilanti, Michigan What I meant was that it requires another trip through memory to accomplish...it can't be done without temporary storage of the samples because there is a corner-turn. Implementation, of course can be done in many ways, including using a addressable shift register if that is what tickles your fancy. In a hardware implementation, this means either an additional memory (or registers) or additional sequencing and steering to push the result back into memory used earlier in the algorithm.Article: 113326
Hi, all you need is under the folder "example_design". There is the top module and an example for instantiation and under physical you have the parts for the mgt's ... BirgerArticle: 113327
Thanks,
I realized from the error that each library has signed function and
that confuses the compiler, but didn't know std_logic_arith is not a
standard and I have to use numeric_std. When would one want to use
std_logic_arith library over numeric_std?
integer'image returns the textual representation of "int", but what is
wrong with simply writing "int"? Or I guess I should ask what the
difference between two is? (Is output of "int" type integer and output
of "integer'image" type char (or is it string of integers?)?)
Vitaliy
KJ wrote:
> "Vitaliy" <m.vitaliy@gmail.com> wrote in message
> news:1165779955.314942.70530@l12g2000cwl.googlegroups.com...
> > In to_integer(signed(My_slv)), does signed relate to integer or to
> > arithmetic (I think integer, but just checking)?
> 'signed' relates to how the std_logic_vector is supposed to be interpreted.
> All by itself std_logic_vectors have no implicit 'sign' bit or any sort of
> numerical interpretation so, for example, "10000000" could mean either 128
> (decimal) or a negative number or just a collection of 8 bits of 'stuff'.
> signed("10000000") means that the bit on the left is to be interpreted as a
> sign bit and the vector is a twos complement representation of a number,
> which means that in this case we're talking about a negative number, 8 bit
> numbers can represent anything from -128 to +127.
>
> There is also the function unsigned() which says that there is no sign bit
> in the std_logic_vector argument so unsigned("10000000") is a positive
> number, in this case 128. If you're only dealing with things that cannot be
> negative there is no value in the 'sign' bit, 8 bit numbers can represent
> anything from 0 to 255.
>
> To convert the std_logic_vector to an integer via the to_integer() function
> you need to supply it with an argument that has a specific interpretation
> which is what the signed() and unsigned() functions provide.
>
> > Because there are two libraries:
> > ieee.numeric_std.signed and ieee.std_logic_arith.signed
> Don't use std_logic_arith, it has problems and it is not a standard.
>
> > So, when I specify the complete name of the library (i.e
> > ieee.numeric_std.signed), the compiler is happy.
> Since both libraries have a 'signed' function and the compiler can't tell
> the difference between the two of them by their usage, specifying the full
> path name to the function that you want is the work around. Sometimes this
> is handy but in this particular instance you'd be better off getting rid of
> std_logic_arith.
>
> By the way, since the title of the thread is ''Writing output signals to
> text file (VHDL)" I'm guessing that you actually want to write out this
> integer as text in which case you'll probably be needing to convert that
> integer to a text string in order to write it to a text file. This can be
> done with
> integer'image(My_integer)
> or combining with the conversion of the std_logic_vector to an integer....
> integer'image(to_integer(signed(My_slv))
>
> KJ
Article: 113328Hi all. I have created a simple application to test ISRs. This application is very similar to the application example provided by xilinx with EDK 8.2 for ISR testing: there is a timer and UART ISR.Press f key leds "blink" faster, while pressing s leds "blink" slower. This application works fine if loaded directly in BRAM. If I decide to create the application to be loaded in RAM(so setting .Text start address in DDR RAM) I founfd troubles. If I create .elf file and download it in RAM< via EDK no problem, all work well. But if I transform .elf file in .bin file and I download it in RAM and after jump ion RAM ISRs seem to be vanish out... Normally using this procedure (transform application in binary, load it in RAM and jump in RAM) no problem at all I had never seen before... Please any suggestion ? Thanks ! It's very important. Al.Article: 113329
"Alfmyk" <alfmyk@hotmail.com> wrote in message news:eea0f4e.-1@webx.sUN8CHnE... > Hi all. I have created a simple application to test ISRs. > > This application is very similar to the application example provided by xilinx with EDK 8.2 for ISR testing: there is a timer and UART ISR.Press f key leds "blink" faster, while pressing s leds "blink" slower. > > This application works fine if loaded directly in BRAM. If I decide to create the application to be loaded in RAM(so setting .Text start address in DDR RAM) I founfd troubles. If I create .elf file and download it in RAM< via EDK no problem, all work well. But if I transform .elf file in .bin file and I download it in RAM and after jump ion RAM ISRs seem to be vanish out... Normally using this procedure (transform application in binary, load it in RAM and jump in RAM) no problem at all I had never seen before... Please any suggestion ? > > Thanks ! It's very important. > > Al. Two things to check: (a) is cache enabled, I've had problems like this in the past where I had to disable cache to get it to work and (b) is your interrupt vector table on 64 kbyte boundary, the tool won't complain if it isn't but it won't work. I would use GDB to see if you at least get to main(). If so it's probably the IV table. -ClarkArticle: 113330
yep, that worked fine. much better than making an extra mux or relaying out my board. -Thanks "Antti Lukats" <antti@openchip.org> wrote in message news:elhhrh$2lg$1@online.de... > > "Anonymous" <someone@microsoft.com> schrieb im Newsbeitrag > news:hAXeh.13390$it.10363@tornado.southeast.rr.com... > > Turns out the hack was pretty easy. Just two lines changed in > > mem_steer.vhd. > > But obviously I don't want to have to hack the EDK code to compile my > > design. Does anyone know if there is an easy way to Import the opb_emc > > peripheral into my project to create a "myopb_emc" that I can hack without > > messing up EDK? I guess I can manually copy all the files but then I'm not > > sure how I get EDK to recognize my version from the Xilinx version? > > > > Thanks, > > Clark > > > just copy into local \pcores > and use that it will override the orginal one > > Antti > >Article: 113331
Hi,
Based on the suggestion of Gabor, I have revised Anydivider to generate
the following sample code.
Some other new features have also been added. The comparison between
DLL/PLL and TAD will also be added in the document. Topweaver
Anydivider 1.1 will be released soon after the final test.
TAD
/***********************************************************************************
Module Name : tad
Fout/Fin : 4/11
Duty Cycle : 50.00000%
Jitter : 0.82645%
Website : http://www.topweaver.com
...
***********************************************************************************/
module tad (
input rst ,
input clk ,
output reg error ,
output clko
);
reg [3:0] cnt ;
reg h ;
reg l ;
always @(posedge clk)begin
if(rst==1'b1)begin
cnt<=10;
end else begin
cnt<=(cnt>=10)?0:cnt+1'b1;
end
end
always @(posedge clk)begin
if(rst==1'b1)begin
h<=1'b0;
end else begin
h<=
(
cnt==4 ||
cnt==7 ||
cnt==10 ||
cnt>=0 && cnt<=1
)?~h:h;
end
end
always @(negedge clk)begin
if(rst==1'b1)begin
l<=1'b0;
end else begin
l<=
(
cnt==3 ||
cnt==6 ||
cnt==9
)?~l:l;
end
end
/*
h and l cannot recover from a error state automatically,
so I think an optional error indicator is needed.
*/
always @(posedge clk)begin
if(rst==1'b1)begin
error<=1'b0;
end else begin
error<=(cnt==10)?(clko):error;
end
end
assign clko = h ^ l ;
endmodule
Article: 113332Hi groups, for a CAN2B core demo : which differential input model for xilinx (spartan3E) can fit at best a 80C250 tranceiver ? I would like connect filed bus pair (canh and canl) directly to the fpga input diff. pair ? is it reallistic ? or a tranceiver is needed ? LVDS_25, MINI_LVDS ??? thanks raphArticle: 113333
rponsard@gmail.com wrote: > Hi groups, > > for a CAN2B core demo : which differential input model for xilinx > (spartan3E) can fit at best a 80C250 tranceiver ? > I would like connect filed bus pair (canh and canl) directly to the > fpga input diff. pair ? is it reallistic ? or a tranceiver is needed ? > LVDS_25, MINI_LVDS ??? > > thanks > raph You really need a CAN transceiver. CAN is not differential in quite the same way as other diff systems; CANH sits at a nominal 2.5V and goes above this for a dominant condition, CANL sits at a nominal 2.5V and goes below this for a dominant condition. Both sit at about 2.5V when recessive. Cheers PeteSArticle: 113334
Vitaliy wrote: > Thanks, > > When would one want to use std_logic_arith library over numeric_std? 'Never' would be the short answer to when you should use std_logic_arith when writing new code. If instead you're maintaining and supporting existing code that somebody else wrote and they used std_logic_arith then in order to try to avoid introducing new bugs caused by subtle differences between the two libraries you might want to continue to have this legacy code use std_logic_arith if you're making only otherwise minor changes. > > integer'image returns the textual representation of "int", but what is > wrong with simply writing "int"? Or I guess I should ask what the > difference between two is? (Is output of "int" type integer and output > of "integer'image" type char (or is it string of integers?)?) > I'm not sure what exactly you mean here or exactly what file format you're really trying to write. Try having the simulation write out the file and see what you get. If the file comes out in the format that you want, then you're done. KJArticle: 113335
Ed, > Last year, I was three steps away from the funny farm when > implementing a desgin with the x4 PCI Express core in a Virtex 4 FX > (this used MGTs). What problems are you having? > Is there a thread where you are discussing this? I have started a thread but no one commented so far... Basically, I have 2 boards , which should talk to each other using basic Aurora simplex protocol. One board has V4FX20CES2 and the other V4FX60CES4. I am testing FX20 to FX60 transmit and the problem seems to be that the receiver's PLL doesn't lock and consequently neither LANE_UP, nor CHANNEL_UP signals come up... Unfortunately, my design doesn't lend itself very well to using Xilinx debug solutions. I can't use ChipScope with BERT because it wouldn't allow for selecting which transceivers to activate, but instead activates all available on chip. This kills my 1.1V/1.2V MGT power supply, which was designed to run only a few transceivers... Another mistake I did was not to use receivers and transmitters in the same transceiver. In other words I have all of my receivers on one side of the chip and all the transmitters on the other side. The reason for this was to have potentially different reference clocks. Now, it turned out that every single Xilinx sample design involving loopback expects both receiver and the transmitter to be a part of the same transceiver. Besides, generating TX only or RX only cores frequently leads to bugs. Another issue is of course silicon stepping. The CES2 is not supported by the latest Aurora core (v2.5), and the CES4 is not supported by the v2.4. This creates a mess... Add here all the mess with calibration blocks, such as Aurora v2.4 generates core with calblock 1.2.1 and Xilinx knowledge base states that this MUST be changed to 1.2.2. The latest RocketIO wizard on the other hand uses calblock 1.1.1 for the CES2 silicon... Perhaps I shouldn't be digging into this, but the thing doesn't work and I just don't know where to look... > Also, on V4 FX, > the MGT reference voltage is .1V lower than what the datasheet > specifies if I am not mistaken...that .1V seemed to really matter too > :) :) !!!! This might have changed now that V4FX is in (or close to) > production, but double check this with Xilinx. Yeah, it should be 1.1V for CES2 and 1.2V for CES4.... Thanks, /MikhailArticle: 113336
My apologies. I posted the right page number but the wrong URL. The correct URL appears below. [... snip ...] > The Device DNA feature is described in more detail on page 246 of the > Configuration User Guide. CORRECTED URL : http://www.xilinx.com/bvdocs/userguides/ug332.pdf > You may also be interested in the associated article discussing how to > use the Device DNA. > > How to implement high-security in low-cost FPGAs > http://www.pldesignline.com/howto/showArticle.jhtml?articleID=196601422 --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3 Generation FPGAs http://www.xilinx.com/spartan3a http://www.xilinx.com/spartan3e Tel: (408) 626-7447 E-mail: steve.knapp@xilinx.com --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 113337
vits wrote: > ok I will put it like this.. > always @(*) > begin > a=b; > @(posedge clk); > c=a; > end > What does it mean. It is a bad idea. Synthesis tools will reject this code, and although a simulator will process it, nobody reading your code will be able to understand or maintain it. To help you understand it, I'll explain what it does in simulation... 1) It waits for an event on a, b or clk 2) It sets a=b 3) It waits for a rising clock edge 4) It sets c=a 5) It loops from step 1. > Neo wrote: > > vittal wrote: > > > Hi, > > > What does a statement like @(posedge clk) synthesise to? > > > if i write:- > > > > > > input b; > > > output c; > > > a=b; > > > @(posedge clk); > > > c=a; > > > > Assuming your 'a' is a reg it will systhesize to one DFF with input b > > and ouput c.Article: 113338
Hello. I've implemented few crypto algorithms in FPGA and I found this exciting - it require very different way to think rather than in case of conventional programming, etc. So I wish to continue - to implement different crypto or math or another calculation tasks in FPGA. The question is - where and how should I start. Can I apply for temporary/freelance job, if so, where should I try to do this? Thanks in advance.Article: 113339
Hi, everyone I am designing a FPGA PCB board with one DDR2 dimm memory slot. As current project will only need single dimm slot, is that mean I don't need any termination resistor on the board? Since the DDR2 will have ODT(On Die Termination) technology. Even without ODT, it should not cause signal reflection problem since this is only one dimm slot. There is no standby hi-Z on the end of transmission line. So there is no necessary to put termination resistors on the end? Normal ref design have two DDR2 Dimm Slots, I believe single slot is different. Can anyone tell this idea is correct or more things need to be concern? Thanks, ChaoArticle: 113340
Hi all, does anybody know how partial reconfiguration is carried out in new Xilinx FPGAs (Spartan3 and Virtex4)? These devices have no internal three-state buffers or bus macros, so is there a way to avoid contentions during reconfiguration?!? Thanks, AntonioArticle: 113341
"kunil" <kunilkuda@gmail.com> schrieb im Newsbeitrag news:1165797516.077446.272980@l12g2000cwl.googlegroups.com... > I'm using Picoblaze to emulate the MAC (still on early stage, I can't > tell whether it works or not). Basically, the MAC interface (MII) is > not so hard to understand and the PHY layer helps against the noise > from CAT5 cables. > > Take a look at http://www.fpga4fun.com/10BASE-T.html, and the PHY's > datasheet. The complete details about how should MAC work can be found > in IEEE802.3 whitepaper (http://standards.ieee.org/getieee802/). But I > think fpga4fun site's information is enough. > hah, look at U-BOOT, there is software bit bang MII management routine already included of course writing from scratch isnt much more complicated AnttiArticle: 113342
you could implement a decaying exponential using a LUT and to keep the LUT from getting too big, you sample the decaying exponential at just enough points, then linearly interpolate between those points Say if you wanted to estimate an exponential function with 16 bits of precision, you could sample the function at say 256 equidistant points, then the LUT would have 256 entries with 16 bit word size each. To get the value of the exponential at a point lying between the 256 you sampled, figure out which two (table entries) you are between and linearly interpolate. Kolja Sulimma wrote: > burn.sir@gmail.com schrieb: > > In an interview from 97, Bob Yannes the designer of MOS 6581 (aka > > "SID") said the following aboud the chips ASDR enveloper: > > > > "In order to more closely model the exponential decay of sounds, > > another look-up table on the output of the Envelope Generator would > > sequentially divide the clock to the Envelope Generator by two at > > specific counts in the Decay and Release cycles. This created a > > piece-wise linear approximation of an exponential. I was particularly > > happy how well this worked considering the simplicity of the circuitry. > > The Attack, however, was linear, but this sounded fine." > > > > In short, he was using an down-counter to count down from 255 down to > > some number, but he somehow made the counter to move > > pseudo-exponentially instead of linearly. > > > > Does anyone know how this works? > > Well, he explains it, doesn't he? > "sequentially divide the clock to the Envelope Generator by two at > specific counts in the Decay and Release cycles" > > So there is a linear down counter, with a clock divider in front. > Based on the counter value the clock devider value is increased. > In an FPGA you would want to control a clock enable instead of the > clock. > > > Kolja SulimmaArticle: 113343
"Roger" <enquiries@rwconcepts.co.uk> wrote in message news:457c91ed$0$8712$ed2619ec@ptn-nntp-reader02.plus.net... > I've just used the Core Generator to customise an Aurora 16 bit streaming > interface for a V2P. The resulting code has the core placed on the bottom > edge of the device when I put it on the top edge during customisation. Has > anyone else noticed this? I haven't seen this particular issue, but Xilinx has just confirmed to me that Aurora v2.5 can generate wrong code if an existing core is recustomizied. I found this when playing with a simplex core for V4FX. /MikhailArticle: 113344
You are not giving enough information. How far the boards are? Do they share a common ground? Does the second board have the same FPGA? Can you put a UART into each of the FPGAs? How quickly is quickly enough? In other words how much data in how much time? /Mikhail "alterauser" <fpgaengineerfrankfurt@arcor.de> wrote in message news:1165749051.727279.174470@n67g2000cwd.googlegroups.com... >I have a ready built design with a cyclone device offering nothing more > than some (around 5 maybe) unconnected io pins showing up on a standard > connector (pinhead, IDE-like) and like to transport out data as quickly > as possible into another board for test purposes. I am thinking of just > adding an eval board an linking them via a logical upload channel. > > The question is, how this could be done easily? I intend to use a kind > of serial connection and wire it directly - could a differential pair > be of some use here ? What data bit rates colud I expect? > > Different ideas ? > > Thanks >Article: 113345
Mark, that's very interesting. I have a configuration device on my board, but I'm not entirely sure that it's wired correctly. (I laid some traces on the board wrong and hand-soldered the parts.) I'll spend some careful time reviewing this. Thank you for your observations. Oddly, I don't see this mentioned in the cyclone datasheet. -Nevo "Mark McDougall" <markm@vl.com.au> wrote in message news:457cfcd0$0$2704$5a62ac22@per-qv1-newsreader-01.iinet.net.au... > Nevo wrote: > >> I have a board designed around the EP1C6 Cyclone device. The Quartus >> programmer is able to detect the EP1C6 on a JTAG boundary scan. I'm able >> to >> initiate programming the device over the JTAG port, but Quartus gives me >> an >> error CONF_DONE failed to go high on device 1. > > Interesting that you have these problems... > > I have very recently inherited a board which I am using for a very > different purpose to that for which it was originally intended. The > board is based on an EP2C35 and has options for both passive and active > serial configuration, as well as JTAG. The former options require > configuration devices to be plugged into DIP sockets on the board. > > Not needing auto-configuration, I dispatched with the config devices (I > actually don't *own* any) but was met with "CONF_DONE not going high" > when attempting to configure via JTAG. > > After scratching my head for some time, I eventually tried it with the > config device plugged in - and it worked! > > Now I can't for the life of me understand why this device must be > present for JTAG programming? There's a pullup on CONF_DONE (10k)and > nSTATUS (10k). > > What's more, at one stage I configured the FPGA then removed the config > device whilst still powered - and I'm pretty sure a subsequent attempt > to configure the FPGA via JTAG actually succeeded!?! > > Ultimately I need a solution because eventually I probably won't have > access to the config device (it's on a small daughterboard) and I just > don't like not knowing *why* it doesn't work!?! > > So any suggestions/insight/wild guesses would be most welcome here too! > > I guess I should add that CONF_DONE is being routed to an empty header > (for ASM programming) and also an empty socket. > > Regards, > > -- > Mark McDougall, Engineer > Virtual Logic Pty Ltd, <http://www.vl.com.au> > 21-25 King St, Rockdale, 2216 > Ph: +612-9599-3255 Fax: +612-9599-3266Article: 113346
Look at the SN65HVD1050 from Texas Instruments. It's <$1.00, and it solves all the problems (like 40V input) that the FPGA cannot handle. Peter Alfke On Dec 11, 8:05 am, rpons...@gmail.com wrote: > Hi groups, > > for a CAN2B core demo : which differential input model for xilinx > (spartan3E) can fit at best a 80C250 tranceiver ? > I would like connect filed bus pair (canh and canl) directly to the > fpga input diff. pair ? is it reallistic ? or a tranceiver is needed ? > LVDS_25, MINI_LVDS ??? > > thanks > raphArticle: 113347
Peter Alfke wrote: > Look at the SN65HVD1050 from Texas Instruments. It's <$1.00, and it > solves all the problems (like 40V input) that the FPGA cannot handle. > Peter Alfke > > On Dec 11, 8:05 am, rpons...@gmail.com wrote: >> Hi groups, >> >> for a CAN2B core demo : which differential input model for xilinx >> (spartan3E) can fit at best a 80C250 tranceiver ? >> I would like connect filed bus pair (canh and canl) directly to the >> fpga input diff. pair ? is it reallistic ? or a tranceiver is needed ? >> LVDS_25, MINI_LVDS ??? >> >> thanks >> raph > I use the TI SN65HVD232 in an existing design and I've never had a failure. Here's the TI offerings for VDD = 3.3V: http://focus.ti.com/paramsearch/docs/parametricsearch.tsp?&familyId=540&uiTemplateId=NODE_STRY_PGE_T§ionId=null&tabId=null&appId=null&viewDeviceCallingPage=null&totalCount=14&showAdditionalParameters=no¶meter=2462004422&lc=2000305&lc=2001079&lc=2200309&lc=2000368&lc=2000494&lc=2001130&lc=2001192&compare=yes&download=yes&sort=yes&customize=yes¶mResults=yes¶mCriteria=yes&familyTree=yes&military=no&baSystem=yes¶mTable=no&sortOption=&sortMode=&searchPaths=1000540&pageId=undefined&templateId=0&navigationId=0&family=analog¶mTable=no&military=no&&uiTemplateId=NODE_STRY_PGE_T§ionId=null&tabId=null&appId=null&viewDeviceCallingPage=null&resetCompare=true#sdp Cheers PeteSArticle: 113348
First picture of Tarfessock1, minus cardbus covers, now on our website for those that are interested in our little cardbus dual-FPGA development board. John Adair Enterpoint Ltd. www.enterpoint.co.ukArticle: 113349
Tommy Thorn ha scritto: > I don't have the Xilinx Spartan 3E Start Kit, but David claimed it > worked, and given that I got it running by simply supplying the correct > .ucf I strongly suspect it works. (BTW the 1600E edition which I have > has the same Micron DDR SDRAM you list above). > > If you want us to help you, you need to be more explict about what > didn't work. Did it fail to syntesize? Place and Route? Program? > > When it works you should see the LEDs blinking. To interpret them you > need to read the verilog. > > Tommy > > Hello, I'm happy; finally the original DDR opencore code working; the only thing is that the frequency is only 50 MHz because the DCM that increase the frequency from 50MHz to 100MHz don't work (I use the Xilinx system generator in the webpack 8.2) but I hope to solve the problem quickly. With the code now I write and read only half memory (I have the 32M16 instead 16M16); how I can use the full memory? I think that I must increase the coloumn address bit from 10 to 11 but I don't understand when I must do the change. May sameone help me please? Thanks for all Daniele
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