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John Williams wrote: > That's interesting - what memory configuration? We have a single > MT47H32M16CC-37E and just cannot get any sense out of it. > > Addressing looks all wrong - it reads back the same data value at 4 consecutive > dword addresses (offset 0x00 -> 0x0c) > > Writing is unreliable, if you write 0xffffffff it just randomly twiddles a few > of the top 16 bits, but not in any discernable pattern. > > I've tried more combinations that I care to admit - differential DQS on vs off, > timing params exact according to Micron datasheet vs more conservative, you name > it. Triple-checked UCF pin assignments, blah blah blah. Hi John, It sounds like your read data isn't getting aligned properly. You should try tweaking the parameters C_CTRL_Q10_DELAY and C_CTRL_DP_RDFIFO_WHICHPORT_DELAY. If your running DDR2 at 200MHz, you probably want to decrement those by 1. The parameters can be found in the mpmc2_ctrl_path_params.v file in the verilog directory. HTH. -ChrisArticle: 112851
Looks like Xilinx has pulled the old XCell journals off the website. Someone was asking about my article on downconverters in issue #38, and I sent them there since I do not have an electronic copy of the article. Well, it is gone. Anybody out there have a pdf of that article? Xilinx, why are the older Xcell journals gone? Surely the space they occupy isn't ridiculously large, and even though they refer to sunset devices, many of the articles are still applicable to the current devices.Article: 112852
Hi Antti, What ver of MPMC2 are you using? They fix OPB related bug in the october release. Antti wrote: > it seems that Xilinx has real problems getting even simple FIFOs to > work after having problems with Virtex4 coregen FIFOs I have now > succesfully wasted - about 2 weeks, because another Xilinx FIFO bug! :( > > because of REALLY low performance of the EDK multichannel DDR2 core, > OPB_MCH_DDR2 - bandwidth 50MByte/s when bursting, and below 20MByte/s > for random access I have tried to use MPMC2 IP Core > > The FPGA test design failed memory test, actually it stalled on first > read to the memory. > > After long troubleshooting with the FPGA board, DSO and finally full > system EDK simulations the problem is found - namly the fifo used in > MPMC2 read data path fails to de-assert empty flag in all cases where > the data width is 32 and not 64 I have now tried all combinations of > parameters, and all fail succesfully (of course the fifo file header > lists 32 bit as supported width). This has naturally an effect that > first OPB read to the DDR2 memory never completes. > > > Antti (not very happy about the time wasted with another Xilinx Bug)Article: 112853
PLL with what reference? What's the max. jitter allowance? First of all you need a crystal or an oscillator then try to multipply/divide it to a desired freq. If you want the pixel clock to be line-locked to some sources then you need something likes ICS1523 otherwise forget about it. IMHO something like a programmable oscillator would be suitable in your app. regards, hansman wrote: > Hi! > > I am starting a DVI Board design. The purpose is to generate DVI data > in an FPGA. interface it to an DVI transmitter from silicon image. > There are quite a lot of data formats to support with dvi. a list is > shown below. my question is ho to generate this pixel clocks, ranging > from 52MHz to 165MHz. Can anyone give a hint? > > we are using a V5LXT with integrated PLL features. > > > regards > hans > > > formatver hor FrRatePclk[MHz] Drate [Mbps] > WUXGA 1920 1200 85 281,25 6750 > WUXGA 1920 1200 75 245,25 5886 > WUXGA 1920 1200 60 193,25 4638 > WUXGA 1920 1200 50 158,25 3798 > UXGA 1600 1200 85 235 5640 > UXGA 1600 1200 75 204,75 4914 > UXGA 1600 1200 60 161 3864 > UXGA 1600 1200 50 131,5 3156 > SXGA 1280 1024 85 159,5 3828 > SXGA 1280 1024 75 138,75 3330 > SXGA 1280 1024 60 109 2616 > SXGA 1280 1024 50 88,5 2124 > XGA 1024 768 85 94,5 2268 > XGA 1024 768 75 82 1968 > XGA 1024 768 60 63,5 1524 > XGA 1024 768 50 52 1248Article: 112854
"John Williams" <jwilliams@itee.uq.edu.au> schrieb im Newsbeitrag news:newscache$auki9j$qze$1@lbox.itee.uq.edu.au... > Antti wrote: > >>>Antti wrote: >>> >>>>all attempts to get MPMC2 DDR2 designs to work have failed so far >>>>have tested on custom V4 board with single 16bit device and on ML501 >>>>all attempts failing >>> >>>And same here (mch_opb_ddr2 not MPMC) - we've spent a week trying to get >>>the >>>mch_opb_ddr2 core talking to a Micron 512Mb 32Mx16 -37E part on a PCIe >>>board - >>>no luck. The board is OK - there's a MIG design that works fine. >>> > >> OPB_MCH_DDR2 (EDK 8.2 SP2) worked for me like magic, just out of box, >> all working, no issues > > That's interesting - what memory configuration? We have a single > MT47H32M16CC-37E and just cannot get any sense out of it. > > Addressing looks all wrong - it reads back the same data value at 4 > consecutive > dword addresses (offset 0x00 -> 0x0c) > hm, this sounds like the address bus bits need be bit-reversed remember EDK is "wrong endian" it is impossible to guess if you need to reverse the bits in the busses even or odd times, just try reversing the bit order in all ext mem busses to the ddr2 AnttiArticle: 112855
"leevv" <leevv@mail.ru> schrieb im Newsbeitrag news:1164857451.935467.94790@j44g2000cwa.googlegroups.com... > Hi Antti, > What ver of MPMC2 are you using? > They fix OPB related bug in the october release. > > I am using the latest version, I will check later what version but the read datapath fifo is as broken as it can be - in all cases when its configured as 32 bit wide, its just isnt working that has the effect that OPB PIM fails AnttiArticle: 112856
Hi, I imagine it would be pretty heavy in terms of communication but I have read and not investigated the fact that some hardware in the loop simulation was availbale when doing DSP functions with Simulink. I was wondering wether there wasn't a similar mechanism for other types of application. Best regards, JF Hasson Andy a =E9crit : > Co-simulation with real hardware would take a LOT of software work for > the API calls from the simulator to the hardware, and would require a > pretty good interface between the computer runninng the simulation and > the hardware. > > You might try creating your testbenches such that they are > synthesizable, and load them into the chip too (assuming there's enough > room). You can't use assert statements or text io, but you could set > spare outputs that could be monitored with a scope or logic analyzer. > > With built-in wrap-around interfaces, the processor in the design could > run a lot of tests. > > Andy > > > jfh wrote: > > Hi, > > > > I am presently involved in a project dealing with a pretty large design > > in a Stratix II GX chip with a Nios II processor. Is there anyway to > > perform hardware in the loop simulation where the Nios II would be > > running on a board while modelsim is simulating the design ? Does > > anyone have an advice as to how simulation times could be improved when > > involving Nios II processor ? > >=20 > > Best regards, > >=20 > > JF HassonArticle: 112857
Ray Andraka wrote: > Looks like Xilinx has pulled the old XCell journals off the website. > Someone was asking about my article on downconverters in issue #38, and > I sent them there since I do not have an electronic copy of the article. > Well, it is gone. Anybody out there have a pdf of that article? > > Xilinx, why are the older Xcell journals gone? Surely the space they > occupy isn't ridiculously large, and even though they refer to sunset > devices, many of the articles are still applicable to the current devices. Judging by the looks of http://www.xilinx.com/publications/xcellonline/date.htm, with all the missing graphics, perhaps they started re-designing the archive, and either dropped the effort, or simply haven't finished it yet. I hope the latter, my first was back in #26...although, come to think of it, I'd do that circuit differently now that the parts are so much faster, and the carry logic is now tied to the LUT outputs (it was semi-independent of the LUTS in the 3000 parts). Just have to write another one... Sorry I don't have a copy of yours Ray, who'd have thought they'd take them away? I wish some of the original data books were up there too, some of the app notes in them were little gems.Article: 112858
John_H schrieb: > You can spool off multiple place & route jobs across the cluster but one > "long" place & route job will take what it takes on one computer. I use > quotes because the half hour is tiny for some of the Xilinx designs out > there. Extreme coordination is difficult to do in different rooms. > > <jetmarc@hotmail.com> wrote in message > news:1164830490.778732.110340@n67g2000cwd.googlegroups.com... > > Hi, > > > > Is it possible to run Xilinx ISE on a cluster? In the office there are > > about 20 desktops, all networked & idle, and I'm waiting for the single > > one that is implementing an ISE design since half an hour now. It > > would be great to put those 20 desktops to work and get stuff done at > > 20x. I'm asking for the impossible, right? I wouldn't mind a linux > > solution. > > > > Regards, > > Marc > > Some usefull links about linux clustering http://freshmeat.net/articles/view/458/ I am in the process of building a cluster using the open source clustering application using some old sun workstations.Article: 112859
leevv schrieb: > Hi Antti, > What ver of MPMC2 are you using? > They fix OPB related bug in the october release. > release 10202006 october 20th? BUG : PRESENT, OPB just doesnt work AnttiArticle: 112860
Hi, jfh schrieb: > I am presently involved in a project dealing with a pretty large design > in a Stratix II GX chip with a Nios II processor. Is there anyway to > perform hardware in the loop simulation where the Nios II would be > running on a board while modelsim is simulating the design ? Does > anyone have an advice as to how simulation times could be improved when > involving Nios II processor ? Have a look at Semulator (www.ger-fae.com). I have no practical experience with this system, but maybe you could use it. bye ThomasArticle: 112861
Hi guys, Does the instruction prefetch buffer in microblaze block if the required (prefetch) instruction takes more than a cycle or does it proceed to prefetch the next instruction (if that is available in a faster memory)? Thanks MuraliArticle: 112862
>> What is two months waiting time worth to you ..? >If I buy it now I can get everything setup during my Christmas holiday. >If I wait two months I could be too busy to sort things out afterward. MS will use you as a beta tester and charge you for the pleasure. Better upgrade in the summer or next christmas when other ppl have suffered the initial bugs ;) Btw, there's always the Linux way.. :p (No forced upgrades & virus headaches) >> What hinders you to use MS-XP after Vista is released..? >MS will possibly eventually stop supporting XP. >(e.g. no more service pack and security updates) >Some existing software will eventually move over to Vista. It will take more than 1 year for this to happen. And anti-virus companies are locked out from Vista (so I read). So they may have an incentive to keep MS-XP running for a long time even if MS halt updates. >Also, it is often necessary to learn new stuffs. >When you work in IT fields people, e.g. family and friends, >expect you to know everything, from changing toner of their >printers (brands you've never used before) to fixing >virus/spyware infected computer. *sign* :( Tell them XP or I don't know. I wouldn't let them tell me what enviroment I should run. >> You most likely will pay for hardware that will be consumed by Vista Bells & >> Whistles that won't benefit your vhdl/verilog processing. >Processing power is not really my biggest concern. I am using >the Xilinx Spartan-3 starter kit anyway (only a 200k FPGA). >It is purely for learning, not for real work stuffs. >But I want to make sure it can run existing tools that I am using now. It depend more on Xilinx than MS.. As long as Xilinx don't bother with Vista you won't have to either. >Glad to know that someone has actually used ISE 8.2 in 64-bit Vista :) >I don't think I will spend that much money to get a home PC with >4G RAM (2GB RAM more likely). For FPGA ram doesn't hurt :-)Article: 112863
The prefetch buffer is not doing parallel instruction fetches. It will fetch instructions sequentially but it's not tied with the execution of instructions. It will just fetch the next instruction as long as there is space in the prefetch buffer. Göran "Murali" <vmurali@mit.edu> wrote in message news:456e8ece$0$556$b45e6eb0@senator-bedfellow.mit.edu... > Hi guys, > Does the instruction prefetch buffer in microblaze block if the required > (prefetch) instruction takes more than a cycle or does it proceed to > prefetch the next instruction (if that is available in a faster memory)? > > Thanks > MuraliArticle: 112864
>> You can spool off multiple place & route jobs across the cluster but one >> "long" place & route job will take what it takes on one computer. I use >> quotes because the half hour is tiny for some of the Xilinx designs out >> there. Extreme coordination is difficult to do in different rooms. >> >> <jetmarc@hotmail.com> wrote in message >> news:1164830490.778732.110340@n67g2000cwd.googlegroups.com... >> > >> > Is it possible to run Xilinx ISE on a cluster? In the office there are >> > about 20 desktops, all networked & idle, and I'm waiting for the single >> > one that is implementing an ISE design since half an hour now. It >> > would be great to put those 20 desktops to work and get stuff done at >> > 20x. I'm asking for the impossible, right? I wouldn't mind a linux >> > solution. >Some usefull links about linux clustering >http://freshmeat.net/articles/view/458/ I wonder what the probability of cluster ISE is.. ;) (Source & Specification = secret) Anyway it's proberbly the feature considering that Intel aims for 80 core cpu in five years. For now I think the best option is to use makefiles that utilize parallism where it's possible.Article: 112865
looking for someone to program an FPGA to interface with a mitsubishi camera chip... definitely not top dollar, but if you want to practice your skills and make a few bucks, send an email. RArticle: 112866
Hello to all, I'm new in this forum; In a Project I need to write and read from a Micron DDR memory (I have a Spartan 3E starter kit wit a Micron 46V32M16); I tried to use the Opencores DDR Sdram controller and the simulation with my code was fine (the ddr controller is for a 46V16M16 but I see that the only difference is the half memory space). When I try to Implement the code in the board the controller don't work properly; I write some data in different address but I read alwais the last data writted. I use the Xilinx ISE Webpack 8.2.03i. May sameone help me please? Thanks in advance for all. DanieleArticle: 112867
Hello I would like to ask if somebody have any information about TMED (Temporal Modulation Energy Distribution) algorithm used for displaying colors on DSTN-LCDs. I have found description of these algorithm here (chapter 7.3.3): <http://www.intel.com/design/pca/applicationsprocessors/manuals/27869302.pdf> but algorithm needs TMED Matrix which isn't described ther. Have anybody any information about these matrix (how to construct that matrix, or how it is composed...)? I am constructing FPGA-based LCD controller, only for research use, and I want to implement this algorithm. Thanks for any information. Michal Strug AGH University of Science and Technology PolandArticle: 112868
On Nov 30, 4:05 am, Ray Andraka <r...@andraka.com> wrote: > Looks like Xilinx has pulled the old XCell journals off the website. > Someone was asking about my article on downconverters in issue #38, and > I sent them there since I do not have an electronic copy of the article. > Well, it is gone. Anybody out there have a pdf of that article? > > Xilinx, why are the older Xcell journals gone? Surely the space they > occupy isn't ridiculously large, and even though they refer to sunset > devices, many of the articles are still applicable to the current devices. Hi Ray, Issues 17-39 can be found here: ftp://ftp.xilinx.com/pub/documentation/xcell MichalArticle: 112869
I want to simulate my design with help of altera netlist .vo format and and timing information .sdo in generated in quartus s/w 6.0 for cyclone devic in ncverilog.I need library information of altera.where can i get it.what are the commands used for that in ncverilog.Please give information on this.Thanking you kumarArticle: 112870
"Austin Lesea" <austin@xilinx.com> wrote in message news:ekkng8$slr1@cnn.xsj.xilinx.com... > All, > > Yes, DCM's have a fixed 300 ps cycle to cycle jitter max in high > frequency mode (1000 ps cycle to cycle in low frequency mode) limit for > clock input jitter (not to exceed to lock). > Hi Guys, What spread spectrum clock violates that spec.? > > Locking to a spread spectrum referenced clocked data stream is a > requirement for the V5 MGTs (ie SATA), and yes, they do comply. > Certainly not SATA. Quote from t'internet:- Serial ATA allows the use of spread spectrum clocking (SSC), or intentional low frequency modulation of the transmitter clock. The purpose of this modulation is to spread the spectral energy to mitigate the unintentional interference of radio frequency. The modulation frequency of SSC shall be in the range of 30 KHz to 33 KHz. SATA talks about SSC with a bandwidth of maybe 2000ppm, you're not gonna get 300ps jumps with modulation of DCM compatible clocks at c.30kHz. I guess the main reason for having these PLLs in V5 is their jitter attenuation properties. Maybe it's hard for the FAE to say that because for years he's been slagging off A's PLLs. ;-) Of course, there's no reason why a design DCM can't attenuate jitter, but only down to the limit imposed by the minimum delay change. Finally, I wonder if spread spectrum clocking in this context is a complete con merely to get around the CE / FCC regulations. The amount of energy radiated is just the same, and it's arguable that spreading the spectrum makes it more likely to interfere with something than not spreading. The regulations should impose limits for power radited over a bigger bandwidth to prevent interference. Using a regulatory 120kHz band is not a good idea if you're trying to prevent interference with a 6 MHz TV signal. http://en.wikipedia.org/wiki/Spread_spectrum#Spread-spectrum_clock_signal_generation "The usefulness of spread spectrum clocking as a method of actually reducing interference is often debated" ... oh dear, that sounds ominous. Let's end this thread now! :-) Cheers, Syms. p.s. Sean, thanks for explaining what your FAE was talking about!Article: 112871
Looks like I have a museum piece! Oh, well...thanks for the info! I'll check into getting a "current" board. Thanks again! Scott "sjb" <sjb@mindspring.com> wrote in message news:9Lgbh.4783$tM1.1156@newsread1.news.pas.earthlink.net... > Hi all, > > Would anyone be able to direct me to (or provide me with) any materials > related to this board that I've got. > > http://trifs.dyndns.org/xilinx%20board.jpg > > It's an Xilinx XC3020-50 chip on a board of which I cannot locate anything > describing the layout or functions (dip switches/leds/connections/etc...). > The only markings on the board are: > > Xilinx (1994 (C))(on front side) > 0430456 rev 04 (on front side) > 1280037 Rev 02 (on back side) > > I got this board thinking it would be good to continue my education with > FPGA's, of which I'm just starting (so please go easy on me :>)). I've > tried Xilinx's site and can only get documentation on the chip itself. > Xilinx won't provide me with any support on this whatsoever! Internet > searches turn up nothing. Is this really that old of a board/chip that I > should just scrap this thing and try something else? > > Thanks for any input... > > Scott >Article: 112872
Joseph wrote: > Hi all, > > I wonder if anyone here are in the same situation as me. > I am think of buying a new PC, but wondering if I should > wait for Windows Vista become available first. > Have anyone try running FPGA tools (Xilinx Webpack, > Modelsim XE, Quartus, Cygwin) on Windows Vista beta? > Does it work okay? > Or should I get a "Vista capable" PC now and upgrade later? > (sound too much hassle to me, but it might be better?) > Thanks. > > regards, > > Joe Thanks for all the feedback. I will I will get a PC with XP and use the free upgrade only if I need to. JoeArticle: 112873
"Ray Andraka" <ray@andraka.com> wrote in message news:mUrbh.536$K15.11@newsfe17.lga... > Looks like Xilinx has pulled the old XCell journals off the website. > Someone was asking about my article on downconverters in issue #38, and I > sent them there since I do not have an electronic copy of the article. > Well, it is gone. Anybody out there have a pdf of that article? > > Xilinx, why are the older Xcell journals gone? Surely the space they > occupy isn't ridiculously large, and even though they refer to sunset > devices, many of the articles are still applicable to the current devices. Hi Ray, The wayback machine is another answer. http://www.archive.org/index.php It takes you here, eventually! http://web.archive.org/web/20030501170232/www.xilinx.com/xcell/xl38/xcell38_48.pdf Looks like Michal has saved the day anyway. HTH, Syms.Article: 112874
Marc As alternatives to a cluster: A bit out of date but worth having a look at this TechiTip http://www.enterpoint.co.uk/techitips/Previous_TechiTips/techitips_increment_synth.html. You can effectively freeze modules by this approach and cut down rebuild times for the bits you are working on. Also worth considering getting Core2 Duo machine. My inital benchmarks look very good on one I have here. Some way to help the solution I believe multi-processor support is coming too acording to previous posts. John Adair Enterpoint Ltd. - Home of Craignell. Spartan-3E in DIL format. http://www.enterpoint.co.uk <jetmarc@hotmail.com> wrote in message news:1164830490.778732.110340@n67g2000cwd.googlegroups.com... > Hi, > > Is it possible to run Xilinx ISE on a cluster? In the office there are > about 20 desktops, all networked & idle, and I'm waiting for the single > one that is implementing an ISE design since half an hour now. It > would be great to put those 20 desktops to work and get stuff done at > 20x. I'm asking for the impossible, right? I wouldn't mind a linux > solution. > > Regards, > Marc >
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