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Al schrieb: > Jim Granville wrote: > >> I needed a delay to advance an address counter after a bus strobe > >> ended. It was for a CPLD on a small plug-in board, and there was > >> no other need for a clock on the board. So, I routed the signal out > >> one pin, through a 1.5 K Ohm resistor, and into another pin. The > >> input capacitance of the pin became the C of the RC time constant. > >> This has worked well in the application. > >> > >> In your case, taking the signal through a similar external delay, and > >> then > >> bringing it back in to an AND2B1 for a pulse only on the rising edge, > >> or an XOR if you want pulses on both edges should do what you want. > >> Adjust the resistor value to get the desired time delay. > >> > >> It may also be possible to route to an unbonded IO pad with weak drive > >> and get a fair amount of delay, easily 5 ns, but probably not 10. > >> > >> Jon > > > > > > Al mentioned he wanted to avoid a PCB respin, but he could > > certainly look for spare IO pin(s), and make use of the pin path delays. > > It may even become probe-able ? > > > > -jg > > > > Hi guys, well, as Jim said I wouln't like to respin the pcb, but still > the IO delay could be used because there are some close pins which are > not used and can be easily shorted, but unfortunately I need to > instantiate a lot of these delays. So either I implement a free running > counter with this delay to generate an internal clock and then do all > the things I need, or I simply try to count on the internal routing > delay, which is quite ok on post-layout sim, but still have to try it on > the hardware! > I will post my results next week, when I will do some tests. > > Thanks to all > > Al > -- > Alessandro Basili > CERN, PH/UGC > Hardware Designer buried ring oscillator tends to run at rather high frequencies, so you may use a single unused IO pin as pin-pad-oscillator (just route pad in over inverter back to pad, may have to add always true tristate control to avoid synthesis issues) this will usually oscillate at lower frequencies, and in most cases will have constant routing without special tricks to lock the instances AnttiArticle: 112726
Jim Granville wrote: > Depending on what exactly you are using this for, you could also look > at 'margining' it - generate a tapped delay, and use a faster tap for > your delay, and check the longer one was still (just) OK, which > means the faster one was OK with margin. Sorry Jim, I didn't understand correctly what do you mean by that. > > Or, even build a calibrate phase into the tap selection. > Don't understand this either > On the 'going faster' sense, the FPGAs tend to self-compensate : A > fast process device will give, and tolerate, faster delays, and a > hot device will give, and need, longer delays. > Generally the big problems come when the delays run into the > next clock edge :) > Could you give me some reference about what you said or simply explain this to me in a more detailed way? You can contact me directly if you think this is not the place to go in details. Thanks a lot Al -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 112727
Late at night, by candle light, "Homer J Simpson" <nobody@nowhere.com> penned this immortal opus: > >"YD" <ydtechHAT@techie.com> wrote in message >news:gi9nm2lrbdh2b3l89oj6nu097g18gor66n@4ax.com... > >>>I've completely lost the point of this now. Have you? > >> Obviously. No. > >Then what has it to do with finding prime numbers on a microcomputer? > > NFI. You should know. - YD. -- Remove HAT if replying by mail.Article: 112728
"Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message news:456b5eea$1@clear.net.nz... > > Al mentioned he wanted to avoid a PCB respin, but he could > certainly look for spare IO pin(s), and make use of the pin path delays. > It may even become probe-able ? > Guys, I used an unbonded IOB to get delay once. Drove a signal to its unbonded pad and got the signal back through the IOB delay thing on the same unbonded IOB. Who knows what the delay would be from device to device, but it was good enough to deglitch a 19MHz clock. If you do this, you need to turn of the DRC in the bitgen part of the tool flow. HTH, Syms.Article: 112729
wallge wrote: > I am trying to write an SDRAM controller in VHDL for a mobile SDR SDRAM > that I want to be able to control via an FPGA on the same PCB. > I am having trouble with the verilog model. I have used both a samsung > and a micron model for the part (two compatible parts). Unfortunately > these models are not available in VHDL, and my verilog is pretty weak. > > I wondered if any one had some experience with memory models, both in > terms of using them to design memory controllers and debugging them > when they spit out spurious timing violations. > These verilog models in particular seem to send out all manner of > timing violations or functional problems that don't seem to be in line > at all with what the data sheet says regarding the timing and command > and control procedures (for doing a full page read or write, for > instance). > > Has any one else had trouble with bad/buggy models? What is the best > way to solve this problem? > What is the best way to go about designing a memory controller (I have > seen an example on Altera's website in VHDL (but it sucks), as well as > some others in open cores and one written for a homebrew graphics > accelerator card (manticore). I find the documentation and/or > functionality lacking in most of the aforementioned existing reference > designs. > > thanks Hi, I'm trying to use an AMD (Spansion) FLASH model, and it's just one BIG headache. Despite following all their advice and recompiling lots of libraries with vital2000, the model still falls over immediately in modelsim. It's really poor putting out models that just don't work, IMO. Kev P.Article: 112730
Hello,
PLL is a good way to do FM demodulation in analogue domain. What about
its use in digital domain? Why not to use a digital PLL to do FM
demodulation? what is advantages(if any) and disadvantages of this
technique?
Regards
Article: 112731it seems that Xilinx has real problems getting even simple FIFOs to work after having problems with Virtex4 coregen FIFOs I have now succesfully wasted - about 2 weeks, because another Xilinx FIFO bug! :( because of REALLY low performance of the EDK multichannel DDR2 core, OPB_MCH_DDR2 - bandwidth 50MByte/s when bursting, and below 20MByte/s for random access I have tried to use MPMC2 IP Core The FPGA test design failed memory test, actually it stalled on first read to the memory. After long troubleshooting with the FPGA board, DSO and finally full system EDK simulations the problem is found - namly the fifo used in MPMC2 read data path fails to de-assert empty flag in all cases where the data width is 32 and not 64 I have now tried all combinations of parameters, and all fail succesfully (of course the fifo file header lists 32 bit as supported width). This has naturally an effect that first OPB read to the DDR2 memory never completes. Antti (not very happy about the time wasted with another Xilinx Bug)Article: 112732
Bob wrote: > > I was just doing some HyperLynx sims and saw no difference for the LVDS and > LVDS_DT models. I thought it might have been because we're using an older > version of HyperLynx. > > Why does Xilinx include the LVDS_DT as a separate entity, in the IBIS file, > if it's not modeled properly. Well, Xilinx? > Unless I missed them, there are not any LVDS_25_DT models in the latest Spartan3E IBIS files. There is an LVDS_25_DT in the V4 models, which is modeled as an IBIS "series" element, called "rterm_100", across the pins of a regular LVDS_25 input model. This is modeled in V4 as a static resistance with tolerance, which ignores any artifacts caused by a FET termination scheme whose impedance varies with Vid and Vicm ( which I suspect is how they are implemented, but I don't know for sure ) The _DT models in the V4 IBIS files appeared to be working in HyperLynx at some point, if you look on pages 35-38 of those LVDS sims I posted last spring you can see the input swing being terminated by the LVDS_25_DT model: http://members.aol.com/fpgastuff/lvds_current.pdf ( There were problems at one point with the V2 LVDS_25_DCI models in older versions of Hyperlynx, but those modeled the split terminations by burying the terminator currents in the clamp tables ) BrianArticle: 112733
JG schrieb: > We're close to december now. > Have anyone heard when Lynuxworks will deliver? > > /JG silence...Article: 112734
On 27 Nov 2006 14:54:21 -0800, "wallge" <wallge@gmail.com> wrote: >I am trying to write an SDRAM controller in VHDL for a mobile SDR SDRAM >that I want to be able to control via an FPGA on the same PCB. >I am having trouble with the verilog model. I have used both a samsung >and a micron model for the part (two compatible parts). Unfortunately >these models are not available in VHDL, and my verilog is pretty weak. Micron certainly used to provide good VHDL models, and I wish they still did. Look for an older non-mobile equivalent for the SDRAM (same size, bus width, banks, etc and same speed grade if possible) and you'll probably find a VHDL model for it. Failing that, Hynix provide VHDL models, but I don't know if they have an equivalent part to the mobile SDRAM you are using. - BrianArticle: 112735
ma wrote: > Hello, > PLL is a good way to do FM demodulation in analogue domain. What about > its use in digital domain? Why not to use a digital PLL to do FM > demodulation? what is advantages(if any) and disadvantages of this > technique? > > Regards > > A disadvantage of the PLL technique is that it trickier to get it right compared to a discriminator. An advantage is that the threshold (knee in the SNRout vs SNRin curve) can be lower than for a discriminator. Search for the term "threshold extension" to get some ideas. JohnArticle: 112736
Symon wrote: > "Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message > news:456b5eea$1@clear.net.nz... > >>Al mentioned he wanted to avoid a PCB respin, but he could >>certainly look for spare IO pin(s), and make use of the pin path delays. >>It may even become probe-able ? >> > > Guys, > I used an unbonded IOB to get delay once. Drove a signal to its unbonded pad > and got the signal back through the IOB delay thing on the same unbonded > IOB. Who knows what the delay would be from device to device, but it was > good enough to deglitch a 19MHz clock. If you do this, you need to turn of > the DRC in the bitgen part of the tool flow. > HTH, Syms. > > What is the DRC in the bitgen? Thanks Al -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 112737
"Brian Davis" <brimdavis@aol.com> wrote in message news:1164716934.270148.320470@14g2000cws.googlegroups.com... > Bob wrote: >> >> I was just doing some HyperLynx sims and saw no difference for the LVDS >> and >> LVDS_DT models. I thought it might have been because we're using an older >> version of HyperLynx. >> >> Why does Xilinx include the LVDS_DT as a separate entity, in the IBIS >> file, >> if it's not modeled properly. Well, Xilinx? >> > Unless I missed them, there are not any LVDS_25_DT models > in the latest Spartan3E IBIS files. > > There is an LVDS_25_DT in the V4 models, which is modeled as an > IBIS "series" element, called "rterm_100", across the pins of a > regular LVDS_25 input model. > > This is modeled in V4 as a static resistance with tolerance, which > ignores any artifacts caused by a FET termination scheme whose > impedance varies with Vid and Vicm ( which I suspect is how they > are implemented, but I don't know for sure ) > > The _DT models in the V4 IBIS files appeared to be working in > HyperLynx at some point, if you look on pages 35-38 of those > LVDS sims I posted last spring you can see the input swing > being terminated by the LVDS_25_DT model: > http://members.aol.com/fpgastuff/lvds_current.pdf > > ( There were problems at one point with the V2 LVDS_25_DCI > models in older versions of Hyperlynx, but those modeled the split > terminations by burying the terminator currents in the clamp tables ) > > Brian > Brian, It was V4 that I was simulating (LVDS_25_DT). The only way I could get it to work was to manually add in a parallel 100ohm. I didn't try the DCI version. That version of termination scares me because (normally) the LVDS driver sets the common mode voltage of the pair. With DCI, it has an effect on the common-mode operating point. Xilinx LVDS -> Xilinx LVDS_DCI should work (you would think) but what about other non-Xilinx LVDS drivers into DCI? Perhaps it is our version of HyperLynx that's the problem. If so, I apolgize to Xilinx. BobArticle: 112738
hi,
currently I am working on a small hobby project with the Spartan 3
Starter Kit board from Xilinx. I use ISE WebPack 8.1i and Verilog as a
language.
Now some questions have come up during this:
1) There is a need to implement bus structures, say a 16 bit
bidirectional data bus which should connect several modules on the
highest level of the project.
1a) Do i understand it right that although there is an "inout" statement
for pins in verilog, this is of no use here, as it is working fully only
for IO-Pins on the main level, which connect to physical pins of the
FPGA itself ?
1b) Additionally there seems to be no possibility (at least for the
Spartan 3 device) that several outputs from different modules drive a
single bus line, even if care is taken for a proper assignment of 1'bz
values.
So the consequence seems to be the following (my own thought):
if one has modules
m1, m2, m3
and one is intending
m1(inout d), m2(inout d), m3(inout d)
one has in reality to do
m1(in din, out d1), m2(in din, out d2), m3(in din, out d2)
and declare a 4th module
bus_star(in sd1, in sd2, in sd3, out sdo)
and connect
sdx to dx (x from 1 to 3)
din to sdo
The 4th module I called "bus_star" as it is internally realising a star
shaped topology on the buses, wire-oring the products
(sdi and eni)
to give sdo. The signals eni here are enable signals, which dictate
which of the modules mx is allowed to "talk out" over dx into the sdo
and therefore into the din bus.
Is this correctly thought ? Or is there an easier way ?
1c) If the way in 1b) is correct, can the duplication of the buses (d1,
d2, d3) - which are in reality maybe 32 bit wide - lead to practical
problems in routing on the FPGA chip ? (Too many lines ?)
2) A second, totally unrelated question: Is there a verilog simulation
module for the static RAMs on board of Spartan3 Starter Kit ? I intend
to write a synchronous RAM-controller for these asynchronous RAMs and
would like to test it before, possibly, damaging the RAMs with wrong
code. (Or is this impossible ?)
Greetings
Jürgen
--
Jürgen Böhm www.aviduratas.de
"At a time when so many scholars in the world are calculating, is it not
desirable that some, who can, dream ?" R. Thom
Article: 112739ma wrote: > Hello, > PLL is a good way to do FM demodulation in analogue domain. What about > its use in digital domain? There are many ways to do FM demodulation in analog or digital domains. Neither way is good or bad. It depends on what is available and what are the performance requirements. > Why not to use a digital PLL to do FM > demodulation? Yes, you can do it this way if you like. what is advantages(if any) and disadvantages of this > technique? It can provide for somewhat better performance compared to a discriminator. On the other side, the complexity will be significantly higher. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.comArticle: 112740
"Al" <alessandro.basili@cern.ch> wrote in message news:ekhe85$snq$1@cernne03.cern.ch... > > What is the DRC in the bitgen? > Thanks > Al, http://catb.org/esr/faqs/smart-questions.html HTH, Syms.Article: 112741
Hi all, I'm looking for a verilog to VHDL translator. Does anybody can point me for a free tool please? thanks in advance, FrancescoArticle: 112742
Martin Thompson schrieb: > "u_stadler@yahoo.de" <u_stadler@yahoo.de> writes: > >> hi >> >> i hav a problem with edk. i created a poject a while ago and everything >> worked fine. but today i changed some c code and wanted to compile it. >> i got the following error message : >> >> Console Log) >> At Local date and time: Tue Oct 10 22:53:30 2006 >> xbash -q -c "cd /cygdrive/c/CodeGeeks/test_edk8/; /usr/bin/make -f >> system.make program; exit;" started... >> system.make:173: *** target pattern contains no `%'. Stop. >> >> Done! >> >> >> i tired to reinstall everything but it didn't help. any ideas somebody? >> > > EDK is incompatible with the new version of cygwin make. I got around > this by deleting the make.exe from the cygwin install - EDK puts it's > version back in after that. Hi, I'm facing that particular problem right now. Unfortunatley my (updated) cygwin installation resides in c:\Xilinx\EDK\cygwin, thus EDK can't put its version back in. Does anybody know, which version of cygwin/make comes with EDK 8.2i? I could possibly revert the update manually... to avoid reinstalling EDK :-/ Thanks in advance, cheers /ChrisArticle: 112743
Christian Schleiffer schrieb: > Martin Thompson schrieb: > > "u_stadler@yahoo.de" <u_stadler@yahoo.de> writes: > > > >> hi > >> > >> i hav a problem with edk. i created a poject a while ago and everything > >> worked fine. but today i changed some c code and wanted to compile it. > >> i got the following error message : > >> > >> Console Log) > >> At Local date and time: Tue Oct 10 22:53:30 2006 > >> xbash -q -c "cd /cygdrive/c/CodeGeeks/test_edk8/; /usr/bin/make -f > >> system.make program; exit;" started... > >> system.make:173: *** target pattern contains no `%'. Stop. > >> > >> Done! > >> > >> > >> i tired to reinstall everything but it didn't help. any ideas somebody? > >> > > > > EDK is incompatible with the new version of cygwin make. I got around > > this by deleting the make.exe from the cygwin install - EDK puts it's > > version back in after that. > > Hi, > I'm facing that particular problem right now. Unfortunatley my (updated) > cygwin installation resides in c:\Xilinx\EDK\cygwin, thus EDK can't put > its version back in. > Does anybody know, which version of cygwin/make comes with EDK 8.2i? I > could possibly revert the update manually... to avoid reinstalling EDK :-/ > > Thanks in advance, cheers > /Chris 8.2 SP2 make ver 3.79.1 anttiArticle: 112744
Christian Schleiffer schrieb: > Martin Thompson schrieb: >> "u_stadler@yahoo.de" <u_stadler@yahoo.de> writes: >> >>> hi >>> >>> i hav a problem with edk. i created a poject a while ago and everything >>> worked fine. but today i changed some c code and wanted to compile it. >>> i got the following error message : >>> >>> Console Log) >>> At Local date and time: Tue Oct 10 22:53:30 2006 >>> xbash -q -c "cd /cygdrive/c/CodeGeeks/test_edk8/; /usr/bin/make -f >>> system.make program; exit;" started... >>> system.make:173: *** target pattern contains no `%'. Stop. >>> >>> Done! >>> >>> >>> i tired to reinstall everything but it didn't help. any ideas somebody? >>> >> EDK is incompatible with the new version of cygwin make. I got around >> this by deleting the make.exe from the cygwin install - EDK puts it's >> version back in after that. > > Hi, > I'm facing that particular problem right now. Unfortunatley my (updated) > cygwin installation resides in c:\Xilinx\EDK\cygwin, thus EDK can't put > its version back in. > Does anybody know, which version of cygwin/make comes with EDK 8.2i? I > could possibly revert the update manually... to avoid reinstalling EDK :-/ > > Thanks in advance, cheers > /Chris I just discovered that it seems to work with make-3.80. You can get it from here: http://cygwin.paracoda.com/release/make/make-3.80-1.tar.bz2 /ChrisArticle: 112745
Bob wrote: > > I didn't try the DCI version. That version of termination scares me because > (normally) the LVDS driver sets the common mode voltage of the pair. > It scares me too! [1,2] > Perhaps it is our version of HyperLynx that's the problem. If so, > I apolgize to Xilinx. I haven't had access to HyperLynx for a few years now, but Mentor's support abstracts say you need better than V7.5 to use terminations modeled using the IBIS series elements: " "TechNote mg42698: HyperLynx: Differential DCI internal termination " If this behavior is modeled using the clamp table currents, " HyperLynx can account for the internal termination during simulation. " If however the model is calling a series IBIS resistor model to model " the internal termination, HyperLynx V7.5 and eqarlier will ignore it. " The work around in this case would be to place a differential " "quick terminator", of the same value, between the two IC pins instead. " Note that modeling a non-linear, on-die, FET termination as an outside-the-package, ideal, resistive termination might produce HyperLynx simulation results that "are not helpful to anyone" :) Brian [1] post describing LVDS DCI modulation artifacts http://groups.google.com/group/comp.arch.fpga/msg/62fe69c2f44f4e68 [2] Xilinx Answer Record 13012, plots of DCI LVDS modulation artifacts http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=13012Article: 112746
"bm" <nospam@nospam.fr> escribió en el mensaje news:4568035a$0$29316$426a74cc@news.free.fr... > http://www.sump.org/projects/analyzer/ > > "hypermodest" <hypermodest@gmail.com> wrote in message > news:1164394012.977690.199470@m7g2000cwm.googlegroups.com... >> Hi. >> Is there any ready open source (or not so open) logic analyzers based >> on FPGA + (S|D)RAM? >> I mean, we need to connect bunch of wires to FPGA, record all samples >> to RAM and download it somehow to PC. >> Also, is there any good starting points and/or known pitfalls, e.g. >> what should I read first? >> Thanks in advance. >> > > I do recommend it. Nice tool. Cheers -- Posted via a free Usenet account from http://www.teranews.comArticle: 112747
Hi folks, Does anyone knows when will the ML555 (LXT/8x PCIe) board be officially released (and available for ordering ?). Thanks in advance, Steven DerrienArticle: 112748
I'm using Model for Actel. When performing pre-synthesis simulation in ModelSim, I observe 'unknown' signals in design. However, these signals are defined in simulation which I made in other simulator. Thanks for helpArticle: 112749
Steven Derrien schrieb: > Hi folks, > > Does anyone knows when will the ML555 (LXT/8x PCIe) board be officially > released (and available for ordering ?). > > Thanks in advance, > > Steven Derrien I bet ML505 should be released next week, dont know about 555 Antti
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