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What is different between general micro-controller and FPGA soft processor? Speed? Cost? Easy to use? Easy to learn? I am curiouse if the soft controller will replace the regular microcontroller? Xilinx said they implement 32-bit RISC controller with a lot of benefits. Would that replace ARM?Article: 73251
Hi All, I am good in Digital System design with Verilog and VHDL Coding. But I never implemented myself any design on FPGA. Now I am trying to learn myself the issues related to FPGA implementation. So I would like to know what are the important topics I need to learn..especially implementation issues like configuring your FPGA for the respective Board environments, configuring I/O's etc. As I have a Spartan board with Xilinx tool, I would like to learn all the issues related to implementation. So Please help regarding this... Thanks. Best Regards, VLSI StudentArticle: 73252
I'm having a hard time finding out the exact status of these PROMs. Anyone sampling or buying them yet? My local disty is checking for me, but I'm trying to get an answer quickly. Thanks, RobArticle: 73253
OOPS! http://www.xilinx.com/products/virtex4/capabilities/designsec.htm We have AES 256 bit key in THIS generation! (---twice the key length of our nearest competitor with similar features) Oh, and to be compliant with the federal standard for encryption, you are not allowed to use non-volatile key storage (must allow 'zeroization'). Non volatile key storage is trivial to reverse engineer. I asked our F/A lab how long it would take to read the value of EM polyfuses (invented by IBM), and they repplied "less than a hour." Now, if you had poly fuses AND volatile battery backed RAM, that would be the best possible implementation. Those that have secrets worth less than $10,000 would use the poly fuses (how much it costs to decap the device, and read the fuses), and those with secrets worth more than $10,000 would use the $1 lithium coin cell BBRAM solution. To remember all of the new neat features is tough. http://www.xilinx.com/products/virtex4/capabilities.htm (but here is a 'cheat' sheet with links) Austin Austin Lesea wrote: > IgI, > > See below, > > Austin > > IgI wrote: > >>>> Yup. Not his time. Aside, do we have enough BRAM? >> >> >> >> I always make use of all BRAMs available in a device, but because >> there is a >> new primitive IDELAY available in V4 the need for synchronization >> FIFOs will >> be reduced. This new feature will be very useful. I do have several >> questions regarding the usage of ILOGIC primitive. What is the tab >> resolution delay? I remember a number of 80ps from the presentation, >> but I'm >> not sure I heard correctly? > > > Yes, you did. 78 ps. > > I believe this delay depends on the speed-grade > >> of the device, right? > > > Nope. It is derived from a feedback loop from the reference clock, so > it never changes. > >> >> In order to use variable IDELAY, IDELAYCTRL has to be instantiated. >> Lets say >> I would like to use IDELAY for two groups of data signals, one running at >> 166MHz and the other at 200MHz. Do I have to instantiate two IDELAYCTRL >> primitives and connect REFCLK of each IDELAYCTRL to the same reference >> clock >> or do I have to connect 166MHz clock to one IDELAYCTRL and 200MHz >> clock to >> other IDELAYCTRL. > > > The reference clock is always 200 MHz for the delay elements, and has > nothing at all to do with the speed the interface needs to run at. One > ref clock for the delay is all it takes for the whole part. > > Is there any correlation between the REFCLK and clocks of > >> the incoming data signals at all, or is REFCLK completely unrelated to >> any >> other clock? > > > Completely unrelated, unless by chance you need a 200 MHz clock to do > something else. > >> >> I saw there is a "Fourth-Generation Design Security" build into V4. Is >> external battery still needed, or have you implemented some sort of >> non-volatile memory (EEPROM) inside V4 for the keys? > > > Triple 56 bit key DES, battery bcked key RAM, just like V2 and V2P. It > is the fourth generation/technology part to have this core. Even though > single and double key DES is no longer considered secure (by the federal > gov't), triple DES with three differing keys is still considered safe > for the time being. Next generation will require AES (in two years). > >> >> What's the size of bitstream file compared to the previous generation of >> devices? > > > Uh, depends on the device. Generally speaking, an LX25 is ~ 2500 system > gates (whatever that means) and is 7,819,520 bits long. A 2VP20 (~2000 > system gates) is 8,214,560. V4 has fewer BRAM bits than Virtex II Pro > in ratio to CLBs, and the LX family has no PPC or MGTs. > > Or, to put it another way, we haven't done anything radical to save > config bits in V4. > >> >> Regards, >> Igor Bizjak >> >>Article: 73254
kathy wrote: > What is different between general micro-controller and FPGA soft > processor? > > Speed? On the same process, a soft processor will always be slower, but soft processors have other benefits : You can deploy more than one very easily, and can choose the resource level. The FPGA process tends to be leading edge, so that reduces the actual speed penalty - but at the cost of static Icc. Soft processors can also readily connect to the other logic > Cost? On a pure silicon basis, a soft processor will always be more expensive. BUT if you already have the FPGA for other tasks, the _incremental_ cost of a soft processor can be quite low. > Easy to use? Improving all the time :) A weakness of soft processors, is code memory/boot memory has to be separate. That's a lot of PCB traces, and much EMC... A valid alterative would be to use an external Flash Microcontroller, with a high speed serial data interface to the FPGA, for example. > Easy to learn? Reasonably, given that you will be doing the FPGA Logic design as well. > I am curiouse if the soft controller will replace the regular > microcontroller? Complement is a better description than replace, tho I am sure the Marketing Depts of the FPGA vendors would claim otherwise.... It is quite common to see a number of microcontroller and micro-processor/DSP working together in a single product. > Xilinx said they implement 32-bit RISC controller with a lot of > benefits. Would that replace ARM? Xilinx also offer PowerPC cores. If the Soft processor was a universal solution, ask yourself why would they bother doing that ? -jgArticle: 73255
The distributor just got back to me. Parts are available but lead time is 12 weeks.. "Robert Sefton" <rsefton@abc.net> wrote in message news:2que3fF13p5n5U1@uni-berlin.de... > I'm having a hard time finding out the exact status of these PROMs. Anyone > sampling or buying them yet? My local disty is checking for me, but I'm > trying to get an answer quickly. > > Thanks, > Rob >Article: 73256
In article <cid123$821@cliff.xsj.xilinx.com>, Austin Lesea <austin@xilinx.com> wrote: >OOPS! > >http://www.xilinx.com/products/virtex4/capabilities/designsec.htm > >We have AES 256 bit key in THIS generation! (---twice the key length of >our nearest competitor with similar features) >Oh, and to be compliant with the federal standard for encryption, you >are not allowed to use non-volatile key storage (must allow >'zeroization'). Non volatile key storage is trivial to reverse >engineer. I asked our F/A lab how long it would take to read the value >of EM polyfuses (invented by IBM), and they repplied "less than a hour." Also, if you DO want a lot of non-volatile memory which is protected, you can bootstrap.... Have the configuration contain compiled-in random key (store_key). The configuration is also encrypted, with a different random key (config_key). Upon loading, the bitfile decryptor has config_key stored in the battery backed SRAM cells. It decrypts the bitfile and loads the configuration. Now the configuration can use store_key to decrypt data in the large flash chip which is used for the non-volatile store. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 73257
"kathy" <yong.qin@ecadusa.com> wrote in message news:c18c5dac.0409161222.314d5c59@posting.google.com... > What is different between general micro-controller and FPGA soft > processor? > Just to add to what Jim says, a big difference is that soft processors don't go obsolete. Cheers, Syms.Article: 73258
Physical means. There are quite a few companies in Taiwan that specialize in this. There might also be noninvasive imaging techniques similar to those used for MRI or perhaps even Van Eck phenomena. Dallas Semiconductor is pretty familiar with these attacks since they specialize in designing NVRAM devices that clear themselves in such scenarios. Actually, I would sincerely hope that the key isn't held in any sort of "memory"; even ROM. If I were designing such a system I would make sure that the "key" was an emergent property of some structure with lower spatial complexity than the key itself (for example, a sequential circuit computing the collatz sequence). I suppose an even better protection technique would be to base the key on some analog, physical property of the chip itself combined with a per-chip "offset" value. For example, a function of the ratio of oscillation frequencies of two pairs of inverters, plus some offset value "X" which is computed during the testing process and then flashed onto the chip (ie each chip has a different oscillatior value due to process variations as well as a different X -- but they all sum up to the same universal decryption key). I hadn't thought of this before; this would actually be pretty hard to extract. But at the same time I doubt that Xilinx is hiding any NVRAM in their chips; if their process allowed for that they would probably offer some of it to their customers -- even a few bytes would still be handy. I suppose that this is my core point: as long as every Xilinx chip of a given type is exactly the same with respect to the part of it that performs decryption, I'm highly suspicious of any design security claims. And if you're going to go so far as adding nonvolatile storage to a chip, well, you might as well go the Actel route and save your customers the hassle of putting an extra chip on board just to serve up the configuration data. This also means that a breach of one particular device's security doesn't compromise the IP of every single customer at the same time because of a shared secret: Xilinx is putting all of their customers in the same high-profile basket. - a Austin Lesea <austin@xilinx.com> writes: > Adam, > > And how do you propose to read out the bits from the key memory? > > Austin > > Adam Megacz wrote: > >> Hey Nick, 441 Soda Hall just isn't the same without you.... =( >> >>>Thus you have the encrypted bitfile loading on the Virtex lines. >> Well, IMHO it doesn't qualify as encryption when the chip itself -- >> which you're giving to your customers -- contains the decryption key. >> >>>Personally, I think the V4 version is easily good enough for >>>protecting a $10,000 secret, and I could probably be OK comfort wise >>>protecting a $100,000 secret. >> $10k (loaded cost) will buy you about half a month of a mediocre >> hardware engineer's time. I doubt many of Xilinx's customers' designs >> are that simple. Even <$100k designs probably constitutes an >> unimportant fraction of their market. >> But I agree with your estimate. I could envision the task of >> extracting the decryption key from a Xilinx part as being a feasible >> project with around $300k of funding and the right team to pull it >> off. >> So, basically, I wouldn't trust the security of any serious >> commercial >> design to Xilinx's obfuscation. Now lawyers, on the other hand... =) >> - a --Article: 73259
Hi Glen, Rick, I can see what you guys are saying. Thanks for the clarification about semantics. I think that the bit about packing is very interesting. I agree that the dependence of routing resources on packing is dependant on the amount of routing and logic resources left over but I guess that the more efficiently the logic is packed, the slower we will hit the threshold that would place severe constraints on routing and mapping. Correct me if I am wrong. Also, the part on the use of carry chains could produce routing problems make sense. However, if the carry chain is not used, more routing resources would need to be used to link the carries from 1 cell to another. For arithmetic rich operations, this could be a problem. It seems to me that relationship between routing resources and packing efficiency is pretty strong across most aplications. Again, feel free to refute me. Thanks. tEd glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote in message news:<cicins$usv$1@gnus01.u.washington.edu>... > Ted wrote: > > > I have 3 burning, if fundamental questions about FPGA architecture. > > > 1) When the term routing is used, does it include the switch block > > multiplexers and the interconnections (Long wires, short wires etc.)? > > Different architectures are different, but I would include everything > except LUT data bits, carry chain configuration, and IOB configuration. > Inputs to LUT's, FF's, and IOB's usually come from mux's, which are, > to me, routing. > > > 2) When packing it done well, can I say that LUTs are packed close to > > each other so the amount of routing resources used is less? > > Maybe. If you use the carry chain that fixes the relative position > of many CLBs. That can restrict the routing such that close > packing increases the routing problems. > > Also, as the device gets full and routing resources get low, the > router can make some very long routes, including through LUTs. > > If the device is not very full, there isn't much constraint on > the routing and some routers will spread the logic out. > > > 3) For Altera FPGAs (eg. Stratix versions), how are the LUTs > > implemented? For Xilinx, its generally distributed RAM. For Altera > > which only uses coarse-grain memory, this can't be the case so what is > > the alternative? > > It is, I believe, a course array of RAM, DSP, and LAB blocks, > where the LAB blocks internally contain LUT's and routing > resources, and then routing between the different kinds of blocks. > > http://www.altera.com/literature/hb/stx/ch_2_vol_1.pdf > > -- glenArticle: 73260
Dear All, I am looking for a way to quantify the amount of routing resources used on a Xilinx FPGA (Spartan chip). Does anybody know of a software that can do that. I understand that Jbits handles bitstreams. However, is it able to compile these statistics? It will be brilliant if I am able to find out the amount and type of connections used for certain types of components. Of course FPGA editor and floor planner does that graphically but clicking on more than 1 component normally creates a jumble of arrows such that it is difficult to extract anything useful. Numbers that could be automatically extracted will be exactly what I need. If no direct and convinient method exists, suggestions of indirect, heuristical techniques would also be welcomed. tEdArticle: 73261
Thanks Vikram, My Modelsim libraries are compiled.I have the unisim,simprim,XilinxCorelib libraries compiled and they are under the directory C:\modeltech5.7g\xilinx_libs\unisim C:\modeltech5.7g\xilinx_libs\simprim C:\modeltech5.7g\xilinx_libs\XilinxCoreLib Earlier the libraries were pointing to Xilinx Libraries and hence I was seeing those errors.Now I see new errors like... # ** Error: inrom_translate.vhd(641): Unknown identifier: init. ###### inrom_translate.vhd(653): INIT => '0' # ** Error: inrom_translate.vhd(653): Unknown identifier: init. ###### inrom_translate.vhd(665): INIT => '0' # ** Error: inrom_translate.vhd(665): Unknown identifier: init. ###### inrom_translate.vhd(1936): INIT => '0' # ** Error: inrom_translate.vhd(1936): Unknown identifier: init. ###### inrom_translate.vhd(1948): INIT => '0' # ** Error: inrom_translate.vhd(3531): Unknown identifier: x_roc ###### inrom_translate.vhd(3533): port map (O => GSR); # ** Error: inrom_translate.vhd(3533): Unknown component name ###### inrom_translate.vhd(3534): NlwBlockTOC : X_TOC # ** Error: inrom_translate.vhd(3534): Statement cannot be labeled. # ** Error: inrom_translate.vhd(3534): Unknown identifier: x_toc ###### inrom_translate.vhd(3535): port map (O => GTS); # ** Error: inrom_translate.vhd(3535): Unknown component name ###### inrom_translate.vhd(3537): end Structure; # ** Error: inrom_translate.vhd(3537): VHDL Compiler exiting # ERROR: C:/Modeltech_5.7g/win32/vcom failed. Thanks for any ideas/help, Sridhar Vikram Pasham <Vikram.Pasham@xilinx.com> wrote in message news:<41496A9A.3204C56B@xilinx.com>... > Looks like Simprim libraries are missing which includes components like > x_lut2, x_ff etc. Post Ngdbuild or post PAR back annotated simulation files > have these libraries included. Unisim libraries are behavioral models while > Simprim libraries are gate level models. Did you compile these libraries? > > This answer record will guide you on doing backannotated simulations. > http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=10177 > > Regards > Vikram > > Sridhar Hegde wrote: > > > Hi, > > > > I am designing a simple ROM in VHDL and following is the code for > > it.Xilinx ISE 6.2i doesn't seem to have any issues synthesizing the > > design to a Virtex 2 chip(xc2v4000) or translating/mapping/routing the > > design(Implementation process). > > > > When I use the test bench created by HDL bencher to see the results, > > in Modelsim, a behavioral simulation shows be proper results but a > > post translate simulation or anything beyond that like a Post Map or a > > Post place and route simulation show a U on all output pins and > > Modelsim gives me a number of warnings about "Unbound components" > > shown below.. > > > > Im stuck at this design phase and would appreciate any help from the > > VHDL gurus out there...Heres the code:- > > > > ----------------------------------------------------------------------- > > > > library IEEE; > > use IEEE.STD_LOGIC_1164.ALL; > > use IEEE.STD_LOGIC_ARITH.ALL; > > -- Uncomment the following lines to use the declarations that are > > -- provided for instantiating Xilinx primitive components. > > --library UNISIM; > > --use UNISIM.VComponents.all; > > > > entity inrom is > > Port ( en : in std_logic; > > clk : in std_logic; > > dout : out std_logic_vector( 15 downto 0); > > valid : out std_logic; --valid data is present on output when 1 > > reset : in std_logic > > ); > > end inrom; > > > > architecture rtl of inrom is > > > > type array_rom is array (15 downto 0) of std_logic_vector( 15 downto > > 0); > > signal myarray : array_rom; > > signal valid_sig:std_logic; > > signal dout_sig : std_logic_vector(15 downto 0); > > signal clk2: std_logic; > > > > begin > > > > myarray(0) <= x"0000"; > > myarray(1) <= x"0000"; > > myarray(2) <= x"0000"; > > myarray(3) <= x"003C"; > > myarray(4) <= x"0000"; > > myarray(5) <= x"0000"; > > myarray(6) <= x"0064"; > > myarray(7) <= x"0000"; > > myarray(8) <= x"0000"; > > myarray(9) <= x"000A"; > > myarray(10) <= x"0000"; > > myarray(11) <= x"0000"; > > myarray(12) <= x"003C"; > > myarray(13) <= x"0000"; > > myarray(14) <= x"0000"; > > myarray(15) <= x"0064"; > > > > process( reset,clk) > > variable romvar:natural range 0 to 15; > > > > begin > > if reset = '1' then > > dout_sig <= (others=>'0'); > > valid_sig <='0'; > > romvar :=0; > > > > elsif (clk'event and clk='1') then > > if en='1' then > > dout_sig <= myarray (romvar); > > valid_sig<='1'; > > romvar :=romvar + 1; > > else > > dout_sig <= myarray (romvar); > > valid_sig<='0'; > > end if; > > end if; > > end process; > > > > dout <= dout_sig; > > valid <=valid_sig; > > end rtl; > > ------------------------------------------------------------------------- > > Warnings given by Modelsim: > > > > do inromtbw.ndo > > # ** Warning: (vlib-34) Library already exists at "work". > > ###### inrom_translate.vhd(443): ); > > # WARNING[1]: inrom_translate.vhd(443): No default binding for > > component: "x_mux2". (No entity named "x_mux2" was found) > > ###### inrom_translate.vhd(455): ); > > # WARNING[1]: inrom_translate.vhd(455): No default binding for > > component: "x_ff". (No entity named "x_ff" was found) > > ###### inrom_translate.vhd(468): ); > > # WARNING[1]: inrom_translate.vhd(468): No default binding for > > component: "x_xor2". (No entity named "x_xor2" was found) > > ###### inrom_translate.vhd(472): ); > > # WARNING[1]: inrom_translate.vhd(472): No default binding for > > component: "x_zero". (No entity named "x_zero" was found) > > ###### inrom_translate.vhd(476): ); > > # WARNING[1]: inrom_translate.vhd(476): No default binding for > > component: "x_one". (No entity named "x_one" was found) > > ###### inrom_translate.vhd(714): ); > > # WARNING[1]: inrom_translate.vhd(714): No default binding for > > component: "x_lut2". (No entity named "x_lut2" was found) > > ###### inrom_translate.vhd(2994): ); > > # WARNING[1]: inrom_translate.vhd(2994): No default binding for > > component: "x_lut3". (No entity named "x_lut3" was found) > > ###### inrom_translate.vhd(3128): ); > > # WARNING[1]: inrom_translate.vhd(3128): No default binding for > > component: "x_lut4". (No entity named "x_lut4" was found) > > ###### inrom_translate.vhd(3203): ); > > # WARNING[1]: inrom_translate.vhd(3203): No default binding for > > component: "x_or2". (No entity named "x_or2" was found) > > ###### inrom_translate.vhd(3341): ); > > # WARNING[1]: inrom_translate.vhd(3341): No default binding for > > component: "x_tri". (No entity named "x_tri" was found) > > ###### inrom_translate.vhd(3450): ); > > # WARNING[1]: inrom_translate.vhd(3450): No default binding for > > component: "x_inv". (No entity named "x_inv" was found) > > ###### inrom_translate.vhd(3533): port map (O => GSR); > > # WARNING[1]: inrom_translate.vhd(3533): No default binding for > > component: "x_roc". (No entity named "x_roc" was found) > > ###### inrom_translate.vhd(3535): port map (O => GTS); > > # WARNING[1]: inrom_translate.vhd(3535): No default binding for > > component: "x_toc". (No entity named "x_toc" was found) > > # vsim -lib work -t 1ps inromtbw > > # Loading C:/Modeltech_5.7g/win32/../std.standard > > # Loading C:/Modeltech_5.7g/win32/../ieee.std_logic_1164(body) > > # Loading C:/Modeltech_5.7g/win32/../ieee.std_logic_arith(body) > > # Loading C:/Modeltech_5.7g/win32/../std.textio(body) > > # Loading C:/Modeltech_5.7g/win32/../ieee.std_logic_textio(body) > > # Loading C:/Modeltech_5.7g/win32/../vital2000.vital_timing(body) > > # Loading C:\Xilinx6\vhdl\mti_se\simprim.vcomponents > > # Loading C:/Modeltech_5.7g/win32/../vital2000.vital_primitives(body) > > # Loading C:\Xilinx6\vhdl\mti_se\simprim.vpackage(body) > > # Loading work.inromtbw(testbench_arch) > > # Loading work.inrom(structure) > > # ** Warning: (vsim-3473) Component 'romvar_madd_n0000_inst_cy_5_0' is > > not bound. > > # Time: 0 ps Iteration: 0 Region: /inromtbw/uut File: > > inrom_translate.vhd > > # ** Warning: (vsim-3473) Component 'valid_sig_1' is not bound. > > # Time: 0 ps Iteration: 0 Region: /inromtbw/uut File: > > inrom_translate.vhd > > # ** Warning: (vsim-3473) Component 'mmux_n0001_inst_mux_f5_130' is > > not bound. > > > > I can not use a Core generated ROM for this design due to some > > restrictions I have in my other codes..Sorry for a rather long mail > > and thanks in advance for any help!!Article: 73262
Hi Vikram, This is my second message...I figured out the error and thought I would reply here just in case some one else encountered the same issue "Component is not bound/unbound" warnings come (as you said) when Modelsim cant find the simprimlibraries.I had the libraries compiled as I said but I was pointing to the wrong ones. I needed to point to the one under C:\Xilinx6\vhdl\mti_se\simprim instead of C:\Modelsim5.7g\xilinx_libs\simprim.. As soon as I fixed this, I got results as expected...Thanks for the guidance.Now I can proceed with my design!! Best Regards, Sridhar Vikram Pasham <Vikram.Pasham@xilinx.com> wrote in message news:<41496A9A.3204C56B@xilinx.com>... > Looks like Simprim libraries are missing which includes components like > x_lut2, x_ff etc. Post Ngdbuild or post PAR back annotated simulation files > have these libraries included. Unisim libraries are behavioral models while > Simprim libraries are gate level models. Did you compile these libraries? > > This answer record will guide you on doing backannotated simulations. > http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=10177 > > Regards > Vikram > > Sridhar Hegde wrote: > > > Hi, > > > > I am designing a simple ROM in VHDL and following is the code for > > it.Xilinx ISE 6.2i doesn't seem to have any issues synthesizing the > > design to a Virtex 2 chip(xc2v4000) or translating/mapping/routing the > > design(Implementation process). > > > > When I use the test bench created by HDL bencher to see the results, > > in Modelsim, a behavioral simulation shows be proper results but a > > post translate simulation or anything beyond that like a Post Map or a > > Post place and route simulation show a U on all output pins and > > Modelsim gives me a number of warnings about "Unbound components" > > shown below.. > > > > Im stuck at this design phase and would appreciate any help from the > > VHDL gurus out there...Heres the code:- > > > > ----------------------------------------------------------------------- > > > > library IEEE; > > use IEEE.STD_LOGIC_1164.ALL; > > use IEEE.STD_LOGIC_ARITH.ALL; > > -- Uncomment the following lines to use the declarations that are > > -- provided for instantiating Xilinx primitive components. > > --library UNISIM; > > --use UNISIM.VComponents.all; > > > > entity inrom is > > Port ( en : in std_logic; > > clk : in std_logic; > > dout : out std_logic_vector( 15 downto 0); > > valid : out std_logic; --valid data is present on output when 1 > > reset : in std_logic > > ); > > end inrom; > > > > architecture rtl of inrom is > > > > type array_rom is array (15 downto 0) of std_logic_vector( 15 downto > > 0); > > signal myarray : array_rom; > > signal valid_sig:std_logic; > > signal dout_sig : std_logic_vector(15 downto 0); > > signal clk2: std_logic; > > > > begin > > > > myarray(0) <= x"0000"; > > myarray(1) <= x"0000"; > > myarray(2) <= x"0000"; > > myarray(3) <= x"003C"; > > myarray(4) <= x"0000"; > > myarray(5) <= x"0000"; > > myarray(6) <= x"0064"; > > myarray(7) <= x"0000"; > > myarray(8) <= x"0000"; > > myarray(9) <= x"000A"; > > myarray(10) <= x"0000"; > > myarray(11) <= x"0000"; > > myarray(12) <= x"003C"; > > myarray(13) <= x"0000"; > > myarray(14) <= x"0000"; > > myarray(15) <= x"0064"; > > > > process( reset,clk) > > variable romvar:natural range 0 to 15; > > > > begin > > if reset = '1' then > > dout_sig <= (others=>'0'); > > valid_sig <='0'; > > romvar :=0; > > > > elsif (clk'event and clk='1') then > > if en='1' then > > dout_sig <= myarray (romvar); > > valid_sig<='1'; > > romvar :=romvar + 1; > > else > > dout_sig <= myarray (romvar); > > valid_sig<='0'; > > end if; > > end if; > > end process; > > > > dout <= dout_sig; > > valid <=valid_sig; > > end rtl; > > ------------------------------------------------------------------------- > > Warnings given by Modelsim: > > > > do inromtbw.ndo > > # ** Warning: (vlib-34) Library already exists at "work". > > ###### inrom_translate.vhd(443): ); > > # WARNING[1]: inrom_translate.vhd(443): No default binding for > > component: "x_mux2". (No entity named "x_mux2" was found) > > ###### inrom_translate.vhd(455): ); > > # WARNING[1]: inrom_translate.vhd(455): No default binding for > > component: "x_ff". (No entity named "x_ff" was found) > > ###### inrom_translate.vhd(468): ); > > # WARNING[1]: inrom_translate.vhd(468): No default binding for > > component: "x_xor2". (No entity named "x_xor2" was found) > > ###### inrom_translate.vhd(472): ); > > # WARNING[1]: inrom_translate.vhd(472): No default binding for > > component: "x_zero". (No entity named "x_zero" was found) > > ###### inrom_translate.vhd(476): ); > > # WARNING[1]: inrom_translate.vhd(476): No default binding for > > component: "x_one". (No entity named "x_one" was found) > > ###### inrom_translate.vhd(714): ); > > # WARNING[1]: inrom_translate.vhd(714): No default binding for > > component: "x_lut2". (No entity named "x_lut2" was found) > > ###### inrom_translate.vhd(2994): ); > > # WARNING[1]: inrom_translate.vhd(2994): No default binding for > > component: "x_lut3". (No entity named "x_lut3" was found) > > ###### inrom_translate.vhd(3128): ); > > # WARNING[1]: inrom_translate.vhd(3128): No default binding for > > component: "x_lut4". (No entity named "x_lut4" was found) > > ###### inrom_translate.vhd(3203): ); > > # WARNING[1]: inrom_translate.vhd(3203): No default binding for > > component: "x_or2". (No entity named "x_or2" was found) > > ###### inrom_translate.vhd(3341): ); > > # WARNING[1]: inrom_translate.vhd(3341): No default binding for > > component: "x_tri". (No entity named "x_tri" was found) > > ###### inrom_translate.vhd(3450): ); > > # WARNING[1]: inrom_translate.vhd(3450): No default binding for > > component: "x_inv". (No entity named "x_inv" was found) > > ###### inrom_translate.vhd(3533): port map (O => GSR); > > # WARNING[1]: inrom_translate.vhd(3533): No default binding for > > component: "x_roc". (No entity named "x_roc" was found) > > ###### inrom_translate.vhd(3535): port map (O => GTS); > > # WARNING[1]: inrom_translate.vhd(3535): No default binding for > > component: "x_toc". (No entity named "x_toc" was found) > > # vsim -lib work -t 1ps inromtbw > > # Loading C:/Modeltech_5.7g/win32/../std.standard > > # Loading C:/Modeltech_5.7g/win32/../ieee.std_logic_1164(body) > > # Loading C:/Modeltech_5.7g/win32/../ieee.std_logic_arith(body) > > # Loading C:/Modeltech_5.7g/win32/../std.textio(body) > > # Loading C:/Modeltech_5.7g/win32/../ieee.std_logic_textio(body) > > # Loading C:/Modeltech_5.7g/win32/../vital2000.vital_timing(body) > > # Loading C:\Xilinx6\vhdl\mti_se\simprim.vcomponents > > # Loading C:/Modeltech_5.7g/win32/../vital2000.vital_primitives(body) > > # Loading C:\Xilinx6\vhdl\mti_se\simprim.vpackage(body) > > # Loading work.inromtbw(testbench_arch) > > # Loading work.inrom(structure) > > # ** Warning: (vsim-3473) Component 'romvar_madd_n0000_inst_cy_5_0' is > > not bound. > > # Time: 0 ps Iteration: 0 Region: /inromtbw/uut File: > > inrom_translate.vhd > > # ** Warning: (vsim-3473) Component 'valid_sig_1' is not bound. > > # Time: 0 ps Iteration: 0 Region: /inromtbw/uut File: > > inrom_translate.vhd > > # ** Warning: (vsim-3473) Component 'mmux_n0001_inst_mux_f5_130' is > > not bound. > > > > I can not use a Core generated ROM for this design due to some > > restrictions I have in my other codes..Sorry for a rather long mail > > and thanks in advance for any help!!Article: 73263
Dear Steven:
Thanks for ur reply and Kens's artical. Now, i have removed reset from DFF which need to be placed into IOB. Just like the followings.
However, ISE map "r_dbus_o" into "FDS"(D and SR are connected with "s_dt_cdio_o" ) not "FD", this still prevent DFF placed into IOB. Oh, god save me.
---------IN ISE6.2.03i ----------
always @ ( posedge SYSCLK ) begin
r_dbus_t <= s_dt_cdio_t ;
r_dbus_o <= s_dt_cdio_o ;
end
assign DBUS = ( r_dbus_t == 1'b1 ) ? 64'hzzzz_zzzz_zzzz_zzzz : r_dbus_o ;
// synthesis attribute MAX_FANOUT of r_dbus_t is 1;
---------------------------------
regards,
seyior
Article: 73264On Thu, 16 Sep 2004 14:37:07 -0700, Austin Lesea <austin@xilinx.com> wrote: >OOPS! > >http://www.xilinx.com/products/virtex4/capabilities/designsec.htm > >We have AES 256 bit key in THIS generation! (---twice the key length of >our nearest competitor with similar features) > >Oh, and to be compliant with the federal standard for encryption, you >are not allowed to use non-volatile key storage (must allow >'zeroization'). Non volatile key storage is trivial to reverse >engineer. I asked our F/A lab how long it would take to read the value >of EM polyfuses (invented by IBM), and they repplied "less than a hour." Note that FIPS compliant 'zeroization' requires actively setting all the bits in the key to zero. Turning the power off and hoping that the bits change isn't the same as zeroization. This implies the following: 1. Either Xilinx isn't performing zeroization (and I haven't found anything in the data sheet that indicates that they do perform FIPS compliant zeroization). Hmmm. 2. Or, Xilinx have added a low voltage detector and a have developed a ram with a 'clear' input, or have developed a ram cell that always goes to a known state as the supply drops. 3. Or, zeroization is possible, but can only happen when the user overwrites the key with zeros, which is only possible when the power is on (and wouldn't be too hard to circumvent in a real product). Please note: I'm commenting on Austin's use of the (well defined) term 'zeroization'. I don't mean to imply that I think that there is anything wrong with the security of the Xilinx parts. Regards, AllanArticle: 73265
Andre Bonin wrote: > Hello all, > I have an algorithm i would like to implement in an fpga. I have no > idea of knowing how many times the 'while' loop should run. > But doing something like this seems to be illegal in verilog. Any ideas > of how i can get around this? How could i implement a c-style loop in > verilog? You need to get used to thinking in terms of hardware, instead of how many times something will loop. Think about how you would build it using TTL gates and flip-flops, for example. Once you do that, consider what your loop is doing. Making things run fast in hardware means doing many things in parallel. C style loops don't naturally do that. Hope this helps, -- glenArticle: 73266
Kumar Vijay Mishra wrote: > I am getting a continuous stream of 16-bit data. In every clock cyle I > have to sort 32-size array. When I have sorted the array in ascending > order, I want to choose 24th number only. In the next clock cycle, I > get a new no added to my array while the first number gets out of the > array. The new array that I get is to be sorted again and he 24th > position number is to be taken out. > So, in every clock cycle, I get a new data (in an array of 32 16-bit > numbers) (with the oldest data getting deleted from this array) and in > the same clock cycle, I need to have the 24th-position data available > to me for further processing. If it really works that way there is just about only one way to do it, because you must do everything in one clock cycle. You need to compare the number coming in against all the others in the list, except the one going out, and arrange the new data ready to clock in on the next cycle. Startup is a little complicated, as you must make sure that it fills up the right way. 32 16 bit registers, appropriate comparators and such should fit easily in a medium sized FPGA. -- glenArticle: 73267
Hi, there: My ASIC library doesn't allow 1) input pins of any cells left unconnected, 2) multiple input pins of same cell connected to same signal net. Though 2nd appear quite abscure, since these multiple input pins waste too many vdd/gnd cells. My library has special tie-high/low cells to cater these circumstances, but what are the constants in Design Compiler that I can set in order to comply with these two rules? ThanksArticle: 73268
Look at Lattice's XPLD. They have in each XPLD 2 PLL's that you can use at will, and you don't consume logic to build the DLL. Regards On 16 Sep 2004 08:46:23 -0700, sch@elpro.at (Kriki) wrote: >I need to program a digital PLL in a CPLD. > >I tryed to use an external Clock Generator @ 24.576 MHZ, but the data >signal is not exactly that frequency. > >So can anyone help me with that problem ???Article: 73269
To answer your multiple posting, I'm using a TCXO from CMAC, they do them down to about 0.5 ppm. Niv. "Hal Murray" <hmurray@suespammers.org> wrote in message news:WKKdnXmYUeQJbNXcRVn-hg@megapath.net... > >I need accurate frequency, I'm using a 2 ppm osc as source and need to > >maintain that. > > That's an interesting spec. What sort of crystal/box are you using > to get that level of stability? How expensive? > > That got me thinking... Many applications that need good accuracy > also need low jitter. DLL type designs have lots of jitter. (For > some value of "lots".) > > Is it interesting to use something like a DLL in an unlocked mode? > That is, run a calibration phase then lock it at the best tap. > > The idea is to kill the tap-changing jitter in trade for timing > wander as temperature or Vcc changes while still getting most > of the timing fixup from the DLL calibration step. > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam. >Article: 73270
There is no answer ! Can I have to consider than one more time, Altera implement a new fonction that doesn't work ? "io" <tartampion@nullepart.com> a écrit dans le message de news: cibhf2$ukd$1@s5.feed.news.oleane.net... >I try to use Quartus In-system Memory Editor but it doesn't work. > > I have implement a RAM and I can read data from it. > But the problem is that I can't modify data like I want. > If I change a word, my data is corrupt and if I update all the memory, all > my RAM began corrupted. > > Did someone have ever make work that tools ? > For me it's seems to be at prototype state. >Article: 73271
> > You have the required pullups and pulldowns ? > 1k up for TMS, TDI and TDO and 1k down for TCK. > Plus there is whealth of pins that require a fixed connection. > Documented in the *.RPT file as ASCII. > > Yes, i have all pullups and pulldowns, all signal except TDO look good, i mean levels. All grounds and supplies are also OK. Anyway instead of solving problem, i will change logic family to MAX3000A, which better suits my needs (3.3V)Article: 73272
Hi, I've finally managed to design a simple test peripheral which uses the IPIF master & slave attachment to the PLB bus (plb_ipif version 2). Simulations are OK but there's a performance problem : when performing a burst read, it seems that the IPIF stores the whole burst and then write it back to the IP. Doing so, the performance is divided by 2 (better case). Is there a way to configure the IPIF to be faster or do I have to manage the PLB bus myself ? Thanks a lot for your help StéphaneArticle: 73273
Hi friends.. In my board design of FPGA, I Want to interface the Spartan-3 xc3s400-tq144 with PC/104 ISA bus. I'm new to the interface design. Pls give some suggestion. Regards Senthil Chett.Article: 73274
Does anyone know where I can buy a EPM7160SLC84 in the UK?
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