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This loop should compile fine in Synplify. Andre Bonin wrote: > Hey all, I'me trying to convert a C algorithm to Verilog using Quartus > II Web edition. > > The following for loop doesn't compile because it says its not of > constant loop time. > > What i really need is to be able to calculate the loop time "on the fly". > > Can VHDL or Verilog do this? or is this a limitation? > > > Thanks > Error: Verilog HDL For Statement error at XXXXXXXX.v(49): must use only > constant expressions in terminating conditions > > ---- Error at while loop - > integer X = 0; > always > begin > while( X < 30 ) > begin > X = X + 1; > end > endArticle: 73376
Ken McElvain wrote: > This loop should compile fine in Synplify. I'me using quartus2. What is synplify? > > Andre Bonin wrote: > >> Hey all, I'me trying to convert a C algorithm to Verilog using Quartus >> II Web edition. >> >> The following for loop doesn't compile because it says its not of >> constant loop time. >> >> What i really need is to be able to calculate the loop time "on the fly". >> >> Can VHDL or Verilog do this? or is this a limitation? >> >> >> Thanks >> Error: Verilog HDL For Statement error at XXXXXXXX.v(49): must use >> only constant expressions in terminating conditions >> >> ---- Error at while loop - >> integer X = 0; >> always >> begin >> while( X < 30 ) >> begin >> X = X + 1; >> end >> end > >Article: 73377
Here's one way to do it in "interactive" batch mode. On the first run out of the chute, I'll add start the waveform viewer, and add all the signals I want to see, format them, etc. Then, do a File->Save->Format Save the "wave.do" file. Next, make a *.do file similar to below ---------Start of do file ---------- vlog -f file_collection.f vsim work.Test view wave #opens the wave viewer do C:/Projects/wave.do #loads the signals you want to see run -all #execute full sim --------- End of do file ---------- Because you're using the sim in interactive mode, you'll need to do is issue a "$stop" in your testbench instead of the "$finish" Then, in the modelsim window, just execute >> do myfile.do SM "FGreen" <fastgreen2000@yahoo.com> wrote in message news:d31579b8.0409201330.6ca48820@posting.google.com... > I'm rather new at Modelsim, so please bear with me. > Couldn't find answer to these questions, in manual or in search. > > I'm running simulation in batch mode. (Currently just using command > window, > will migrate to Cygwin later.) My batch file is something like this: > > vlog -lint tb_test.v > vsim -c tb_test -wlf test.wlf < test.do > > So, the simulation runs fine, spits messages, etc. > > When viewing the waveform, what's the best way to bring up the waves, > with > the pre-selected signals (or not) without having to open the main > Modelsim > windows? > > I find it tedious to open the main window, open the waves, select > dataset, then format, especially because I'm in debugging stage where > I change the testbench a lot. There has to be a better way than > having to go through a series of mouse clicks. I can tolerate the > main window opening, as long as I can have the waves show up with > signals loaded... am I making sense? > > Any help would be appreciated.Article: 73378
--You would need a board for sure, there are plenty of options, pick and
choose what suits your needs and budget. Xilinx.com-->Products-->Development
Boards has a nice search feature
--ISE Webpack is not a good option for this kind of work, since that only
supports 2VP2 (which means no PowerPC) and does not have CoreGen either
-ISE BaseX could be considered if you are going to use not bigger than
2VP7 part. That could save you some $$.
-If you are going to use bigger than 2VP7 part, you need to have ISE
Foundation
BaseX and Foundation both run on Linux.
--For the PowerPC development, EDK is pretty self sufficient which includes
the GNU toolchain for IBM405. It does not include any RTOS (except a small
Xilinx kernel, XMK). If you want to run VxWorks on PPC, you need to get that
separately, ditto for other supported RTOSs'
--Other tools?
--A simulator (ModelSim XE) and Chipscope Pro for in-system debugging
would be good idea too.
Rgds
Neeraj
"Tuukka Toivonen" <tuukkat@killspam.ee.oulu.finland.invalid> wrote in
message news:slrnckm1nk.1ng.tuukkat@s-inf-pc92.oulu.fi...
> Hi all. I'm looking for FPGA for real-time video processing.
> The requirements are not yet fixed, but I think something
> like Xilinx Virtex-II Pro from XC2VP7 to XC2VP30 would be
> a good choice. PCI interface would be nice so that I could
> plug the card in and transfer uncompressed video frames into
> the card and get compressed frames back. Something like,
> say 100 Mbit/s Ethernet, might also work but then it would
> use pretty much all of the bandwidth.
>
> Also, I want to do development on Linux (Debian) host,
> so the tools should run on that. Running Linux on the
> FPGA PowerPCs sounds like a nice idea too.
>
> My question is: what hardware and software do I need?
> Looks like I need:
> - The development board. Prospective candidates are
> Alpha Data's ADM-XPL and Amirix boards. Something
> from Avnet might also do, except that it appears
> they don't support Linux. Not sure about Alpha Data
> either. And then there's Xilinx's
> ML310 which appears to be a complete computer with
> PCI slots and Ethernet. But it might have some bandwidth
> problems, unless I connect camera directly into the
> PCI slots in the board.
> - Hardware development tools. Are there other alternatives
> than ISE Foundation/BaseX? And are there differences
> between the two except that the latter supports
> devices only up to XC2VP7?
> - Software development tools. Should I get them from the
> board vendor or is it possible to use them from third
> party? I have found EDK from Xilinx and the TimeSys SDK.
> What is the difference between the two? Other alternatives?
> - Operating system for the PowerPC inside the FPGA. Does
> this come with the development kits or would I need
> to get one separately?
> - Something else?
>
> I hope the questions were not too silly, but I haven't
> done any work with FPGAs before.
Article: 73379Responding to comments on device availability and fab partnership . . Stratix II Availability: Altera has a track record of shipping devices on schedule. We realize the importance of delivering products on schedule to minimize our customers' risk to deliver their end products. Altera has worked with TSMC, worldwide foundry leader, on 90nm process technology since 2001 and taped out >10 test chips prior to Stratix II. As a result, we were able to ship our first 90nm Stratix II device, the EP2S60, 6 weeks ahead of schedule. Stratix II development boards are available today. 4 additional Stratix II devices are on schedule to roll out before the end of the year and the final Stratix II device is on track for a Q1-05 introduction. And Stratix II devices are on boards at over 60 customers. 90-nm Fab Partnership A key component of any architectural selection decision involves probability of success in rolling out the devices. I agree with the general assertion made by my colleague that past success does influence this probability. Past success is based on picking the right fab partner, investing heavily with that partner, and staying on primary process nodes with mainstream processes. Argument was made that success on a proven 90 nm partner UMC (with Spartan 3) explains why Virtex 4 is low-risk. The fact that Xilinx's technical spokesperson has repeatedly highlighted that all of Spartan-3's availability woes are "demand related" and not "supply related" is also relevant here. Altera will continue to invest all process related resources with a single partner, TSMC. This partner continues to demonstrate process excellence at every leading node. By investing with a single fab partner rather than diluting investment across multiple partners, Altera will continue to stay ahead of the process curve. Altera will stick with mainstream processes and release product on them when they are ready for mainstream production. All 90-nm products will include low-K; now that low-K is mainstream and provides significant upside in terms of power and performance, it is clearly an advantageous feature. Triple oxide deviates from standard processing which seems ill-advised. Spartan-3 delivery problems are not a demand issue. Spartan 3 unit shipments are below Spartan 2 unit shipments (I base this on publicly highlighted numbers) - perhaps Xilinx could point out the specifics here. And Spartan 3 unit shipments are ~ 1/4th Cyclone unit shipments (both parts rolled out at the same time). Clearly high-volume families are architected to expand the FPGA market; claiming "best rollout ever" or "demand problem" just doesn't line up with the facts. And even if Spartan-3 90-nm issues were suddenly solved, this UMC "success" would only be relevant if Virtex 4 used the exact same fab process and fab partner for production. Current rumors in the trade press highlight that Xilinx is evaluating other sources for their 90-nm products (no doubt based on the tremendous success with the Spartan-3 rollout). I look for Xilinx to comment on which fab will be used for producing Virtex 4 parts. I would strongly prefer to leave this site to the technologists. Altera will continue to respond though with marketing oriented postings when the facts are not properly presented or when marketing questions arise. Dave Greenfield Sr. Director of Product Marketing High Density FPGAs Altera CorporationArticle: 73380
Responding to comments on features and performance . . . Stratix II Features: Altera has led the innovation to introduce high-density, high-performance FPGAs. In 2002, the Stratix family won EDN Innovation of Year award over Virtex-II Pro. This year, we introduced the Stratix II family which includes a new logic structure, a whole new set of features, and breakthrough performance. Altera is the first FPGA company to integrate dedicated SERDES and DPA circuitry into our devices for high-speed source-synchronous I/Os (LVDS, LVPECL, etc.). Altera is the first FPGA company to introduce dedicated DQ and DQS circuitry into our devices for external memory interface support (DDR, DDR2, etc.). Altera is the first FPGA company to introduce a new flexible logic structure the Adaptive Logic Module (ALM). Stratix II Logic Efficiency: Altera studies highlighted that had we implemented the traditional logic structure on 90nm process technology, we would have seen minimal gains on performance and cost (over 130 nm products). Stratix II devices utilize new highly flexible adaptive logic modules (ALMs) that are optimized for 90nm process technology to maximize logic efficiency and performance. The inputs of a single ALM can be flexibly divided between the two output functions, allowing wide input functions to run fast and narrow input functions to efficiently use remaining resources. Stratix II is the industry's only FPGA with such a flexible logic structure, allowing it to provide 50% faster performance and consume 25% less logic comparing to other FPGAs. Stratix II Design Security: The Stratix II devices come with both the non-volatile key and volatile key storages for design security. Altera chose to only market the non-volatile key solution because it delivers the optimal features and functionality for customers. A volatile key solution requires a battery to backup the key when the power is off, which is not ideal as it increases the cost of the solution, board manufacturing complexity and is simply less reliable. Significant protections is put in place to make sure the non-volatile key is secure within the Stratix II FPGA. Reading poly fuses on a 9 layer 90nm process is not trivial. It cannot be done in "less than an hour". Our feature has been designed to make it as painful as possible to crack, and has been verified by independent security consultants. Since all crypto systems are crackable, including ones by our competitors, it is a question of how much money and time one is willing to spend on this endeavor. The battery solution for a volatile key provides no data integrity. What is the purpose of having security if you can over write a "supposedly secure design" (a design that has been loaded with an encrypted bit-stream) with any other design. You can do this in Virtex 4 devices which have a security key on board. A hacker can load a new design into a device with a security key onboard without knowing the key that resides onboard. He can also change the original key itself. A poly fuse system provides data integrity since the only bit-stream you can load is the encrypted bit-stream. A hacker trying to load any other bit-stream will be not be successful in loading the device and cannot change the original design. A 256 bit key in this situation provides minimal added security beyond a 128 bit key. If you are going to spend the money to attempt cracking either Altera or Xilinx devices by reverse engineering the silicon, the entire method is dependent on how difficult you make the reverse engineering rather than the key length. Since no known method exists for cracking AES, a brute force attack is the only way to attempt to crack the key. A 128 bit key length is more than sufficient for this. Performance Stratix II performance on average is 50% faster than Stratix performance details are well documented at our web-site (http://www.altera.com/products/devices/performance/per-index.html). Virtex 4 literature highlights that performance doubles, yet we only see two concrete examples on this bulletin board, neither substantiating the claim. It doesn't appear there has been any change to the Virtex CLB since Virtex-II (except removing half of the distributed RAM in Spartan-3 and Virtex 4). Without changes to the core architecture (logic module), I question how performance can double and power be cut in half (we have not yet run our benchmark suite though). Altera will be happy to release benchmark information on the 2 architectures once available. Dave Greenfield Sr. Director of Product Marketing High Density FPGAs Altera CorporationArticle: 73381
There was a thread about ring oscillators recently. I tried to build one in a Xilinx V2Pro and found, as I suspected, that the ISE tools collapsed the ring of inverters into a single inverter. I'm sure there is a simple way to preserve the logic from being pruned by the tools by means of a constraint, but I can't figure it out. What's the secret, short of routing each inverter's output to an IOB to prevent pruning? The frequency of the oscillator is not critical so I'm not worried about placement or routing. -KevinArticle: 73382
Responding to comments on 90-nm power . . . Claims here are challenging to understand. It appears that Xilinx suggest power goes down by 50% at the same time performance doubles, due mainly to a triple oxide process (benefit to leakage power) and embedding hard IP (benefit to dynamic power). Let's take a look at these claims. Leakage and triple oxide: Xilinx claims triple oxide is used in CRAM to reduce leakage current by 50%. In Stratix II, CRAM accounts for 5% of total leakage. Does this imply CRAM leakage in Virtex devices had been 50% of the chip's total leakage? Current collateral also glosses over the tradeoffs of triple oxide, which the rest of the industry (including the likes of Intel, TI, IBM, etc.) have analyzed and have deemed too risky and too costly at 90nm for the small benefit provided. Triple oxide adds die size (larger transistors). It also requires ~4 more wafer processing steps. Both of these aspects increase the wafer cost. Both of these factors also reduce yield. Because there are now not two, but three different oxides it takes longer to tighten up the process and thus deliver sustainable, regular yields (i.e. guaranteed delivery). Finally, rapid yield enhancement requires driving wafer volume, but the limited use of triple oxide at either UMC or some other potential foundry highlights that Virtex 4 may be stuck driving the triple oxide yield enhancement alone. Dynamic power and the benefits of embedding more hard IP: Xilinx suggests dynamic power goes down by a factor of 7x by embedding hard IP. The Virtex 4 documentation suggests the new multipliers run up to 500 MHz and consume only 57 uW/MHz. In the SX55 device (with 512 multipliers), that is 15 W of dynamic power just for DSP. Dynamic power for the core, RAMs, and I/O, and then leakage are on top of this. I'll assume the 7x factor likely doesn't apply here. Low-k helps reduce dynamic power by about 10% and gives a boost to performance of ~ 10% (part of Altera's power reduction arsenal). It doesn't look like Virtex 4 will get this low-K benefit. There are other process techniques besides triple oxide to reduce leakage power. For instance, Altera implements different Vt's using different implants to reduce leakage power. This is how we get a low leakage CRAM. It is safer than triple-oxide, and yields leakage power reductions that are quite similar. We also judiciously apply non-minimum length transistors. Configuration RAM is a solved problem since there is no performance requirement, we can use both these techniques to greatly reduce sub-threshold leakage. The Stratix II ALM is power-friendly. (1) It reduces the number of logic levels, so we can use lower leakage routing transistors and maintain speed. (2) It reduces the amount of routing needed by absorbing more logic into the larger logic functions, so we replace the still-somewhat-leaky routing transistors with low-leakage CRAM cells. My assessment is that Virtex 4 is primarily trying to get power reductions through process techniques, while most of the semiconductor industry has concluded this is not sufficient -- you also need to get gains at the architecture level. Dave Greenfield Sr. Director of Product Marketing High Density FPGAs Altera CorporationArticle: 73383
In article <6fO3d.84788$D%.79178@attbi_s51>, Kevin Neilson <kevin_neilson@removethiscomcast.net> wrote: >There was a thread about ring oscillators recently. I tried to build one in >a Xilinx V2Pro and found, as I suspected, that the ISE tools collapsed the >ring of inverters into a single inverter. Maybe the KEEP attribute would work? http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/cgd/cgd0125_78.html -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 73384
Might be a power pin. Or a GCLK. Usually PACE is better spotting hardware issues than we are. What is your part number? "kathy" <yong.qin@ecadusa.com> wrote in message news:c18c5dac.0409201324.4d5106ad@posting.google.com... > I am trying to follow the Xilinx "Introduction to Programmable Logic". > I try to implement in FPGA. But when I try to assign I/O pin in PACE's > DOL. I found I can not assign Loc=P36. The drop-down list does not has > the entry. I am using Webpack6.2i for Spartan 3. > > Why?Article: 73385
Hi Sebastian, > well i hope some time soon they make it somehow "standard", cause > right now altera just lost (again! cause it's the second time in few > months i see it happening) against xilinx, cause the boss said it was > already too much trouble having generates for ASIC and for FPGA, to > have another one for another family we were just evaluating (we'd need > to modify lots of files). I'm sorry to hear of this design loss. In the future, please contact your Altera FAE for help converting the design. Our FAEs have access to tools that facilitate design conversion by re-targeting Xilinx-specific features to equivalent structures in Altera devices. Conversion success rate is fairly high, especially when the considerable performance and logic density advantages of Stratix II and Cyclone over the competition is taken into account. For the do-it-yourselfers out there, we provide documentation at http://www.altera.com/products/software/switching/x/qts-x2a_migration.html on how to switch from using Xilinx-based devices and software to our devices and Quartus. AN307 gives detailed descriptions on how to re-target architecture sepecific features. And as Rick suggests in another post, isolating device-specific features in your design at the HDL level is a useful design technique that eases the process of porting to devices (within the same company's products, or to other company's products). > And also because we werent seeing any gains > in LUTs (the same design was using more LUT4 in altera than on > xilinx) On average across a suite of 97 designs, we find that Stratix requires 9% fewer logic elements than does Virtex-II Pro. See http://www.altera.com/literature/wp/wp_stx_logic_efficiency.pdf for details. You mention "LUT4" and not LEs, so I'm wondering whether you are taking into account the "register packing" factor. The Stratix & Cyclone architectures were designed to support LEs where both the LUT and FF are used, even for unrelated functions. You must be careful when comparing logic counts -- in our experience, Quartus does a much better job than competing tools at packing combinational logic with registers. This register packing functionality can be tuned to more or less aggressive modes in Quartus, trading off (to some degree) performance and wiring for logic density. By setting "Auto Packed Registers" to "Minimize Area" results in the tightest packing. In the default flow, Quartus only begins to aggressively pack your logic when you start running out of logic elements. Also, make sure you compare logic counts after running through Quartus and ISE -- while 3rd party synthesis tools can provide reasonable estimates, you don't know the real answer until you run through the back-end CAD tools. So when comparing logic element counts between two competing products, make sure you're looking at the final result (half "slices" in Xilinx, LEs in Startix, ALUTs in Stratix II). Of course, it's also possible your design falls into the group (roughly 20% of designs) that experience better densities on Virtex than Stratix. Hope to have you as a customer in future! Paul Leventis Altera Corp.Article: 73386
Andre Bonin a ้crit: > Ken McElvain wrote: > >> This loop should compile fine in Synplify. > > > I'me using quartus2. What is synplify? QuertusII doesn't like VHDL while loops. I replaced one with a for loop and an exit statement and it worked OK. I don't know if it is the same with Verilog while loops though. -- ____ _ __ ___ | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le - | | | | | (_| |_| | Invalid return address: remove the - |_| |_|_|\__|\___/Article: 73387
Stephen Williams <spamtrap@icarus.com> wrote: : Steven K. Knapp wrote: : > You may be able to remove the user reset completely. Is your user reset : > only to guarantee the initial state of the design (a common ASIC practice)? : > If so, you can eliminate this reset signal, which will potentially make you r : > design significantly smaller. : > : > Xilinx FPGAs have an internal Global Set/Reset signal that is asserted at : > the end of the configuration process, guaranteeing the initial conditions. : This can't be good advice. I have a co-worker who does that often, : and I get to write drivers for the resulting chips. It bugs me a lot. : Using the configuration process to initialize things to a safe : startup state is nice and all (especially for "roms" and the like) : but RESET is *not* the same thing. Stephen, is there a way to tell iverilog ( or other verilog simulators) to use registers with a default initial value, so no "initial" assignment would be needed. Only registers with a non default values would be needed to be set explicitly. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 73388
Hi, I'm trying to use mutliple clock domains in DK2. I followed the tutorial PDF found on celoxica.com and it compiled without problem. (I used the touchscreen.hcc and reverb.hcc) When loading the bitstream I only get the touchscreen to work. Both applications work by themselves. OliverArticle: 73389
Got it. Got help from systemc.org Needed to include the path of libstdc++ to LD_LIBRARY_PATH aaruljain@gmail.com (Aarul Jain) wrote in message news:<15891236.0409200122.52291b5b@posting.google.com>... > I was finally able to compile the code. But when i tried to run the > code I got the following message, > > --> run.x > ld.so.1: run.x: fatal: relocation error: file run.x: symbol cerr: > referenced symbol not found > Killed > Exit 137 > > > Does anyone have a clue to what must have gone wrong. > > The code compiled successfully as > --> gmake -f Makefile.gcc > g++ -O3 -Wall -I. -I.. -I../../../include -c display.cpp > g++ -O3 -Wall -I. -I.. -I../../../include -c numgen.cpp > g++ -O3 -Wall -I. -I.. -I../../../include -c main.cpp > g++ -O3 -Wall -I. -I.. -I../../../include -c stage1.cpp > g++ -O3 -Wall -I. -I.. -I../../../include -c stage2.cpp > g++ -O3 -Wall -I. -I.. -I../../../include -c stage3.cpp > g++ -O3 -Wall -I. -I.. -I../../../include -L. -L.. > -L../../../lib-gccsparcOS5 -o run.x display.o numgen.o main.o stage1.o > stage2.o stage3.o -lsystemc -lm 2>&1 | c++filt > > Regards > AARUL JAIN > > > Javier Castillo <jcastillo@opensocdesign.com> wrote in message news:<Xns95645803872B9jcastilloopensocdesi@193.147.184.15>... > > aaruljain@gmail.com (Aarul Jain) wrote in > > news:15891236.0409130014.5e7a0662@posting.google.com: > > > > > Hello > > > > > > I am trying to learn systemc. Systemc was already installed in one of > > > the servers and I am using Solaris 2.8 with gcc 3.3 > > > > > > I am trying to run example programs from the installation directory. > > > However when I run make i get error message > > > > > > -------compiles the code and generates .o -------- > > > ---- > > > g++ -I. -I.. > > > -I/_TOOLS_/dist/systemc-2.0.1/sparc-sun-solaris2.8/include -L. -L.. > > > -L/_TOOLS_/dist/systemc-2.0.1/sparc-sun-solaris2.8/libS/gcc-3.2.2 -o > > > run.x source.o sink.o fft.o main.o -lsystemc -lm 2>&1 | c++filt > > > Undefined first referenced > > > symbol in file > > > CoolLog::CoolLog[in-charge](char const*, char*, > > > bool)/_TOOLS_/dist/systemc-2.0.1/sparc-sun-solaris2.8/libS/gcc-3.2.2/li > > > bsystemc.a(sc_main.o) ld: fatal: Symbol referencing errors. No output > > > written to run.x collect2: ld returned 1 exit status > > > > > > I tried to do everything I could but it seems there is some problem in > > > makefiles. > > > > > > Following are the makefiles I used. > > > > > > Makefile > > > > > > TARGET_ARCH = gccsparcOS5 > > > > > > CC = g++ > > > OPT = -O3 > > > DEBUG = -g > > > OTHER = -Wall > > > EXTRA_CFLAGS = $(OPT) $(OTHER) > > > # EXTRA_CFLAGS = $(DEBUG) $(OTHER) > > > > > > MODULE = run > > > SRCS = source.cpp sink.cpp fft.cpp main.cpp > > > OBJS = $(SRCS:.cpp=.o) > > > > > > include ../Makefile.defs > > > > > > > > > Makefile.defs > > > > > > ## Variable that points to SystemC installation path > > > SYSTEMC = /_TOOLS_/dist/systemc-2.0.1/sparc-sun-solaris2.8 > > > > > > > > > INCDIR = -I. -I.. -I$(SYSTEMC)/include > > > LIBDIR = -L. -L.. -L$(SYSTEMC)/libS/gcc-3.2.2 > > Hello: > > > > Try to use gcc 3.2 instead 3.3 > > > > Regards > > > > Javier Castillo > > jcastillo@opensocdesign.com > > www.opensocdesign.com > > > > > > > > > > LIBS = -lsystemc -lm $(EXTRA_LIBS) > > > > > > > > > EXE = $(MODULE).x > > > > > > .SUFFIXES: .cc .cpp .o .x > > > > > > $(EXE): $(OBJS) $(SYSTEMC)/libS/gcc-3.2.2/libsystemc.a > > > $(CC) $(CFLAGS) $(INCDIR) $(LIBDIR) -o $@ $(OBJS) $(LIBS) 2>&1 | > > > c++filt > > > > > > .cpp.o: > > > $(CC) $(CFLAGS) $(INCDIR) -c $< > > > > > > .cc.o: > > > $(CC) $(CFLAGS) $(INCDIR) -c $< > > > > > > clean:: > > > rm -f $(OBJS) *~ $(EXE) core > > > > > > ultraclean: clean > > > rm -f Makefile.deps > > > > > > Makefile.deps: > > > # $(CC) $(CFLAGS) $(INCDIR) -M $(SRCS) >> Makefile.deps > > > > > > #include Makefile.deps > > > > > > > > > Please help somebody, bu mailing me a running code or suggesting any > > > modifications to this code. > > >Article: 73390
Hi Subroto Thanks for your response. This may be a really stupid question but I dont seem to have a 'logic options' button in the assignment editor! How do I display it?? I cant find where to turn it on in the 'view' options. Thanks again Ryan "Subroto Datta" <sdatta@altera.com> wrote in message news:<IKB3d.10962$YD.8442@newssvr31.news.prodigy.com>... > . I have looked at the help files > > under "preserve hierarchical boundary logic option" and it recommends > > that I turn the "preserve_hierarchical_boundary" setting to off. I > > can't find this option in the Assignment editor as it suggests. Where > > would I be able to change this setting which supposedly would cure my > > bi-directional synthesis problem? > > > > > Thanks > > Ryan > > > Hi Ryan, > You can make this seting from the Assignment Editor->Logic Options > Panel. Open the Assignment Editor and click on the Logic Options button in > the upper right hand corner. Once this is done, if you click on the > Assignment Name field you should see this setting in the drop down. This > Assignment should be applied to the Instance of A for which you want to turn > this value OFF. This is specified in the To field of the Assignment Editor. > > Therefore the easiest sequence of steps is: > > 1. Open the Project Navigator->Hierarchy Tab. > 2.Find the instance of A for which hierarchy should not be preserved. > 3.Right click on the instance and select Locate in Assignment Editor. You > will see a row with the Instance name in there. > 4.Click on the Logic Options button in the upper right hand corner of the > Assignment Editor. > 5. Select the Preserve Hierarchy Boundary setting in the cell that is at the > intersection of Assignment Name and the row in Step 3. > 6. Set the value in the cell adjacent to the cell in Step 5 under the Value > column. > > Hope this helps. > Subroto Datta > Altera Corp.Article: 73391
> Since no known method exists > for cracking AES, a brute force attack is the only way to attempt to > crack the key. Nope. Ever heard of differential power analysis? Kolja SulimmaArticle: 73392
Hello I'm using the xilinx webpack and I get an error about a bad nph file. The problem is that I want to use a Spartan2 xc2s200-5pq208. I'm using webpack 6.3.01i Loading device for application Xst from file 'v200.nph' in environment F:/Xilinx. FATAL_ERROR:DeviceResourceModel:basnpdevice.c:620:1.23 - bad nph file Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com ERROR: XST failed Process "Synthesize" did not complete. Can someone tell me what is wrong? Thanks Rune ChristensenArticle: 73393
The problem come from Quartus Software (one bug more !!!!!!) It's impossible to use In-System Memory Editor if there is more than one PLD on the JTAG chain.Article: 73394
It would be nutty to build a CPU to do this! You'll never want to look at another counter, but this game can be done almost completely with ounters. -S "Jacques athow" <jaxlau@yahoo.com> wrote in message news:acc717b2.0409090742.3ebfe798@posting.google.com... > Mark McDougall <markm@vl.com.au> wrote in message news:<41401b1f$0$22802$5a62ac22@per-qv1-newsreader-01.iinet.net.au>... > > Jacques athow wrote: > > > > > CPU->MEMORY->VIDEO->SOUND is important. > Hi Mark, > > > > Its hard to test the video and sound without an appropriate CPU. > > > > I disagree here. You can get a basic tilemap and sprite system running > > without a CPU. In fact, the design will build *much* faster without a > > True that the design and testing cycle will be faster without > designing a CPU and interfacing, but later, if you ever consider to > run it along side of an actual processor, you might face problem with > interfacing. > > > CPU. We had both tilemap and sprites going before we hooked it up to a CPU. > > > actually the design of our "ppu" started sometime after having done > sound, cpu and memory. But the thing is that we needed a CPU model to > test the video unit. It make sense to start with the CPU and have it > running. Its not imperative to have it, it would be more fun to start > with the video, but watch out for complication with the cpu-video > interface sometime futher down the line. That was our mistake and im > just stating it here. I dont know how complex the pacman video system > is, but the process of designing the 6502 CPU helped us understand and > hence design a PPU which was based on a "datapath-controller" > approach. This methodology is somewhat general and variations which > applies to something more specific is needed, in the case of pacman > for example. In our case we also had a sound unit that was hard to > test without a CPU. > > Anyways, I really enjoyed our project and yes, it took us a hell out > of time to complete it! > I believe that with good planification and tools, you can achieve what > you want in the time allocated. Just hurry up and start the project!!! > > good luck and have fun > > jaArticle: 73395
Hi, I am trying to simulate the Example Instance of the Altera DDR SDRAM Controller IP Core. As described in the DDR SDRAM MegaCoreFunction User Guide I type the following command under Modelsim to simulate the IP functional simulation model. set use_simgen_model 1 source example_controller_ddr_sdram_vsim.tcl When running the tcl script I get error messages that several signals are not found, for example: # ** Error: No objects found matching "/DDR_SDRAM_top_tb/dut/local_rdata" # Executing ONERROR command at macro ./wave.do line 35 What is going wrong ? One additional question: What is the difference if I simulate the pre-compiled ModelSim VHDL libraries or if I simulate with an IP functional simulation model (DDR SDRAM MegaCore Function UserGuide page 43) ? Maybe someone has tried to get startet with the IP Core and has some idea of what goes wrong ... I am using QuartusII v. 4.1 SP1 and Modelsim Altera 5.8.c Kind regardsArticle: 73396
Hi, when I choose in Quartuss Utility Windows > Tcl Console and then choose Tcl Script (Tools menu) I cannot see any Tcl tool. Is the Tcl tool only available for certain Quartus versions? I am using Quartus v. 4.1 SP1 (full version) I would appreciate your help. RgdsArticle: 73397
Though I will be using the webpack that ships with the Spartan-3 intially, I am somewhat interested in the Linux version of BaseX or Linux that I've been reading about. With version 6.3, is the Linux version now native (not WINE)? Also, does it provide all of the features of the Windows version?Article: 73398
for Loc drop-down box, there sre T,L,R,TL,TR,BL,BR,RT,RB,LT,LB. What they mean?Article: 73399
The Tcl console is interactive, so that the user can type in Tcl commands in there, or execute Tcl scripts which they write using the source command.. When you choose Tools->Tcl Scripts it opens a dialog which points to the canned Tcl scripts that ship with Quartus. You can then select the script and run it. The only one of significance there is the dse script which you can also run from your DOS box by typing quartus_sh --dse.The Full version of Quartus fully supports Tcl. - Subroto Datta Altera Corp. "ALuPin" <ALuPin@web.de> wrote in message news:b8a9a7b0.0409210601.3fba8e7f@posting.google.com... > Hi, > > when I choose in Quartuss > Utility Windows > Tcl Console > and then choose Tcl Script (Tools menu) > I cannot see any Tcl tool. > > Is the Tcl tool only available for certain Quartus versions? > > I am using Quartus v. 4.1 SP1 (full version) > > > I would appreciate your help. > > Rgds
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