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> Ayon kay Bob: >> "yy" <yy7d6@yahoo.com.ph> wrote in message >> news:1162860919.587459.46830@m73g2000cwd.googlegroups.com... >> > Hi i'm currently working on a high-speed chip-to-chip serial interface >> > FPGA interface, i would like to know some suggestions regarding FPGA >> > differential signalling; especially the trace matching of pair of LVDS >> > signal, and the whole Channel (set of LVDS signals; Tx_Frame, Tx_Clk, >> > Tx_Data) etc. >> > My application is for 622Mbps signalling rate. >> > Anyone has an experience on this? >> > >> >> It's important to keep all signals' p-to-n length matched closely. This >> will >> insure that there is a clean cross between the p and n inputs of the >> input >> comparator during one-to-zero and zero-to-one transitions. You don't want >> a >> p input to change from zero to one while the n input is still stuck at a >> one. >> >> For signal-to-signal length matching (in a source synchronous bus), you >> must >> consider the outputs' clock-to-out delay matching and the inputs' setup >> and >> hold time. There is no way to determine the length matching requirements >> without knowledge of the output and input characteristics. >> >> I would recommend using a FPGA family that has internal 100ohm >> differential >> termination (within the input block). For Xilinx, this is V2Pro and above >> (watch the VCCO requirements carefully). This will make layout easier and >> give you the best setup and hold margin because at 622Mbps you're gonna >> need >> all you can get. >> >> Bob > "yy" <yy7d6@yahoo.com.ph> wrote in message news:1162897549.947143.238690@m7g2000cwm.googlegroups.com... > Hi Bob, > I've matched the trace length withing 100mils is that OK? BTW, i use > Spartan3 FPGA. > Does having the DCI option in Spartan3 will eliminate the external > termination resistor at the receiving end? > One more thing, the other FPGA i'm using is Altera Cyclone-II FPGA(for > this chip-to-chip connection)--and cyclone fpga needs at least 3 > external resistors, my question is, > can Spartan3's LVDS_DCI compensate for the external 'resistor network' > at cyclone2, i mean if the DCI is enabled in spartan3 will there be no > need for that resistors when cyclone2 is driving the LVDS line? > > Yy > The LVDS_DCI should work as the end termination (rather than LVDS_DT), but I'm not 100% sure all LVDS drivers will be compatible with it. The issue is that the DCI attempts to force the common-mode level at the receiving end -- whereas normally this is only controlled by the driver. The other questions you're asking indicate (to me) that this project may be too difficult for you to complete successfully. I suggest you learn more about the things I discussed in the previous post. Your chances, now, of getting a 622Mbps bus working are slim to none. BobArticle: 111676
Jon Elson wrote: > Hello, all, > > Does anyone know where I can get just a few (5 - 10) Xilinx > XCS30-3TQ144C chips? Anybody who has them wants to sell me > a minimum of a hundred or more. I just need a few to make > repairs on equipment in the field. I just got a board back > from a customer who had a lightning strike, and I had to salvage > a chip off a test module to get his unit repaired. > > If anyone has a few of these chips laying around, I'd be glad to > pay the going rate for them, too! I can probably use other speed > ranges or temp ranges as well. I'm in the US, but that shouldn't > make much difference, I seem to be buying my Xilinx chips from > Australia these days! > > Thanks much in advance. > > Jon item 150055912098 on ebay?, XCS30-3TQ144C, buy now price US $6.85 -LasseArticle: 111677
karollo@o2.pl wrote:
> Could you explain the difference between extension vht and vhd?
goggle is your friend:
http://www.google.com/search?q=quartus+vht+file+definition
vhd is vhdl code for modelsim or synthesis
Read some docs.
> Does It
> means that I can't use testbench exporetd from waveform to vht in
> Quartus.
quartus uses vht for it's simulator. Modelsim doesn't.
> ModelSim doesn't see this file. I changed name from tbench.vht to
> tbench.vhd but it doesn't work. I have few waveform files and I want to
> try export them to another format. I could do that in Waveformer Pro
> (Synapticad) but it is only eval version in which I can't even save.
You have discovered one good reason to learn an HDL.
-- Mike Treseler
Article: 111678Hi backhus Thanks a lot! I heard latch is only used in gated clock in ASIC design. Is it right? I think it must be gated clock cause the problem. I see the waveform. And I found though data and clock change at the same time i.e at the same delta time (I forbidden timing delay at global scope), clock change is follow the data change. As we all know data change must follow the clock change. So I guess there must be gated clock cause some logic sequence chaos in simulator. Best regards, Davy backhus wrote: > Hi Davy, > When you say netlist simulation do you mean a timing simulation? > And when you say RTL level simulation Do you mean a behavioral simulation? > If my assumtions are correct think about the following: > > If you are using gated clocks, the gate has no delay in behavioral > simulation, so your circuit works as expected. But in Timing simulation > the gate and the associated routing creates a delay to the clock signal > of the connected registers. The effects depend on the desired clock > speed, and may be significant as you already observed. > > To overcome this you should consider using Clock Enable inputs rather > than gating the critical clock net. > > And, yes you guessed right. A gated clock doesn't behave like the > original clock because it's a totally different signal. > You can compare it to trains. One on rails (clock net), the other not > (normal routing ressources). Guess wich one misses it's schedule at the > next station. :-) > > Have a nice simulation > Eilert > > Davy schrieb: > > Hi all, > > > > When I simulate netlist with gated clock, I found the output is very > > different with what I see in RTL level. > > > > So I add tfile in NCSim to forbidden the delay and timing check in > > global scope (Because the design have no memory like RAM/FIFO). > > > > The netlist waveform seems to be better, but there are also some > > trivial differences between RTL and netlist waveforms (e.g. some signal > > have one clock advance and some signal have one clock delay). I guess > > gated clock does not behavior like original clock and introduce race. > > > > But how to understand gated clock simulation behavior? Any > > comments/reference will be appreciated! > > Thanks! > > > > Best regards, > > Davy > >Article: 111679
hi all, I have a core already inside the Spartan 3 FPGA. I m trying to integrate SDRAM Controller with the existing core. My board doesn't get detected at all after programming the spartan. Anyone help pls... Thanks!! Amirtha.Article: 111680
Ralf Hildebrandt wrote: > Amirtham schrieb: > > > I have implemented a SDRAM Controller in Spartan 3s400.I already have > > another working core inside the same FPGA. when i try to implement my > > design with this, my device is not detected atall. > > Simulate you design - including SDF backannotation. > Break your design into smaller components, Test these components. > Feed interesting signals to output pins / LEDs. Generate Signals, that > allow you decide, if a part is working or not. > > Ralf This is a simulated design & having no problem. amirArticle: 111681
If you are running your bus as DDR, take a look at Xilinx XAPP265. Otherwise check out XAPP622 for SDR. Regardless, XAPP265 has some good tips toward the end on how to use the DCM to adjust your clock and center it in the data valid window. I'd think twice about using the DCI on the S3 and expecting it to work well as an LVDS term . You are better off using discrete resistors. Even better would be to jump to the S3E, which has LVDS_DT inputs available. The 3-resistor network is just an attenuator network at the source to translate full 2.5v or 3.3V levels to the LVDS levels; I suppose you could put it at the end of the line if it produced the required LVDS_25 levels (which it is supposed to), but that is a lot of stuff to bunch up under the chip. You do realize that the stub length on the terminators (to the pin) is kind of important, no? SM "Bob" <nimby_NEEDSPAM@adelphia.net> wrote in message news:_6SdnUjM5M3rs8zYnZ2dnUVZ_oqdnZ2d@adelphia.com... > > >> Ayon kay Bob: >>> "yy" <yy7d6@yahoo.com.ph> wrote in message >>> news:1162860919.587459.46830@m73g2000cwd.googlegroups.com... >>> > Hi i'm currently working on a high-speed chip-to-chip serial interface >>> > FPGA interface, i would like to know some suggestions regarding FPGA >>> > differential signalling; especially the trace matching of pair of LVDS >>> > signal, and the whole Channel (set of LVDS signals; Tx_Frame, Tx_Clk, >>> > Tx_Data) etc. >>> > My application is for 622Mbps signalling rate. >>> > Anyone has an experience on this? >>> > >>> >>> It's important to keep all signals' p-to-n length matched closely. This >>> will >>> insure that there is a clean cross between the p and n inputs of the >>> input >>> comparator during one-to-zero and zero-to-one transitions. You don't >>> want a >>> p input to change from zero to one while the n input is still stuck at a >>> one. >>> >>> For signal-to-signal length matching (in a source synchronous bus), you >>> must >>> consider the outputs' clock-to-out delay matching and the inputs' setup >>> and >>> hold time. There is no way to determine the length matching requirements >>> without knowledge of the output and input characteristics. >>> >>> I would recommend using a FPGA family that has internal 100ohm >>> differential >>> termination (within the input block). For Xilinx, this is V2Pro and >>> above >>> (watch the VCCO requirements carefully). This will make layout easier >>> and >>> give you the best setup and hold margin because at 622Mbps you're gonna >>> need >>> all you can get. >>> >>> Bob >> > "yy" <yy7d6@yahoo.com.ph> wrote in message > news:1162897549.947143.238690@m7g2000cwm.googlegroups.com... >> Hi Bob, >> I've matched the trace length withing 100mils is that OK? BTW, i use >> Spartan3 FPGA. >> Does having the DCI option in Spartan3 will eliminate the external >> termination resistor at the receiving end? >> One more thing, the other FPGA i'm using is Altera Cyclone-II FPGA(for >> this chip-to-chip connection)--and cyclone fpga needs at least 3 >> external resistors, my question is, >> can Spartan3's LVDS_DCI compensate for the external 'resistor network' >> at cyclone2, i mean if the DCI is enabled in spartan3 will there be no >> need for that resistors when cyclone2 is driving the LVDS line? >> >> Yy >> > > The LVDS_DCI should work as the end termination (rather than LVDS_DT), but > I'm not 100% sure all LVDS drivers will be compatible with it. The issue > is that the DCI attempts to force the common-mode level at the receiving > end -- whereas normally this is only controlled by the driver. > > The other questions you're asking indicate (to me) that this project may > be too difficult for you to complete successfully. I suggest you learn > more about the things I discussed in the previous post. Your chances, now, > of getting a 622Mbps bus working are slim to none. > > Bob > > >Article: 111682
On 1 Nov 2006 06:42:49 -0800, "Guru" <ales.gorkic@email.si> wrote: >Using Virtex4FX12, laptop P4M 1.7GHz and ISE 8.1 SP3 and EDK 8.2 SP1. >Strange, because I rebuld one MB project in 8.2 for S3ESK and it worked >fine. I think this are some bugs that emerge from time to time. Lets >pray that EDK SP2 will solve the problem. > Well, in my case SP2 will not correct the problem. I am looking for some free time to dedicate it to nake some slow and painful step-by-step rebuild to see if I can spot the solution ZaraArticle: 111683
Hi Davy, I`m more familiar with FPGA design than ASIC design, but I think for both targets latches should be avoided. They are not sensitive to clock edges, and data changes while they are enabled pass the latch causing trouble in the circuit that follows. I'm not sure if there are still designs which have to use latches instead of FFs for some reason. But to my knowledge Clock gating for latches is a design technique from way back when, when there were no real FFs available and the clock frequencies were about 1 MHz. From the groups you are posting to, I guess that you are using NC-Sim, dont'you? If you say that you wonder about the seqence of changes (Clock before/after Data or vice versa) what time scale are you talking about? Do you change Data within the setup/hold time of your FFs? This may lead to strange results in your simulator. Besides simulation, have you made a static timing analysis for your design? Have a nice simulation Eilert Davy schrieb: > Hi backhus > > Thanks a lot! > > I heard latch is only used in gated clock in ASIC design. Is it right? > > I think it must be gated clock cause the problem. I see the waveform. > And I found though data and clock change at the same time i.e at the > same delta time (I forbidden timing delay at global scope), clock > change is follow the data change. > > As we all know data change must follow the clock change. So I guess > there must be gated clock cause some logic sequence chaos in simulator. > > Best regards, > Davy > > backhus wrote: >> Hi Davy, >> When you say netlist simulation do you mean a timing simulation? >> And when you say RTL level simulation Do you mean a behavioral simulation? >> If my assumtions are correct think about the following: >> >> If you are using gated clocks, the gate has no delay in behavioral >> simulation, so your circuit works as expected. But in Timing simulation >> the gate and the associated routing creates a delay to the clock signal >> of the connected registers. The effects depend on the desired clock >> speed, and may be significant as you already observed. >> >> To overcome this you should consider using Clock Enable inputs rather >> than gating the critical clock net. >> >> And, yes you guessed right. A gated clock doesn't behave like the >> original clock because it's a totally different signal. >> You can compare it to trains. One on rails (clock net), the other not >> (normal routing ressources). Guess wich one misses it's schedule at the >> next station. :-) >> >> Have a nice simulation >> Eilert >> >> Davy schrieb: >>> Hi all, >>> >>> When I simulate netlist with gated clock, I found the output is very >>> different with what I see in RTL level. >>> >>> So I add tfile in NCSim to forbidden the delay and timing check in >>> global scope (Because the design have no memory like RAM/FIFO). >>> >>> The netlist waveform seems to be better, but there are also some >>> trivial differences between RTL and netlist waveforms (e.g. some signal >>> have one clock advance and some signal have one clock delay). I guess >>> gated clock does not behavior like original clock and introduce race. >>> >>> But how to understand gated clock simulation behavior? Any >>> comments/reference will be appreciated! >>> Thanks! >>> >>> Best regards, >>> Davy >>> >Article: 111684
hi, as Slurp already mentioned, the reset seems to be missing, but besides that.. What about your Clock signal? Are there Overshots or Ground Bouncing at your FPGA Input? Depending on your measuring setup and the sensitivity of your LA-Pods these might be invisible to your LA, but valid for the Clock input of your FPGA. Since only the clock edge is of importance here and not the frequency it doesn't matter if you use 150 MHz or 1 MHz when you have this problem. It only depends on the rise time and drive strength of your Clock generator and the associated wire(transmission line) to your FPGA Input. You need some good oszillscope to analyse this, and it may also happen that the problem vanishes when the oszilloscope is connected to your system. In that case the problem is there but can't be seen due to the influence of your probe (input impedance) which changes the behavior of your transmission line. have a nice measuring EilertArticle: 111685
Hi Mordehay, I have done this a few times, but was unsucessful with the IMPACT tool to download into the board. If there is some elaboration on what options to choose and few steps would be great. Thanks and regards, Sandip me_2003@walla.co.il wrote: > Use the IMPACT tool in the ISE. > after implementing your design just open the IMPACT tool and follow the > instructions > it should be pretty simple. > Mordehay. > > Sandip wrote: > > Hi, > > > > I am using ML403 board with Virtex-4. I need to generate and download a > > PROM file into the PROM and then use it after I switch it OFF and then > > again ON. > > Can anyone please help me out in doing so?? > > > > Thanks and regards, > > SandipArticle: 111686
Mark McDougall wrote: > And as we both suggested, have your host driver probe the required > information and explicitly write it to your card. It is the most > practical and benign solution. well sir, let me explain you the whole problem. Targetted application will be the embedded environment and I shall have to configure SATA controller using this opencores PCI. SATA controller talks in the language of PCI. Fortunately, right now I have a PCI card having SATA controller, so basically this gives me an opportunity to emulate whole embedded environment just by placing SATA card and FPGA card in two slots of the same PC. I can use driver to probe the bars but I want to read BARs of SATA card with the help of opencore PCI because this is what I shall be eventually doing. Now I want to take your opinion and suggestions in this regards. Having a nice day. Regards AdnanArticle: 111687
You will not be able to achieve 622Mbps with Spartan 3 as the DCMs are limited to 280MHz to yield a DDR bit rate of 560MHz. You might get there with Spartan 3E. However, you will need to be extra careful with source clocks (jitter) and SSO noise elsewhere on the receiver FPGA. The jitter issue is especially important as I have noticed that cycle to cycle jitter performance with DCMs isn't that great. I write from experience of using Spartan 3 with LVDS links (albeit down a less than ideal cable @ 500MHz). yy wrote: > Hi Bob, > I've matched the trace length withing 100mils is that OK? BTW, i use > Spartan3 FPGA. > Does having the DCI option in Spartan3 will eliminate the external > termination resistor at the receiving end? > One more thing, the other FPGA i'm using is Altera Cyclone-II FPGA(for > this chip-to-chip connection)--and cyclone fpga needs at least 3 > external resistors, my question is, > can Spartan3's LVDS_DCI compensate for the external 'resistor network' > at cyclone2, i mean if the DCI is enabled in spartan3 will there be no > need for that resistors when cyclone2 is driving the LVDS line? > > Yy > > Ayon kay Bob: > > "yy" <yy7d6@yahoo.com.ph> wrote in message > > news:1162860919.587459.46830@m73g2000cwd.googlegroups.com... > > > Hi i'm currently working on a high-speed chip-to-chip serial interface > > > FPGA interface, i would like to know some suggestions regarding FPGA > > > differential signalling; especially the trace matching of pair of LVDS > > > signal, and the whole Channel (set of LVDS signals; Tx_Frame, Tx_Clk, > > > Tx_Data) etc. > > > My application is for 622Mbps signalling rate. > > > Anyone has an experience on this? > > > > > > > It's important to keep all signals' p-to-n length matched closely. This will > > insure that there is a clean cross between the p and n inputs of the input > > comparator during one-to-zero and zero-to-one transitions. You don't want a > > p input to change from zero to one while the n input is still stuck at a > > one. > > > > For signal-to-signal length matching (in a source synchronous bus), you must > > consider the outputs' clock-to-out delay matching and the inputs' setup and > > hold time. There is no way to determine the length matching requirements > > without knowledge of the output and input characteristics. > > > > I would recommend using a FPGA family that has internal 100ohm differential > > termination (within the input block). For Xilinx, this is V2Pro and above > > (watch the VCCO requirements carefully). This will make layout easier and > > give you the best setup and hold margin because at 622Mbps you're gonna need > > all you can get. > > > > BobArticle: 111688
Ray Andraka <ray@andraka.com> writes: > Martin Thompson wrote: > > > > All this applies in spades to RAM blocks, most of the time, all I want > > is an address bus (or two), a write enable and a data bus (or two). > > The Xiinx way forces me to instantiate specific sizes of blocks, which > > change from generation to generation, when all I want to do is say I > > need a 2Kx8 RAM. > > Martin, starting with Virtex4, the same RAMB16 primitive is used for > all variants of the block RAM. It is parameterized with generics, > which makes it a lot easier to instantiate a RAM that is sized > according to the need. Thanks Ray, that's good to know - I haven't V-4ed in anger yet... > I find it still needs a wrapper, but at least that wrapper doesn't > have to contain primitives with every combination of port sizes. I > use a wrapper that automatically generates a RAM array with the > appropriately sized ports on individual BRAMs based on the widths of > the data ports and address ports. It also hides the parity bit/data > bit distinction, plus it gives an easy method to porting to a > different family (replace the wrapper). > I still maintain that Xilinx should provide us with a useful wrapper though, rather than us all having to do our own :-) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 111689
Basically i am looking for a way to get this cable working with the x64 bit version of windows - can somebody help me with this ??? Regards DreArticle: 111690
Hi, I would like to ask if somebody has come across the same problem: I need to convert a picture (bmp format) to a .hex or .mif file which will go into ROM's in a Stratix-2 FPGA. Do you know of any conversion utility which translates .bmp to .hex suitable for FPGA's? Thanks!Article: 111691
Martin Thompson wrote: > Ray Andraka <ray@andraka.com> writes: > > I still maintain that Xilinx should provide us with a useful wrapper > though, rather than us all having to do our own :-) > > I agree, however with the caveat that it may still not fit all users. Mine, for example accepts an unconstrained integer array generic for initialization values. It puts the contents of that N element array into the first N locations of the RAM and zero fills the rest. Since the width can be greater than the 32 bits represented by VHDL integers, I have a second integer array generic for separately initializing the top half of an upto 63 bit wide composite memory. The wrapper instantiates RAMB16s with the depths determined by the number of address bits on each port, and then puts in as many RAMB16s as are required to accommodate the widths of the data ports. The entity for my V4 wrapper is: entity dual_port_ram is generic( SIM_COLLISION_CHECK : STRING := "NONE"; DO_reg: integer:=0; allow_pbits: integer:=1; reset_data: integer:= 0; --not usable with do_reg=1 RAM_data: int_array:=(0,0); --initial data RAM_data_hi: int_array:=(0,0)); --initial data port( CLKA: in std_logic; CLKB: in std_logic; SSRA: in std_logic; SSRB: in std_logic; WEA : in std_logic; WEB : in std_logic; DIA : in std_logic_vector; DIB : in std_logic_vector; DOA : out std_logic_vector; DOB : out std_logic_vector; ADDRA : in std_logic_vector; ADDRB : in std_logic_vector ); end dual_port_ram;Article: 111692
Phil wrote: > Hi, > > I would like to ask if somebody has come across the same problem: I need to convert a picture (bmp format) to a .hex or .mif file which will go into ROM's in a Stratix-2 FPGA. Do you know of any conversion utility which translates .bmp to .hex suitable for FPGA's? > > Thanks! I don't know of anything that converts files directly to hex, but it's not hard to do it in two steps. Several image viewers and editors including Irfanview and PhotoShop can load Windows bitmap files and save them in raw (binary) format. Then you can just convert binary to hex, for which I use "od" from either a Unix/Linux machine or the MCS toolkit under Windows. You may need to do further editing of the hex file to get it into a format that Quartus understands. HTH GaborArticle: 111693
Hello everyone, is there anyone who knows about the FPOA (Field Programmable Object Array) by Mathstar? Did anyone ever used this kind of programmable logic? As they say in their site FPOA can proccess in very high frequencies such as 1 GHz. is there any suggestions about this silicon? thank you very much. tsemerArticle: 111694
I've attached a tutorial that I found in the web I hope it will help you to proceed. goodluck, Mordehay. http://vlsi1.engr.utk.edu/~msharafa/HowToBurnSerialProm.htm Sandip wrote: > Hi Mordehay, > I have done this a few times, but was unsucessful with the IMPACT tool > to download into the board. If there is some elaboration on what > options to choose and few steps would be great. > > Thanks and regards, > Sandip > > me_2003@walla.co.il wrote: > > Use the IMPACT tool in the ISE. > > after implementing your design just open the IMPACT tool and follow the > > instructions > > it should be pretty simple. > > Mordehay. > > > > Sandip wrote: > > > Hi, > > > > > > I am using ML403 board with Virtex-4. I need to generate and download a > > > PROM file into the PROM and then use it after I switch it OFF and then > > > again ON. > > > Can anyone please help me out in doing so?? > > > > > > Thanks and regards, > > > SandipArticle: 111695
Hello, I have a system with limited memory resources which contains a Nios2 processor. An EPCS device is linked to this processor. I don't want to use the HAL drivers to access this device because when I use the HAL drivers I will need lots of memory and I can no longer use the small C library. After looking in the EPCS device controller section in the Quartus2 handbook I have noticed that the register functions are not published. Altera states: "Altera does not publish the usage of the control and data registers. To access the EPCS device, you must use the HAL drivers provided by Altera". I don't want to use the HAL drivers because of their code size. Does anybody have a description of the EPCS Controller Register Map? Thanks and best regards, Karel DeprezArticle: 111696
EPCS device controller info can be found on: http://www.altera.com/literature/hb/nios2/n2cpu_nii51012.pdfArticle: 111697
hi im doing a project to implement single and double precision floating point arithemetic units on Altera FPGA.Can someone please arrange me or tell me any link from whr i can find the VHDL coding for the same.im a beginner in the VHDL field.Article: 111698
shaz.pecobian@gmail.com wrote: > hi > im doing a project to implement single and double precision floating > point arithemetic units on Altera FPGA.Can someone please arrange me or > tell me any link from whr i can find the VHDL coding for the same.im a > beginner in the VHDL field. > What do you mean by arithmetic units? Normally in FPGAs, we implement only the function that is needed for that part of the circuit, not a complete arithmetic unit like you'd find in a microprocessor. Most likely, you won't find something that exactly meets your needs and you'll have to roll your own. You also said nothing about performance or size requirements. Floating point isn't all that difficult to implement, just costly in terms of amount of logic, especially for the adds and subtracts. I suggest you pick up a book such as Israel Koren's Computer Arithmetic that discusses floating point number systems as a starting point so that you understand the hardware that is necessary for floating point operations.Article: 111699
Today I have observed again a kind of unpredicatable behaviour in quartus II that I had already experienced in another project. In each case, the situation was: - A specific signal on a design does not work as expected. - To debug, an output pin is added to monitor a signal around the problematic part of the circuit. No other changes are made. - As a consequence of adding this pin, the original signal works ok. - The debugging pin is removed and the design works perfectly. It seems as if the compilation process is not 100% deterministic but relies on previous runs. The same kind of problem has (had) been experienced in quartus 4.2 and 5.1. Is there any option to force quartus II to start each compilation from scratch? Of course, there is the possibility that I am missing some point. Any hint? Thanks for your time Pere
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