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I'm using the Avnet virtex-4 fx mini module. I downloaded their sample design using the embedded tri mode ethernet mac wrapper. The design is supposed to be an echo server. I am able to build the user application successfully. But when I try to update the bitstream I receive many warnings. I open up the hyperterminal and it does not display whether the memory is being tested on the board, like it is supposed to. I try to connect to port 7 and a message is displayed on the telnet terminal that connect failed. WARNING:MDT - fpga_0_RS232_rtsN (rtsN) - C:\fx12mm_temac_lwip_echo_server_edk8_2_021\V4FX12MM_TEMAC_lwIP_Echo_Server_D esign\system.mhs line 296 - floating connection! Then I get many warnings of this type: WARNING:MDT - MII_RXD_0 (Hard_Temac_0) - E:\EDK\hw\XilinxProcessorIPLib\pcores\hard_temac_v3_00_a\data\hard_temac_v2_1 _0.mpd line 76 - connection is not connected to an external port! . . . . WARNING:MDT - GMII_RXD_1 (Hard_Temac_0) - E:\EDK\hw\XilinxProcessorIPLib\pcores\hard_temac_v3_00_a\data\hard_temac_v2_1 _0.mpd line 141 - connection is not connected to an external port! MPD subproperties IOB_STATE=BUF|REG require that the input port be connected directly to an external port. WARNING:coreutil:8 - Feature <opb_uart16550_v1> is enabled with a Hardware_Evaluation license. Completion time: 3.00 seconds Creating hardware output directories ... Then I get many warnings of this type: WARNING:Xst:2211 - "C:/fx12mm_temac_lwip_echo_server_edk8_2_021/V4FX12MM_TEMAC_lwIP_Echo_Server_Design/hdl/system.vhd" line 3673: Instantiating black box module <IOBUF>. I don't know where to connect the signals that need to be connected. I don't know why it instantiates the black boxes. I have emailed Avnet three times, called them once, opened a webcase on xilinx.com. So any help anyone could give me would be very appreciated! RudyArticle: 112701
pavan kumar ha scritto: > i need vhdl source code for I2C Controller urgently...plz help me > regarding this..MY email ID is meetpavankumar@gmail.com i think there is an i2c controller on opencores.org You can also post there if your professor is happy with that...Article: 112702
Jim Thompson wrote: > I didn't know there was any such thing as an *efficient* switched-cap > regulator. Their only convenience lies in small size. They are > particularly nice when there is no load current... such as the bias > for an integrated electret microphone in a hearing aid chip I designed > last year ;-) Why can't a switched cap converter be efficient? The only losses are in the resistance of the swtich (same as an inductive switcher) and the difference in voltage between the switched output and the end circuit. I was thinking along the lines of using multiple topologies to get a good voltage match to the required output voltage at any given input voltage. 2:1, 3:1, 4:1, I even came up with a circuit to provide 2.5:1, but that is likely overkill. > However, if you're switching large currents... thus low resistance > switches, driving the gate capacitance *will* be a major contributor > to your losses. > > Are you certain you wouldn't be better off with an inductive switcher? Two problems with inductive switchers running from higher voltages; 1) the losses are significant when running at lower currents like < 100 mA. My current board has to run in idle at 100 mW and provide up to 2 watts in full performance mode. With a 9:1 ratio of operation, losses at 100 mW can be significant. 2) Inductors generate a *LOT* of noise and this is inside a radio! We use inductive switchers because it is a 5 watt unit. But we have to keep the well filters, isolated and they still create too much noise so we synchronize them to a common clock to put the spurs in known places. > What are your actual I/O requirements. Input ranges from 7 to 17 volts. Outputs are at 5, 3.3 and 1.8 volts. I would only expect the main switcher to generate 5 volts as the others can be made from that. It should run from a 600 kHz reference clock, but that can be divided down if needed to make the circuit work efficiently. The output current for efficient operation would range from 20 mA to 250 mA. Is this anything like practical?Article: 112703
Jon Elson wrote: > Al wrote: > >> Hi to everyone, I'm trying to generate a 5-10 ns pulse width out of an >> edge, without the use of any clock, just with internal delays. >> Unfortunately I can imagine how much this delay will depend on >> temperature and voltage and how much the width will be affected, but >> still I have some margins (anyway everything will be tested in a >> thermal chamber to verify functionalities). >> So far I developed a sort of a "ripple-counter" with an auto-reset for >> each FF (Q(0) will asynchronously reset Q(0)) so that I can start an >> internal oscillation (a clock!). >> After that a normal counter can be realized on the basis of this >> clock, allowing to build a pulse. Once the pulse is over a reset is >> generated to stop asynchronously all the FFs. > > > I needed a delay to advance an address counter after a bus strobe > ended. It was for a CPLD on a small plug-in board, and there was > no other need for a clock on the board. So, I routed the signal out > one pin, through a 1.5 K Ohm resistor, and into another pin. The > input capacitance of the pin became the C of the RC time constant. > This has worked well in the application. > > In your case, taking the signal through a similar external delay, and then > bringing it back in to an AND2B1 for a pulse only on the rising edge, > or an XOR if you want pulses on both edges should do what you want. > Adjust the resistor value to get the desired time delay. > > It may also be possible to route to an unbonded IO pad with weak drive > and get a fair amount of delay, easily 5 ns, but probably not 10. > > Jon Al mentioned he wanted to avoid a PCB respin, but he could certainly look for spare IO pin(s), and make use of the pin path delays. It may even become probe-able ? -jgArticle: 112704
burn.sir@gmail.com wrote: > No surprise there, Mico32 was Originally _designed_ for Xilinx FPGAs. And how would you know that? (Because it isn't true :-) ). Cheers, JonArticle: 112705
burn.sir@gmail.com wrote: > Thank you for your answer Jon, > > > The JTAG problem was expected, and is easy to fix (write your own JTAG > block). Regarding the MMU, well, I have heard the MB cannot be modified > to include a MMU, is the same true for Mico32? You could add an MMU to Mico32. It would probably have to sit on the bus rather than in the pipeline though (unless you want to ripup the pipeline completely). So you have virtually tagged caches etc. You could either use the user defined instructions for updating the TLB, or just memory map them. Cheers, JonArticle: 112706
I have a xilinx v4 project running mv linux 2.6.10. I have a custom peripheral I made that includes DMA on the opb bus and is therefore master/slave. The SDRAM that the linux .elf file loads to/boots from is also on the opb. Unless I disconnect the custom peripheral linux dies at "uncompressing linux...". I believe this means that there are data errors from the sdram, but everything works fine stand-alone. I know the dma isn't running, for example, and I've made sure to reset every other register related to that peripheral but linux just won't boot unless I disconnect it. Any ideas? Thanks, ClarkArticle: 112707
On 2006-11-27 18:47:24 +0100, burn.sir@gmail.com said: > > http://gpl-violations.org/ > > > Anyway, I fail to see why you need the source code anyway. I suspect > that the only person in this list that can make any use of the GCC code > is Mr Delorie :) > > > bruns So..how about you're getting a NIOS2 board and you just want to compile software for it on a different host? Let's say...FBSD, Solaris, OSX etc... cheers rick > > > > Richard Klingler wrote: >> On 2006-11-27 16:30:59 +0100, "Antti" <Antti.Lukats@xilant.com> said: >> >>> Richard Klingler schrieb: >>> >>>> EHLO (o; >>>> >>>> >>>> What happened to the nios2 sources which were once accessable >>>> via the doc/degree ftp login documented on the Altera website? >>>> >>>> Unfortunately Altera stopped sponsoring me with Quartus/NIOS >>>> for doing core tests and porting cores to sopc builder...so >>>> I won't get any more nios2 toolchain sources on CD (o; >>>> cheers >>>> rick >>> >>> well if they dont want to violate the GPL license they must provide >>> the source codes, like both Xilinx and Lattice do for their soft cpus >>> >>> Antti >> >> Aaahh....familiar name (o; >> >> At least I could win Lattice and Actel for sponsoring design software >> and devices. But concentrating on porting to Lattice now as Actel >> sended an obsolete evaluation board (o; >> >> Isn't that with GPL that you only have to give the sources upon >> requests if you already bought their product? So basically someone >> without a NIOS board the request could be denied? >> >> >> cheers >> rickArticle: 112708
On 2006-11-27 19:47:54 +0100, "Derek Simmons" <dereks314@gmail.com> said: > > The sources that you are looking for are they the ones that come on the > install CDs or the ones described in application note 267 (AN267)? > > Derek Hi Derek The ones on the Linux NIOS2 CD...the WIndows version isn't really usable on a case-sensitive filesystem (o; cheers rick > > Richard Klingler wrote: >> EHLO (o; >> >> >> What happened to the nios2 sources which were once accessable >> via the doc/degree ftp login documented on the Altera website? >> >> Unfortunately Altera stopped sponsoring me with Quartus/NIOS >> for doing core tests and porting cores to sopc builder...so >> I won't get any more nios2 toolchain sources on CD (o; >> >> >> >> cheers >> rickArticle: 112709
I am trying to write an SDRAM controller in VHDL for a mobile SDR SDRAM that I want to be able to control via an FPGA on the same PCB. I am having trouble with the verilog model. I have used both a samsung and a micron model for the part (two compatible parts). Unfortunately these models are not available in VHDL, and my verilog is pretty weak. I wondered if any one had some experience with memory models, both in terms of using them to design memory controllers and debugging them when they spit out spurious timing violations. These verilog models in particular seem to send out all manner of timing violations or functional problems that don't seem to be in line at all with what the data sheet says regarding the timing and command and control procedures (for doing a full page read or write, for instance). Has any one else had trouble with bad/buggy models? What is the best way to solve this problem? What is the best way to go about designing a memory controller (I have seen an example on Altera's website in VHDL (but it sucks), as well as some others in open cores and one written for a homebrew graphics accelerator card (manticore). I find the documentation and/or functionality lacking in most of the aforementioned existing reference designs. thanksArticle: 112710
Antti wrote: > kenm schrieb: > > > Anyone know if there is any way to add pullups or pulldowns to IOBs in > > EDK other than via the UCF? > > My colleague is currently adding them using the UCF, but they then do > > not appear my RTL simulation of the board with other FPGAs, and the > > behaviour in simulation is not then correct. > > > > Many Thanks for any help, > > > > Ken Morrow > > add wrapper around system.vhd and add PULLUP PULLDOWN prims there > dont think there is any other way > > antti Many Thanks Antti, I have now added a wrapper to achieve what I needed. Pity there is not a tidier way. A box in EDK, per pad, to select PULLUP, PULLDOWN, KEEPER or NONE would be nice. Cheers, KenArticle: 112711
In my experience, the Micron models are very very good. I did find a subtle bug in one of their DDR SDRAM models, but it did not affect normal behaviour, and they fixed it as soon as it was brought to their attention. There are SDR SDRAM VHDL models available from Micron. The differences between one 4-band SDRAM and another 4-bank SDRAM are mote, so just pick one and go with it. GHArticle: 112712
"YD" <ydtechHAT@techie.com> wrote in message news:it3nm25ncgfv91nccrgaj8djvju7tifrk1@4ax.com... >>You and Fields. > Actually I was referring to YOU and Fields. Take Jim, Mike and Graham > along, make it a slurp-all-you-can fest. I've completely lost the point of this now. Have you?Article: 112713
Homer J Simpson wrote: > "YD" <ydtechHAT@techie.com> wrote in message > news:it3nm25ncgfv91nccrgaj8djvju7tifrk1@4ax.com... > > >>You and Fields. > > > Actually I was referring to YOU and Fields. Take Jim, Mike and Graham > > along, make it a slurp-all-you-can fest. > > I've completely lost the point of this now. Have you? HOLLY CRAP!!! THERE WAS A POINT??? LOL!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!Article: 112714
Late at night, by candle light, "Homer J Simpson" <nobody@nowhere.com> penned this immortal opus: > >"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message >news:n4ekm218lkea0s3m8bghc98t84b7mbq8h4@4ax.com... > >> Well, I started this thread, if that's what you mean, but it wasn't >> about any kind of sex. And who is "you two"? > >You and Fields. > > Actually I was referring to YOU and Fields. Take Jim, Mike and Graham along, make it a slurp-all-you-can fest. - YD. -- Remove HAT if replying by mail.Article: 112715
Late at night, by candle light, "Homer J Simpson" <nobody@nowhere.com> penned this immortal opus: > >"YD" <ydtechHAT@techie.com> wrote in message >news:it3nm25ncgfv91nccrgaj8djvju7tifrk1@4ax.com... > >>>You and Fields. > >> Actually I was referring to YOU and Fields. Take Jim, Mike and Graham >> along, make it a slurp-all-you-can fest. > >I've completely lost the point of this now. Have you? > Obviously. No. - YD. -- Remove HAT if replying by mail.Article: 112716
Symon wrote: > > You can use LVDS receivers in a Vcco = 3.3V bank. As Sean says, > it appears they're powered from Vccaux. However, you can only use > LVDS_DT receivers if Vcco = 2.5V. Check out the note on Figure 31, > DS083. I've posted here a couple of times about this, I don't think > I ever found out why it is so. > Other S3E LVDS termination trivia to make note of: - S3E constraint syntax uses the V4-style DIFF_TERM attribute for the input terminations, see Answer Record 19627 when using 8.2i, first read Answer Record 23829- using DIFF_TERM in the .ucf file is not supported, you need to stick it on an input primitive directly in the HDL instead - S3E "input-only" pins (IP_Lxx) don't have DIFF_TERMs - LVDS inputs _without_ DIFF_TERMs have a wide common mode input range - LVDS inputs _with_ DIFF_TERMs are limited to the much narrower Vod/Vocm range of the associated LVDS _output_ standard to meet the 120 ohm "spec" in the datasheet ( Rdt, table 77, DS312 v3.4, pp120 ) - that 120 ohm termination "spec" is specified only as a typical, without any min/max; is prefixed with a squiggle whenever mentioned in the datasheet; and, the termination is not modeled ( not even as an IBIS series element with static variation ) in the latest (v2.1) S3E IBIS files - see also Answer Records 17244, 13910 - despite vanishing from the latest Libraries Guide, those handy DIFF_OUT LVDS input buffers are still present in S3E, but the associated tool bugs have gotten worse BrianArticle: 112717
"YD" <ydtechHAT@techie.com> wrote in message news:gi9nm2lrbdh2b3l89oj6nu097g18gor66n@4ax.com... >>I've completely lost the point of this now. Have you? > Obviously. No. Then what has it to do with finding prime numbers on a microcomputer?Article: 112718
"Brian Davis" <brimdavis@aol.com> wrote in message news:1164683869.056807.57210@45g2000cws.googlegroups.com... > Symon wrote: >> >> You can use LVDS receivers in a Vcco = 3.3V bank. As Sean says, >> it appears they're powered from Vccaux. However, you can only use >> LVDS_DT receivers if Vcco = 2.5V. Check out the note on Figure 31, >> DS083. I've posted here a couple of times about this, I don't think >> I ever found out why it is so. >> > Other S3E LVDS termination trivia to make note of: > > - S3E constraint syntax uses the V4-style DIFF_TERM attribute for > the input terminations, see Answer Record 19627 > > when using 8.2i, first read Answer Record 23829- using DIFF_TERM > in the .ucf file is not supported, you need to stick it on an input > primitive directly in the HDL instead > > - S3E "input-only" pins (IP_Lxx) don't have DIFF_TERMs > > - LVDS inputs _without_ DIFF_TERMs have a wide common mode input range > > - LVDS inputs _with_ DIFF_TERMs are limited to the much narrower > Vod/Vocm range of the associated LVDS _output_ standard to meet the > 120 ohm "spec" in the datasheet ( Rdt, table 77, DS312 v3.4, pp120 ) > > - that 120 ohm termination "spec" is specified only as a typical, > without any min/max; is prefixed with a squiggle whenever mentioned > in the datasheet; and, the termination is not modeled ( not even as > an IBIS series element with static variation ) in the latest (v2.1) > S3E IBIS files > > - see also Answer Records 17244, 13910 > > - despite vanishing from the latest Libraries Guide, those handy > DIFF_OUT LVDS input buffers are still present in S3E, but the > associated tool bugs have gotten worse > > Brian > Brian, This is great information. Thanks for posting it. I was just doing some HyperLynx sims and saw no difference for the LVDS and LVDS_DT models. I thought it might have been because we're using an older version of HyperLynx. Why does Xilinx include the LVDS_DT as a separate entity, in the IBIS file, if it's not modeled properly. Well, Xilinx? BobArticle: 112719
The gpio.c and gpio.h can be found under the directory of your project: \project_dir\microblaze_0\libsrc\, which includes the driver code for the pheriphals in your system. Besides, you can find lots of valuable information in the EDK documentation, such as driver API. <icegray@gmail.com> ??????:1164638283.055434.51570@h54g2000cwb.googlegroups.com... > I'm searching Microblaze example projects and codes. I think There are > only a few example on the Xilinx web page. Also I can't find a document > about drivers of microblaze. Dou you know any documents about drivers > like as gpio.h or gpio.c etc? >Article: 112720
Just one thing, MicroBlaze can of course have a MMU. Wonder what the idea this it's impossible come from? Göran Bilski <burn.sir@gmail.com> wrote in message news:1164647777.560172.119220@f16g2000cwb.googlegroups.com... > Thank you for your answer Jon, > > > The JTAG problem was expected, and is easy to fix (write your own JTAG > block). Regarding the MMU, well, I have heard the MB cannot be modified > to include a MMU, is the same true for Mico32? > > > The reason that I posted my previous questions in the first place was > that if you synthesize a Mico32 project with, say, Quartus II you will > notice that it cant fit in _any_ Cyclone II devices. The reason is that > the lm32_ram block is designed in such way that the Quartus synthesizer > cannot infer MK4 blocks... > > > So my question to the list: has _anyone_ tried this CPU on Altera > devices? > > > regards, burns (still waiting for my ECP2M kit) > > Jon Beniston wrote: >> > - If I plan to use a non-Lattice FPGA, would things work as smooth or >> > will development become much more difficult? >> >> The only tricky bit will be the debugger, as that uses the dedicated >> Lattice JTAG block. Workaround that, and the rest should be no problem >> at all. >> >> > - Are any there any technical difficulties against porting Linux to >> > this CPU? (just out of curiosity and completely unrelated to my >> > project) >> >> It doesn't have an MMU, so the full blown Linux is out of the question. >> However, it should be relatively straight forward to port uCLinux. >> >> Cheers, >> Jon >Article: 112721
ghelbig@lycos.com wrote: > In my experience, the Micron models are very very good. I did find a > subtle bug in one of their DDR SDRAM models, but it did not affect > normal behaviour, and they fixed it as soon as it was brought to their > attention. > > There are SDR SDRAM VHDL models available from Micron. The differences > between one 4-band SDRAM and another 4-bank SDRAM are mote, so just > pick one and go with it. > > GH currently I m doing the interface between SDRAM and FPGA. but Controller is using VHDL. I have written my own code refering to a couple of verilog cores. I am facing problem in accessing another bank of same row simultaneuosly. I require a page burst of more than the columns available in single bank. Help me pls if you can. thanks, MDA.Article: 112722
Hi, you can try to finde any equivalent models at hynix or quimonda (former infinion). Or use freemodelfoundry.com. I had the same problem, because Xilinix Memory Interface Generator also provided verilog only models. Bye Helmut wallge wrote: > I am trying to write an SDRAM controller in VHDL for a mobile SDR SDRAM > that I want to be able to control via an FPGA on the same PCB. > I am having trouble with the verilog model. I have used both a samsung > and a micron model for the part (two compatible parts). Unfortunately > these models are not available in VHDL, and my verilog is pretty weak. > > I wondered if any one had some experience with memory models, both in > terms of using them to design memory controllers and debugging them > when they spit out spurious timing violations. > These verilog models in particular seem to send out all manner of > timing violations or functional problems that don't seem to be in line > at all with what the data sheet says regarding the timing and command > and control procedures (for doing a full page read or write, for > instance). > > Has any one else had trouble with bad/buggy models? What is the best > way to solve this problem? > What is the best way to go about designing a memory controller (I have > seen an example on Altera's website in VHDL (but it sucks), as well as > some others in open cores and one written for a homebrew graphics > accelerator card (manticore). I find the documentation and/or > functionality lacking in most of the aforementioned existing reference > designs. > > thanksArticle: 112723
You can also look here: http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/4312c0a1e204ced2/c2cc389ee809ce7d?hl=en#c2cc389ee809ce7d Bye HelmutArticle: 112724
Jim Granville wrote: >> I needed a delay to advance an address counter after a bus strobe >> ended. It was for a CPLD on a small plug-in board, and there was >> no other need for a clock on the board. So, I routed the signal out >> one pin, through a 1.5 K Ohm resistor, and into another pin. The >> input capacitance of the pin became the C of the RC time constant. >> This has worked well in the application. >> >> In your case, taking the signal through a similar external delay, and >> then >> bringing it back in to an AND2B1 for a pulse only on the rising edge, >> or an XOR if you want pulses on both edges should do what you want. >> Adjust the resistor value to get the desired time delay. >> >> It may also be possible to route to an unbonded IO pad with weak drive >> and get a fair amount of delay, easily 5 ns, but probably not 10. >> >> Jon > > > Al mentioned he wanted to avoid a PCB respin, but he could > certainly look for spare IO pin(s), and make use of the pin path delays. > It may even become probe-able ? > > -jg > Hi guys, well, as Jim said I wouln't like to respin the pcb, but still the IO delay could be used because there are some close pins which are not used and can be easily shorted, but unfortunately I need to instantiate a lot of these delays. So either I implement a free running counter with this delay to generate an internal clock and then do all the things I need, or I simply try to count on the internal routing delay, which is quite ok on post-layout sim, but still have to try it on the hardware! I will post my results next week, when I will do some tests. Thanks to all Al -- Alessandro Basili CERN, PH/UGC Hardware Designer
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