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"daver2" <davidroberts@siemens.com> wrote in message news:1162220709.470867.305120@e64g2000cwd.googlegroups.com... >I am implementing an extremely old logic design (circa 1965!) on a > Xilinx Virtex 4 (XC4VLX25). > > For those interested - it is the logic for the computer that flew to > the moon and back! The design is based on approximately 5,000 3-input > NOR gates and not a flip flop in sight! Aw dang, I was going to do that. Well, it was on my 'to do' list for when I have time. But I'm working 12 hour days and hope to do so for quite a while, so I don't have much time left for hobby stuff. I did get round to having a look at it though (see http://www.howell1964.freeserve.co.uk/logic/apollo_clone.htm) and I recall thinking that it might not be a good idea to directly translate the circuit into loads of NOR gates. I was going to try writing a higher level VHDL description to do a functional equivalent that was better suited to current FPGA technology. Good luck with the project - I look forward to fitting it into my own FPGA chip.Article: 111176
"Elmo Fuchs" <maerchenprinz@arcor.de> wrote in message news:4545fdf6$0$5712$9b4e6d93@newsspool3.arcor-online.net... > > Because of the restricted amount of available pins on the device I > selected > (Virtex-4 FX40 with 352 user I/Os) I would like to use just one clock > input > on each side of the FPGA, thereby saving clock multiplexer inputs which I > can use as normal GPIOs, and use an external clock multiplexer instead for > my 3 clocks. > Has anyone made experience with such or similar solution? Has anyone used > an > external clock multiplexer device for frequencies up to 500 MHz, yet? Is > there any recommendation which chip I could use for this application in > terms of jitter, etc.? And by the way... is my approach advisable, at all? > > Any comments are appreciated. > > Regards Elmo > Hi Elmo, Firstly, I recommend you appreciate Andy's comments. :-) I detect a voice of experience in his good advice! Then, when you decide to carry on with your original plan regardless, Google this:- "Runt Pulse Eliminator" site:micrel.com HTH, Syms.Article: 111177
Hi, Where can I find a specification on how stable the internal clock of Xilinx's CPLDs (in this case the XC9572-7) is? For example tolerance, and drift of the frequency for ambient temperature. I can't find it in the product specs, and also not on Xilinx's website (to my surprise). The only thing the data sheet says is that f_SYSTEM has a min-value of 83.3. I also can't find anything about how to connect this system clock to a signal in my VHDL code. I will use the CPLD to generate a PWM signal for control of a servo, and therefore the exact length of the pulses, in absolute time, is critical. If the internal clock is not considered reliable enough I would have to use an external chyrstal oscillator circuit. I could probably at least tolerate an error of a couple of percent of the frequency. Thanks in advance, CarlArticle: 111178
"KJ" <kkjennings@sbcglobal.net> wrote in message news:2_71h.17705$TV3.7155@newssvr21.news.prodigy.com... > > What you're considering as fundamental seem to be the things things that > you started your career with and were thought to be 'fundamental' back > then, This was EXACTLY the point I wanted to make... There are two issues here - one is a valid point about it being useful to understand one or two layers below the abstraction you're working at, and a tangential one which is merely a placeholder for the vague regret we all feel that very much younger people are capable of doing something like our jobs, using a changing set of skills. Technological progression, in pushing down what's fundamental and up what's possible RELIES on people being able to concentrate on only a limited number of layers in the stack. The guys at CERN can't spend their time worrying about how you would use a boson to make a better automobile door handle any more than people programming desktop computers should worry about electronics. One can endlessly and enjoyably debate which particular things are 'fundamental' to solving a particular task, but one shouldn't fool oneself that there's a right answer. WillArticle: 111179
"Rob" <robnstef@frontiernet.net> wrote in message news:iwU0h.4200$Ka1.3743@news01.roc.ny... > > I know you addressed this to Brad, but my answer would be all of the > above. I would counter your question with: if your design necessiates an > FPGA, and that FPGA is capabable of performing the deserialization, why > would you use the National chips? Because it's easier. Which means that I can do something else, which perhaps hasn't been done by someone else already... > Sure, if you have to build your own, it can get tricky with setup/hold > times, jitter, skew, and clock phasing--but what's life w/o challenges? Hmm. There's a hint of 'when did you stop beating your wife?' to that. Maybe I can parry by saying that I see the real engineering challenge as to find the best way to do things, which doesn't necessarly mean 'gratuitously difficult'. Though I'll concede I do like to go for at least a little bit of gratuitous difficulty on every new project. If I built my own cameralink, and the camera mysteriously went out of sync by one pixel every three weeks, I'd really regret it! WillArticle: 111180
"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:12kcsm5kh166g4a@corp.supernews.com... > > Pin count and input/output flexibility. Pin-count is a good one - I hadn't thought of that. Does the Virtex design track nicely to the 3M connectors? Cheers, WillArticle: 111181
You can't; the serial port is a debug console for the embedded processor. To program the device, you need a Xilinx-compatable JTAG adapter. GHArticle: 111182
If you need absolute timing precision, go for a xtal oscillator package ( about $ 1.-) If you just want a defined duty cycle, you can use the internal oscillator, but the frequency will vary more than an octave (2-to-one) Peter Alfke, Xilinx Applications On Oct 30, 3:42 pm, c...@telia.com wrote: > Hi, > > Where can I find a specification on how stable the internal clock of > Xilinx's CPLDs (in this case the XC9572-7) is? For example tolerance, > and drift of the frequency for ambient temperature. I can't find it in > the product specs, and also not on Xilinx's website (to my surprise). > The only thing the data sheet says is that f_SYSTEM has a min-value of > 83.3. I also can't find anything about how to connect this system clock > to a signal in my VHDL code. > > I will use the CPLD to generate a PWM signal for control of a servo, > and therefore the exact length of the pulses, in absolute time, is > critical. If the internal clock is not considered reliable enough I > would have to use an external chyrstal oscillator circuit. I could > probably at least tolerate an error of a couple of percent of the > frequency. > > Thanks in advance, > CarlArticle: 111183
Hi. I have to write FPGA sintezible VHDL code for FFT and IFFT (for 128 points (can be generic too)). Can Anybody help me, please. Any kind of help would help me. Thanks peopleArticle: 111184
Hi all I'm a design engineer trying to evaluate the large number of possibilities for adding Ethernet to our embedded system. So far I've been very impressed by the Altera Cyclone II with NIOS II and free lightweight TCP/IP stack. Adding Ethernet appears to amount to the Cyclone II and a MAC+PHY chip like LAN91C111 (or equivalent). Anyone have experience with using the Cyclone II merely for Ethernet? Should I try to put the MAC inside the FPGA and just use an external PHY? Any recommendations for a communication protocol between the FPGA and my DSP? SPI seems the most obvious choice for reasonably high bandwidth (>6 Mbps). Right now my DSP runs from a 1.5 Mbps UART so mimicking this data flow would save me a bunch of assembly code changes. However, I'd like to send more data back to the host so could use upwards of 6 Mbps. Also, I'm interested in general recommendations for System on a Programmable Chip (SOPC), which Altera is obviously highly interested in advancing. It seems very attractive since I could eventually get rid of the DSP by simply creating a second NIOS II processor within the FPGA and porting my assembly code to C. The upgrade path is straightforward and indefinite since Altera will keep coming up with even better FPGAs. Any caveats or warnings? Lastly, are there major reasons I should be considering Xilinx instead? Thanks in advance for the help! -ToddArticle: 111185
I agree, and I was not making a moral statement. Just that the ranks of engineers that can debug low-level (fundamental) problems are shrinking. Soon only IC designers will understand these things (because they are still their livelihood), since everybody else has "moved up". ( I have a son who works in software R&D, and we have very limited common ground in electronic things). I was, however, bemoaning the fact that so many things in our lives have become black mystery boxes that defy "healthy curiosity". And that phenomenon is new, within the last 50 years, a short time in the evolution of technology. Peter Alfke On Oct 30, 3:48 pm, "Will Dean" <w...@nospam.demon.co.uk> wrote: > "KJ" <kkjenni...@sbcglobal.net> wrote in messagenews:2_71h.17705$TV3.7155@newssvr21.news.prodigy.com... > > > > > What you're considering as fundamental seem to be the things things that > > you started your career with and were thought to be 'fundamental' back > > then,This was EXACTLY the point I wanted to make... > > There are two issues here - one is a valid point about it being useful to > understand one or two layers below the abstraction you're working at, and a > tangential one which is merely a placeholder for the vague regret we all > feel that very much younger people are capable of doing something like our > jobs, using a changing set of skills. > > Technological progression, in pushing down what's fundamental and up what's > possible RELIES on people being able to concentrate on only a limited number > of layers in the stack. > > The guys at CERN can't spend their time worrying about how you would use a > boson to make a better automobile door handle any more than people > programming desktop computers should worry about electronics. > > One can endlessly and enjoyably debate which particular things are > 'fundamental' to solving a particular task, but one shouldn't fool oneself > that there's a right answer. > > WillArticle: 111186
Xilinx have an FFT IP core. Search their site (www.xilinx.com) and download the IP core datasheet to give you some idea what its all about. Jaksa wrote: > Hi. > I have to write FPGA sintezible VHDL code for FFT and IFFT (for 128 > points (can be generic too)). Can Anybody help me, please. Any kind of > help would help me. Thanks peopleArticle: 111187
Which tools and which FPGAs does your school use? "Jaksa" <Jaksa1984@gmail.com> wrote in message news:1162255557.907076.68510@m73g2000cwd.googlegroups.com... > Hi. > I have to write FPGA sintezible VHDL code for FFT and IFFT (for 128 > points (can be generic too)). Can Anybody help me, please. Any kind of > help would help me. Thanks people >Article: 111188
John_H wrote: > Which tools and which FPGAs does your school use? > > > "Jaksa" <Jaksa1984@gmail.com> wrote in message > news:1162255557.907076.68510@m73g2000cwd.googlegroups.com... > > Hi. > > I have to write FPGA sintezible VHDL code for FFT and IFFT (for 128 > > points (can be generic too)). Can Anybody help me, please. Any kind of > > help would help me. Thanks people > > I am using Altera Quartus II software. Why?Article: 111189
c.j.w@telia.com wrote: > Hi, > > Where can I find a specification on how stable the internal clock of > Xilinx's CPLDs (in this case the XC9572-7) is? For example tolerance, > and drift of the frequency for ambient temperature. I can't find it in > the product specs, and also not on Xilinx's website (to my surprise). > The only thing the data sheet says is that f_SYSTEM has a min-value of > 83.3. I also can't find anything about how to connect this system clock > to a signal in my VHDL code. > > I will use the CPLD to generate a PWM signal for control of a servo, > and therefore the exact length of the pulses, in absolute time, is > critical. If the internal clock is not considered reliable enough I > would have to use an external chyrstal oscillator circuit. I could > probably at least tolerate an error of a couple of percent of the > frequency. I think I can see a miss-match here :) The f_system is the maximum value the Chip is guaranteed to clock (external Clock) at (usually with some given test pattern, to make it a usefull number ) It is NOT a spec value for some internal clock oscillator!!. So, yes, you will have to provide an external Osc, with Sq wave drive. -jgArticle: 111190
"Will Dean" <will@nospam.demon.co.uk> wrote in message news:4546910e$0$631$bed64819@news.gradwell.net... > "Rob" <robnstef@frontiernet.net> wrote in message > news:iwU0h.4200$Ka1.3743@news01.roc.ny... >> >> I know you addressed this to Brad, but my answer would be all of the >> above. I would counter your question with: if your design necessiates an >> FPGA, and that FPGA is capabable of performing the deserialization, why >> would you use the National chips? > > Because it's easier. Which means that I can do something else, which > perhaps hasn't been done by someone else already... Setting up the deserilizer within an FPGA, if you can use the mfg's module (which you almost always can when it comes to cameral/channel link), takes about 10 minutes--would you consider that easy? And if by chance you have to build your own, and you understand the hardware, it doesn't take that much longer. And in the end you have the tool in your box you can pull out for the next job (reuse = no time). > >> Sure, if you have to build your own, it can get tricky with setup/hold >> times, jitter, skew, and clock phasing--but what's life w/o challenges? > Hmm. There's a hint of 'when did you stop beating your wife?' to that. I do have a large quantity of white muscle t-shirts with food stains on them!! > Maybe I can parry by saying that I see the real engineering challenge as > to find the best way to do things, which doesn't necessarly mean > 'gratuitously difficult'. Though I'll concede I do like to go for at > least a little bit of gratuitous difficulty on every new project. The real benefit, at least in my world (image processing), is that I always have an FPGA on the board which can do the interface; and my company is always looking to cut board costs since they sell 10's and sometimes 100's of thousands of units. > > If I built my own cameralink, and the camera mysteriously went out of sync > by one pixel every three weeks, I'd really regret it! I believe statistically speaking it is almost impossible for an FPGA to mysteriously go out of sync--there's always a logical reason. I work with a group that tests these ports by running massive amounts of continuous data through these interfaces--they all end up being solid. I have never run into a mysterious missing pixel. Furthermore, with the FPGA you can automatically adjust for skew in the system. The National chips can't do this. And Brad does bring up another great point about pin count. Take care, Rob > > Will > >Article: 111191
Todd wrote: > So far I've been very impressed by the Altera Cyclone II with NIOS II > and free lightweight TCP/IP stack. Adding Ethernet appears to amount > to the Cyclone II and a MAC+PHY chip like LAN91C111 (or equivalent). > > Anyone have experience with using the Cyclone II merely for Ethernet? > Should I try to put the MAC inside the FPGA and just use an external > PHY? Yes, we did some preliminary work for a customer using the opencores MAC and the LWIP stack. There were stability problems, and evidence pointed to the opencores MAC, rather than LWIP. In the end the customer went with a commercial adaptation of the MAC and IP stack, though they still weren't happy with the end results. Granted, they wanted SSL... What bandwidth do you want out of it? Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 111192
marc_ely wrote: > Has anyone recently done any benchmarking of Windows PC's for Xilinx > ISE Compiles? > > Is ISE multithreaded? > Can it use multiple processors (or cores)? > Do big CPU caches help? > > Regards > Marc > P4-3GHz HT 2GB DDR2-533 RAM While the CoreDuo looks the thing right now, on the disk side I'd be interested to know if the new IDE Flash drives that go up to 32GB are any use as a replacement for high RPM drives. The only reviews I have seen (Toms IIRC) obviously have much lower latency but not yet much throughput around 30MBytes/sec but at least the ms delays should now be us delays. At this stage I wouldn't be concerned about wearout as I expect these things to be get replaced sooner or later, prices seem to be falling on Flash much faster than DRAM now and the throughput is bound to reach closer to PATA max rates. just a thought John JaksonArticle: 111193
>> > Hi. >> > I have to write FPGA sintezible VHDL code for FFT and IFFT (for 128 >> > points (can be generic too)). Can Anybody help me, please. Any kind of >> > help would help me. Thanks people >> > >> John_H wrote: >> Which tools and which FPGAs does your school use? >> > I am using Altera Quartus II software. Why? > We also need to know the name of your school. BobArticle: 111194
I consider myself to still be a youngster. I'm only 24 years old and I'm relatively recently out of college, but I find nothing you mention here foreign. This stuff is still being taught in schools (though I might argue my school didn't do a great job of it). The reality of it all is that low level electronics remains useful. I have never once regretted understanding how a transistor works. I have recently been looking a flip flop designs since my company was having a hard time meeting timing. While I'm not an expert, others are, and I've yet to ever meet a person who know this kind of stuff and doesn't want to share that knowledge. The kinds of things I deal with on perhaps a monthly basis are: * What are the costs of transmission gate input flip flop versus a cmos input? * Can Astro synthesis a 4GHz clock tree? * How much drive would it take to overpower the drive of another cell (multiple outputs tied together)? * What are possible resolve states when you have a race on an async set/reset flop? People still have to solve these problems. They aren't going away. The younger engineers still face these. Now I admit that I do work as an IC designer, but ICs are here to stay. They may become fewer, but as long as they exist and get more complicated, plenty of people will be employed in that industry. My point to add to this is that many older engineers have difficulty grasping new ways of operating. Convincing experienced engineers that synthesis tools actually work can be like pulling teeth sometimes. Just the other day, some engineers were ranting about some code that a contractor wrote that was very very behavioral. They were complaining about how that was killing timing and adding 10s to 100s of levels of logic. They hadn't tried it out. I ran it through the synthesizer and it was *faster* than the low level code. I don't see knowledge of the really low level stuff going away. In fact I see it increasing. Things like quantum physics and maxwell's equations are getting used more and more to make electronics work. TCAD engineers live in this realm and TCAD is getting used more and more for things like process definition and modeling. What I see happening is the rift between the low level process/cell designers and the logic designers growing as the logic designers get more high level and the process/cell designers have to get closer to the real physics of the system. Not all of the knowledge is necessary for all parties. The fact is that if a good library is present (and nothing super funky is in the design), a logic designer doesn't need to know electronics. They simply need to know the how to work with the models that are employed by the tools. -ArlenArticle: 111195
Good for you, Arien. Over the past 35 years I have interviewed many hundreds of new college grads. Among others I always asked a very simple question: Show me how you analyze the max clock frequency of a 2-bit shift register (what data-sheet parameters do you need, where do they apply, and what is the math between them?). Most can do that, after some prodding. Then: What happens to the max frequency when there is clock skew between the two flip-flops. About half gave the wrong answer to this slightly tricky question. So they did not get hired...In a new grad I do not look for factual knowledge, but for the ability to think clearly. Some passed this test with flying colors, sometimes amazed at the implication of their own answer. I was looking for nuts-and-bolts applications engineers, and other interviewers tested their systems and software skills. We were (and are) pretty selective... Peter Alfke ======================== On Oct 30, 7:21 pm, "gallen" <arlen...@gmail.com> wrote: > I consider myself to still be a youngster. I'm only 24 years old and > I'm relatively recently out of college, but I find nothing you mention > here foreign. This stuff is still being taught in schools (though I > might argue my school didn't do a great job of it). The reality of it > all is that low level electronics remains useful. I have never once > regretted understanding how a transistor works. I have recently been > looking a flip flop designs since my company was having a hard time > meeting timing. While I'm not an expert, others are, and I've yet to > ever meet a person who know this kind of stuff and doesn't want to > share that knowledge. > > The kinds of things I deal with on perhaps a monthly basis are: > * What are the costs of transmission gate input flip flop versus a > cmos input? > * Can Astro synthesis a 4GHz clock tree? > * How much drive would it take to overpower the drive of another cell > (multiple outputs tied together)? > * What are possible resolve states when you have a race on an async > set/reset flop? > > People still have to solve these problems. They aren't going away. > The younger engineers still face these. > > Now I admit that I do work as an IC designer, but ICs are here to stay. > They may become fewer, but as long as they exist and get more > complicated, plenty of people will be employed in that industry. > > My point to add to this is that many older engineers have difficulty > grasping new ways of operating. Convincing experienced engineers that > synthesis tools actually work can be like pulling teeth sometimes. > Just the other day, some engineers were ranting about some code that a > contractor wrote that was very very behavioral. They were complaining > about how that was killing timing and adding 10s to 100s of levels of > logic. They hadn't tried it out. I ran it through the synthesizer and > it was *faster* than the low level code. > > I don't see knowledge of the really low level stuff going away. In > fact I see it increasing. Things like quantum physics and maxwell's > equations are getting used more and more to make electronics work. > TCAD engineers live in this realm and TCAD is getting used more and > more for things like process definition and modeling. What I see > happening is the rift between the low level process/cell designers and > the logic designers growing as the logic designers get more high level > and the process/cell designers have to get closer to the real physics > of the system. Not all of the knowledge is necessary for all parties. > The fact is that if a good library is present (and nothing super funky > is in the design), a logic designer doesn't need to know electronics. > They simply need to know the how to work with the models that are > employed by the tools. > > -ArlenArticle: 111196
Jaksa wrote: > John_H wrote: >> Which tools and which FPGAs does your school use? >> >> >> "Jaksa" <Jaksa1984@gmail.com> wrote in message >> news:1162255557.907076.68510@m73g2000cwd.googlegroups.com... >>> Hi. >>> I have to write FPGA sintezible VHDL code for FFT and IFFT (for 128 >>> points (can be generic too)). Can Anybody help me, please. Any kind of >>> help would help me. Thanks people >>> > I am using Altera Quartus II software. Why? Knowing it's Altera helps but you haven't mentioned the target FPGA. If your professor lets you target any device, the latest FPGAs should have multiplier/accumulators built-in. The slightly older FPGAs have multiplers in silicon but no integrated MACs. If your lab is only outfitted with old technology, you could even be stuck without multipliers making the job significantly more difficult. Luckily I don't know enough about the nuances of the Altera architectures to help you out.Article: 111197
The Ethernet MACs are mostly commerically available and they're not free. Xilinx has its own Ethernet MAC and it's easy to integrate it into the MicroBlaze soft processor. I think whether choosing MAC+PHY chip or MAC(FPGA) + PHY chip is largely dependent on your budget. For mass production, MAC implemented inside FPGA seems a better choice and a shorter time-to-market can be expected. If you simply want to add Ethernet to your embedded system, you may consider using microprocessors from Rabbit semiconductor, instead of FPGA. Although I do not using their chips, I believe it's the most direct and easiest solution to your post. Good luck, JJ "Todd" <tschoepflin@gmail.com> ??????:1162255661.055244.134860@e64g2000cwd.googlegroups.com... > Hi all > > I'm a design engineer trying to evaluate the large number of > possibilities for adding Ethernet to our embedded system. > > So far I've been very impressed by the Altera Cyclone II with NIOS II > and free lightweight TCP/IP stack. Adding Ethernet appears to amount > to the Cyclone II and a MAC+PHY chip like LAN91C111 (or equivalent). > > Anyone have experience with using the Cyclone II merely for Ethernet? > Should I try to put the MAC inside the FPGA and just use an external > PHY? > > Any recommendations for a communication protocol between the FPGA and > my DSP? SPI seems the most obvious choice for reasonably high > bandwidth (>6 Mbps). Right now my DSP runs from a 1.5 Mbps UART so > mimicking this data flow would save me a bunch of assembly code > changes. However, I'd like to send more data back to the host so could > use upwards of 6 Mbps. > > Also, I'm interested in general recommendations for System on a > Programmable Chip (SOPC), which Altera is obviously highly interested > in advancing. It seems very attractive since I could eventually get > rid of the DSP by simply creating a second NIOS II processor within the > FPGA and porting my assembly code to C. The upgrade path is > straightforward and indefinite since Altera will keep coming up with > even better FPGAs. Any caveats or warnings? Lastly, are there major > reasons I should be considering Xilinx instead? > > Thanks in advance for the help! > -Todd >Article: 111198
Sorry, I was lazy and anwered what the clock would be, if there were one. In fact, there is no internal clock, unless you build one out of a chain of inverter/noninverters. Get a crystal oscillator, they are cheap and good! Peter Alfke On Oct 30, 4:56 pm, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > c...@telia.com wrote: > > Hi, > > > Where can I find a specification on how stable the internal clock of > > Xilinx's CPLDs (in this case the XC9572-7) is? For example tolerance, > > and drift of the frequency for ambient temperature. I can't find it in > > the product specs, and also not on Xilinx's website (to my surprise). > > The only thing the data sheet says is that f_SYSTEM has a min-value of > > 83.3. I also can't find anything about how to connect this system clock > > to a signal in my VHDL code. > > > I will use the CPLD to generate a PWM signal for control of a servo, > > and therefore the exact length of the pulses, in absolute time, is > > critical. If the internal clock is not considered reliable enough I > > would have to use an external chyrstal oscillator circuit. I could > > probably at least tolerate an error of a couple of percent of the > > frequency.I think I can see a miss-match here :) > The f_system is the maximum value the Chip is guaranteed to clock > (external Clock) at (usually with some given test pattern, to make it a > usefull number ) > > It is NOT a spec value for some internal clock oscillator!!. > > So, yes, you will have to provide an external Osc, with Sq wave drive. > > -jgArticle: 111199
Peter wrote: >I may be (overly?) sensitive to a nasty tone, and >I don't like to be called a "Troll of Implausible Deniability". John_H wrote: > It seems the apparant name calling was the problem. > Brian - you can fill us in on what you actually meant if > it's different from Peter's interpretation. Personally, > I saw other interpretations and saw the text as trying > "to be cute, but [he] blew it." That comment was not directed at, nor intended to be an insult to Peter, who comports himself as would be expected of a silver-haired engineer. If you look at the whole paragraph, I wrote: > >And to top it all off, if you then post a summary of said >problems here on comp.arch.fpga, you run the risk of being >flamed by Xilinx's own Troll of Implausible Deniability. > From my perspective, that is an accurate, albeit tongue-in-cheek, description of Austin's posting tactics in the past when I've posted detailed DCI/LVDS problem summaries to the newsgroup. But there's no accounting for my sense of humor. > >The original post is pertinent. I stopped trying to submit >webcases a while back, instead calling straight to the Xilinx >hotline to kickstart the issue > I've given up on them completely except for bugs I can't work around, or simple questions for which I can't locate the answer. Each of us has bumped into differing subsets of all the sharp and pointy bits in the tools and documentation; if I choose to list some of those problems here, that does not mean I'm anti-Xilinx. In comparison to WebCases and Xilinx website searches, once I've posted a problem summary, list of relevant Answer Records, or code example here to the newsgroup, I can easily find it again from any computer. Brian
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