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Colin, So, the device should take on the new configuration for the IO standard once configured. Yes? JTAG or normal IO use should not make any difference: the IO pin can not revert to the default programming just because JTAG is in use? Is this what you have confirmed? Yes, or No, please. I already know my mind doesn't work the same as yours. Austin colin wrote: > Austin Lesea wrote: > >>All, >> >>I posted that quote because it actually did (but very poorly, I agree) >>state that after the device is configured, the pins assume their new >>configured standards, and states. >> >>The tech answer is slightly better written, but is goofy as to say >>"most" or "almost all" which is pretty useless (just poor writing). >> >>The issue is that since the BSDL file is only accurate before >>configuration, there is a "recommendation" NOT to use boundary scan >>after configuration, because you need to then create a design specific >>BSDL file to use any of the JTAG scan software tools out there. And, >>since we don't have software to do that, we just say "don't do that" >>rather than explain why. > > > Err Austin, you do have a tool to do that, it is called BSDLANNO.exe > and comes as standard with webpack. See previous posts, you give it the > output of your design and the original BSDL file and it creates a bsdl > that reflects your programmed CPLD. > > My original support question was, will pins that are functionally SSTL > output only, be SSTL input during JTAG, to be told that once > functionally an output then its only an output for jtag. I then > disproved that by creating a pinA <= pin B design and looked at the new > BSDL (which used my pin names so I'm happy with how I'm driving > bsdlanno). So I think that coolrunner II is included in "most" but your > support line doesn't yet agree. > > I'm sorry if I've communicated badly, my mind obviously works in a > simillar way to Rickmans rather than yours :-) and this forum works on > goodwill rather than expecting people to read reams of typing I > obviously got the balance wrong. > > Interestingly there is a jtag usenet group but all the posts are in > chinese which I guess reflects that western engineers know how to > create great fpga IP and asians know how to manufacture them. > > Colin (from the UK) > > >>Peter and I will see about rewriting this so it makes better sense. >> >>In no way does my post suggest that you 'RTFM': rather, I spend a lot >>of time to search for information, and post where I found it. Just >>because I read very fast in no way suggests that I think you could have, >>or should have, found this information. Again, please do not put words >>in my mouth! >> >>I still have no idea if this is the "answer" to the "question" Colin >>posed originally. >> >>Austin > >Article: 110501
I found the problems come from other SPI devices on board, which should be disabled but I didn't. "Ju, Jian" <eejju@polyu.edu.hk> 写入消息新闻:1160991548.300849@nsserver1.polyu.edu.hk... > Hi all, > > I'm trying to run the ADC chip LTC1407a on the spartan 3e starter kit. > Both the function and timing simulation is validated and the signal > AD_CONV and SPI_SCK is just as wanted when I use an oscilloscope to > observed the board signal. In other words, 34 SPI_SCK after 1 clock period > of AD_CONV. However, the data output is always 0x3FFF when a 10kHz sine > wave is applied on both channel. > > Firstly I used a 50M clock and as it can't work properly, I lower the > clock using the internal DCM to 10MHz and use the chipscope to get the > signals out. I found the signal SPI_MISO, which is the output serial data > from the ADC, is always '1'. But the signal on board observed by > oscilloscope keeps changing '0'/'1'. > > Any suggestions? > > Thanks, > JJ >Article: 110502
Hi Paul, Thanks a lot! I also want to know does Cadence provide such verification methodology like Synopsys and Mentor. And what's Synopsys (IIRC)'s IIRC mean? Best regards, Davy Paul Uiterlinden wrote: > Davy wrote: > > > Hi all, > > > > I want to use SystemVerilog to construct next generation of my > > testbench. > > > > And I found Synopsys provide VMM while Mentor provide AVM. Anyone > > can give some comment on these two methodology? Or are they similar? > > A comparison of AVM and VMM in Verification Horizons: > http://lyris.mentor-info.com/t/5001/4363723/7325/1846/ > PDF version: > http://lyris.mentor-info.com/t/5001/4363723/7330/1851/ > > Four articles in the EETIMES on the SystemVerilog reference > verification methodology: > http://www.eetimes.com/news/design/showArticle.jhtml?articleID=183702807 > http://www.eetimes.com/news/design/showArticle.jhtml?articleID=187001913 > http://www.eetimes.com/news/design/showArticle.jhtml?articleID=188703275 > http://www.eetimes.com/news/design/showArticle.jhtml?articleID=192501500 > > The first is by Mentor, the second by Synopsys (IIRC). Both of course > with their own biases. > > > I don't know if Synopsys's VMM is open document and open source > > code. > > As far as I know the VMM book is not an open document: > http://www.vmm-sv.com/ > > The AVM cookbook clearly is. > > The same goes for VMM and AVM itself. AVM is opensource, VMM source is > heavily licensed (word choice from Verification Horizons). > > -- > Paul.Article: 110503
On Xilinx's website page:
http://www.xilinx.com/ise/embedded/edk_examples.htm
There are 2 LWIP EDK example designs, one of which is supposed to support
the hard Gigabit temac core on the Virtex 4 FX series. In fact, both zip
files are identical and for the 10/100 soft core. Has anybody found the
Temac example, or heard from Xilinx whether the Temac example will be out
with the next EDK service pack (due about now)?
Extract from the Xilinx page:
=============================
PowerPC Supported Examples
LwIP Sockets API:
Using 10/100 regular Ethernet core (zip)
Using 10/100/1000 hard Ethernet core (zip) << SAME AS PREV.
Will now be supported on the ML403 board
=============================
It would ease my life considerably to see the gigabit source, since ,being
new to the EDK, I am struggling trying to convert the 10/100 design for the
Temac.
Paul
Article: 110504Austin Lesea wrote: > Colin, > > So, the device should take on the new configuration for the IO standard > once configured. Yes? > > JTAG or normal IO use should not make any difference: the IO pin can > not revert to the default programming just because JTAG is in use? > > Is this what you have confirmed? Yes, or No, please. I already know my > mind doesn't work the same as yours. I don't think it is a matter of minds working differently, they are mostly the same with a few differences in left/right organization. The important issue is to read what is being written in enough detail to get what is different about the thoughts. "My original support question was, will pins that are functionally SSTL output only, be SSTL input during JTAG" I believe what he is asking about here is whether a pin that is configured for output only as set up in the JTAG configuration be capable of bidirectional testing using boundary scan. I would expect the answer to be, "it will work in either direction during boundary scan". But I can see where he would have some concern about this since the pin will be working in the SSTL voltage levels that are configured by JTAG. So will the configuration also limit whether the pin can be boundary scan tested by both input and output?Article: 110505
Does anyone have any good links to groups/companies working on GSM or CDMA IP cores? Or maybe something like a GSM SDR?... Thought I would start here prior to my google search, after all it is a google group. ThanksArticle: 110506
The Lattice parts have hard IP for the MAC and LTSSM (MACO), I'll look more deeply into the LXT, complete endpoint huh? I suppose that has some value. (is this where I'm supposed to cry Uncle?) One might assert it's splitting hairs suggesting other players have nada...but marketing is marketing...and Xilinx didn't get to be a billion dollar company by doing it badly....Since Xilinx is the only one talking about their 65nm products I suppose they are, by default, the defacto leader in that arena. I just wanted to point out that the LXT is not the first FPGA with hardened communications IP blocks, that's all. Sorry to have ruffled your feathers. Those Xilinx parts, they're pretty nice too....and I acknowledged that a long time ago.... ;) Austin Lesea wrote: > dd, > > Hardened PCIe (in V5). Not a core. Don't see any hardened PCIe on > Lattice website. Am I missing something? > > Not that the Lattice SC products are not nice, they are, and I have > acknowledged that a long time ago. But I don't see any hardened PCIe > core(s). Is this something they are keeping secret? > > Austin > > ddrinkard wrote: > > Hmmm, first in industry with built-in PCI-express? Lattice SCM devices > > have built-in PCI express, have had since Feb (along with a boat-load > > of other stuff too). 100mW per channel, finally catching up with > > Altera and Lattice... S3A may have built-in Flash...seen that before > > too. It's kinda fun watching Xilinx playing catch-up.... ;) > > > > > > Antti wrote: > >> Antti schrieb: > >> > >>> http://www.xilinx.com/prs_rls/2006/silicon_vir/0696v5lxt.htm > >>> > >>> already pricing given for 1000qty not bad at all. > >>> > >>> unfortunatly the LXT related user guides > >>> ug194 EMAC > >>> ug196 GTP > >>> ug197 PCIe > >>> > >>> are all deadlinks at the moment but hopefully those documents become > >>> available shortly. > >>> > >>> new eval boards (besides ML501) are > >>> > >>> ML505 - allows PCIe testing > >>> ML523 - GTP characterization board > >>> ML555 - 8x PCIe card > >>> > >>> GTP has OOB support for PCIe/SATA and supports spread spectrum clocking > >>> as well. > >>> > >>> Antti > >> correction ug194 and ug196 are already available (appearead 6 minutes > >> after the post), so the only missing one is the PCIe UG > >> > >> myself > >Article: 110507
Hi, I updated the GTKWave for Win32 port I am maintaining. It's at 3.0.13 now: http://www.dspia.com/gtkwave.htmlArticle: 110508
Thomas Stanka wrote: > Hi, > It cost only time by doing effectly several runs and using the best > result (you could even have the results from all runs saved on HD) > I think, that timing critical layout gets a bigger problem if your > utilisation is >>95% (YMMV I had only one A54SX72 design exceeding 95% > sequential resources). > To be more precise it only takes more than 90% of the sequential logic, so that's why I'm not yet having any trouble, because I think that the major problem will occur when you have a lot of combinational logic to go through. (By the way, what does YMMV mean???) > > I never used the IDE, what causes your pain? The export of netlist and > sdf from designer tool is very simple (I wish all Vendors would allow > such a simple export of data in their tools). > The Designer is very easy to use and I appreciated it a lot, my only problem is that all my collegues used to make projects with LIBERO IDE and I had to adapt myself to their standards. Now I only use Libero to set up all the directories in such a way I'm used to, but then I use Synplify by itself and Modelsim as well. Libero is only handy when it creates the .do script file for Modelsim and goes through the post-synthesis or the post-layout simulation just in case you have exported the back-annotate from the Designer. > bye Thomas > -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 110509
Mike Treseler wrote: > Al wrote: > > I would recommend this order: > > 1. emacs+vcom for entry and syntax check of uut and > functional testbench code. > define a vhdl-mode project for the source directory. > 2. Modelsim to debug uut and functional testbench code. > 3. Run synplify on the debugged uut source and fix synthesis errors. > 4. Run libero place+route on the synplify netlist and > check static timing. > A post-layout sim is not always needed for a synchronous design. > > This keeps libero out of the loop until it is actually needed. > > -- Mike Treseler Hey that's a great suggestion! Anyway to start Designer is not really needed Libero, you can even live without it. I had never had this approach, in the sense that I always checked syntax directly with the Synplify, moreover I always used the testbench just for the post-synthesis simulation, never for the functional, maybe this can help me quicker to find out "functional" problems. Thanks Mike -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 110510
Joseph Samson wrote: > Is anyone running ISE on an Intel based Macintosh? I'm considering a > MacPro with dual Core 2 Duo processors, running ISE on XP Pro. XP Pro is xp pro, it should run ISE fine ... Should even be possible to run it directly on OSX With a lot of effort ;) I can run Intel Mac executable on a linux PC by relinking so ... "All" you would need is a ELF loader (OSX uses the MachO executable format) and the XServer ofArticle: 110511
Okay guys this is where I'm at and this is what I'm going to do. I have several pins which are functionally SSTL output which are connected to a device which can do bidirectional JTAG and you get better test coverage if both ends of the net get a go at receiving. I'm going to add two pins which I can easily spare, one as an input tied low and one as a floating output. The input will be used to drive the OE of the above output pins. The output pin will be a simple AND of the above pins. This guarantees that the outputs become bidirectional with no logic getting minimsed out. The pins are now bidirectional and so I will need three new pins to be used as VREF pins for the SSTL levels. I can't easily afford these three pins, it forces me to have another bank at 2.5V instead of 3.3v which was the entire reason for ever asking the question (I expected a very quick yes or no). I've just re-read the whole thread and I appologise for side-tracking the issue talking about ouputs becoming IO during jtag (which I did not do straight away). Clearly the cpld needs to be routing vrefs to an IOB to work as an SSTL input. ColinArticle: 110512
Hi, Al schrieb: > Thomas Stanka wrote: > > Hi, > > It cost only time by doing effectly several runs and using the best > > result (you could even have the results from all runs saved on HD) > > I think, that timing critical layout gets a bigger problem if your > > utilisation is >>95% (YMMV I had only one A54SX72 design exceeding 95% > > sequential resources). > > > > To be more precise it only takes more than 90% of the sequential logic, > so that's why I'm not yet having any trouble, because I think that the > major problem will occur when you have a lot of combinational logic to > go through. Both *g*. Of course is the number of gates in a path important for the timing. But your longest path is very likely dominated by routing delay. You will typically have some bad routings exceeding the gate delay of 4-5 gates if your resource usage is high. Just open layout tool and timing analyiser in parallel to see the influence of layout on your timing. You will easily see some registers, that should be moved to improve timing, but high resource usage disables the possibility to put them close together without worsening other delays. > (By the way, what does YMMV mean???) Your mileage may vary (http://en.wikipedia.org/wiki/YMMV). bye ThomasArticle: 110513
hiiiiiii,
I am designing a switch controller to be implemented on
FPGA,i need to map memory blocks to FPGA,are there any libraries to do
this?Does the simulator automatically map the memory?if so give me an
example how to do this.
regards,
hema.
Article: 110514karrelsj <karrelsj@gmail.com> wrote: >Does anyone have any good links to groups/companies working on GSM or >CDMA IP cores? Or maybe something like a GSM SDR?... Thought I would >start here prior to my google search, after all it is a google group. This is NOT a google group. Google Inc. Just happens to archive posts, and provide an webinterface. Get yourself a proper nntp server + client and you will see the light. As for GSM/CDMA.. what is your objective?Article: 110515
Austin Lesea schrieb: > dd, > > Hardened PCIe (in V5). Not a core. Don't see any hardened PCIe on > Lattice website. Am I missing something? > > Not that the Lattice SC products are not nice, they are, and I have > acknowledged that a long time ago. But I don't see any hardened PCIe > core(s). Is this something they are keeping secret? > > Austin > MACO http://www.latticesemi.com/products/fpga/sc/macoonchipstructuredasicb.cfm 1GbE,10GbE,PCIe,SPI4.2 flexiPCS http://www.latticesemi.com/products/fpga/sc/serdesflexipcs.cfm http://www.latticesemi.com/documents/flexiMac-SC.pdf page 7 Lattice and Xilinx have a little different approuches. Lattice has not full PCIe endpoint in any of the FPGA's but Lattice was the first to have FPGA's with hard-macro support for PCIe, the level of functionality being implemented in hard block is different (smaller part is hardened) Xilinx full PCIe endpoint as hardblock is really qute. It solves the missing 5V PCI issue :) AnttiArticle: 110516
Hi everyone, I am new to the FPGA, and would like to know more about how we can program an FPGA to do a complex task. Please suggest the steps or any website relevant to this which aids in studying. Thanks to all in advanceArticle: 110517
Joseph Samson wrote: > Is anyone running ISE on an Intel based Macintosh? I'm considering a > MacPro with dual Core 2 Duo processors, running ISE on XP Pro. Ah colleague of mine is running ISE8.2i in Kubuntu Linux running in "Parallels" (on a Mac Book pro), works fine, including the drivers for the Platform USB Cable to program devices via JTAG. cu, SeanArticle: 110518
<leeaby@gmail.com> wrote in message news:1161080895.017982.164240@m73g2000cwd.googlegroups.com... > > Hi everyone, > > I am new to the FPGA, and would like to know more about how we can > program an FPGA to do a complex task. > > Please suggest the steps or any website relevant to this which aids in > studying. 1. If you haven't done so already, learn a design language (VHDL and Verilog come to mind). 2. If you haven't done so already, learn how to use a simulator for the above chosen language. 3. If you haven't done so already, learn how to use a synthesis tool which turns code written in the above chosen language into a file that you'll download into the FPGA. 4. Code up your 'complex task' in the above chosen language. 5a. Simulate the code to make sure that it is functioning how you want it to. 5b. Run the code through the synthesis tool every now and then just to make sure that the code you are writing and debugging is synthesizable. 6. Once simulation is nearly complete, run it through the synthesis tool to get timing numbers. If they are not acceptable go back to step 4 and rewrite it in such a way that the timing performance numbers have been met. 7. Keep going back to step 4 until the simulation says that you've implemented what you intended....only then can you continue on to #8. 8. Synthesize the code one last time to produce the bitstream to load into the FPGA. 9. Load the bitstream into the FPGA which is presumably on a board that has the necessary input and output connections to meet the needs of your 'complex task'. 10. If the end result doesn't work as intended, debug to find out why. Then beef up your simulation testbench to catch this type of problem. Verify in simulation that you can recreate the problem. Go back to step #4 and figure out what the fix is. KJArticle: 110519
Hi, i'm using Block Memory Generator 2.1 for a 16bit * 1024 RAM implemented in virtex4 BRAM and want to initialize the data with a *.coe file. But if i dump the data from the *.bit file with "data2mem -d" it doesn't match completely with the data from the *.ceo file. for example: * .ceo file: memory_initialization_radix=16; memory_initialization_vector= FFFF, FFFF, 0201, 0403, 0605, 0807, 1009, ... data2mem dump: 7F FF 7F FF 01 01 02 03 03 05 04 07 09 09 It seems that the Block Memory Generator does a wrong mapping of the 16 bit wide ram into the 16 + 2 wide (due to parity bits) BRAM or is this an error of data2mem? My *.bmm File looks like this: ADDRESS_SPACE bram1_space RAMB16 [0x00000000:0x000017FF] BUS_BLOCK ...BRAM[15:0] PLACED = X2Y12; END_BUS_BLOCK; END_ADDRESS_SPACE; If i use data2mem to insert BRAM initialization data from a *.mem file into the *.bit file, the data seems to be correct.Article: 110520
Hi, Can anyone point me out anything that I could read about using both PowerPCs on Virtex 2 Pro. Or using more than 1 micorblazes. Something that could give me some valueable starting information on this topic. Thanks, ErnestArticle: 110521
Ben schrieb: > Hi, > > i'm using Block Memory Generator 2.1 for a 16bit * 1024 RAM implemented in virtex4 BRAM and want to initialize the data with a *.coe file. But if i dump the data from the *.bit file with "data2mem -d" it doesn't match completely with the data from the *.ceo file. for example: > > * .ceo file: memory_initialization_radix=16; memory_initialization_vector= FFFF, FFFF, 0201, 0403, 0605, 0807, 1009, ... > > data2mem dump: > > 7F FF 7F FF 01 01 02 03 03 05 04 07 09 09 > > It seems that the Block Memory Generator does a wrong mapping of the 16 bit wide ram into the 16 + 2 wide (due to parity bits) BRAM or is this an error of data2mem? > > My *.bmm File looks like this: ADDRESS_SPACE bram1_space RAMB16 [0x00000000:0x000017FF] BUS_BLOCK ...BRAM[15:0] PLACED = X2Y12; END_BUS_BLOCK; END_ADDRESS_SPACE; > > If i use data2mem to insert BRAM initialization data from a *.mem file into the *.bit file, the data seems to be correct. try 1) specify RAMB18 in bmm file or 2) make sure the block ram is using 4 or more BRAMs, in that case the parity bits are not used Antti http://www.microfpga.comArticle: 110522
jacko wrote: > David Brown wrote: >> jacko wrote: >>> Henry Wong wrote: >>>> jacko wrote: >>>>> hi >>>>> >>>>> got the tester of model sim from altera, but it seem even though i set >>>>> the environment var from the system control panel, it don't appear >>>>> hence con not find file. this is both quartus II which has other >>>>> methods so no problem, and modelsim which does not find any environment >>>>> variable. >>>>> >>>>> don't work from command.exe either. >>>>> >>>>> any help would be appreciated. >>>>> >>>>> cheers >>>>> >>>> If this is on Windows, I believe the syntax is >>>> >>>> echo %LM_LICENSE_FILE% >>>> >>>> Also note that at least on my system, it's spelled "licenSe". >>>> >>>> Not sure if this helps. >>> got the echo working using % but still no luck finding it even with the >>> S. it's definatly there. >>> >> Use "set" from a command prompt to view all the environment variables in >> windows. >> >> Also note that if you change an environment variable in the control >> panel, it only affects programs started after the change. If you open a >> command prompt, then make the change, you will not see the effect in the >> opened prompt - you need to open a new prompt. > > done it though ctl panel, must have started model sim 3 times now and > it no find, and quartus II does noit either, does it need a reboot?? > It's windows - if in doubt, reboot and see if that helps.Article: 110523
Both
Aurash
John_H wrote:
>Built-in PCIe or built-in SERDES?
>
>
>"ddrinkard" <dale.drinkard@gmail.com> wrote in message
>news:1161035523.262190.222240@k70g2000cwa.googlegroups.com...
>
>
>>Hmmm, first in industry with built-in PCI-express? Lattice SCM devices
>>have built-in PCI express, have had since Feb (along with a boat-load
>>of other stuff too). 100mW per channel, finally catching up with
>>Altera and Lattice... S3A may have built-in Flash...seen that before
>>too. It's kinda fun watching Xilinx playing catch-up.... ;)
>>
>>
>
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 110524Aurelian Lazarut schrieb: > Both > Aurash > John_H wrote: > > >Built-in PCIe or built-in SERDES? > > Aurash, correct would be built in PCIe compliant SERDES AND PCIe endpoint if PCIe host or hub is required then it must be implemented 100% in FPGA fabric, eg full soft-core Antti
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