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Rickman, you can be sure that I will chase this all the way up and down the Xilinx management chain! Peter Alfke, from home rickman wrote: > Over the years I have gotten a lot of junk email from Xilinx to email > addresses that I have given out only to support and never to any > marketing channel. I have always been disappointed that Xilinx has > done this. But now they have sunk to a new low, they are giving or > selling my email address to third party junk emailers. > > I guess I should not be surprised at this since it is getting to be the > norm rather than the exception. Everyone seems to think it is > perfectly ok to post a non-"privacy" statement saying in typical > crypto-speak that they share your information with anyone that suits > them. I have found that if I contact a vendor directly and say I want > to opt out of their "privacy" policy and they should not share my info > with anyone at all, they will honor this. But why is this necessary? > Why can't a privacy policy be a PRIVACY policy and not a NON-privacy > policy? > > Am I alone in being irritated by these practices?Article: 109776
> "We are in the process of completely redesigning the Web Registration > system. Our existing system may be slow, but it is not that difficult > to use. Remember, 1.5 million visitors come to our site every quarter > and I haven't heard a complaint like this in years. Probably because the people who are too lazy to fill out the registration form are too lazy to complain as well ;-) It's good of you to take these comments on board. Cheers, JonArticle: 109777
"johnp" <johnp3+nospam@probo.com> wrote in message news:1159899381.342935.79240@b28g2000cwb.googlegroups.com... > I'm seeing some unexpected behavior when using the Xilinx TNM > constraint in a ucf file. I'm using the 8.2.03 version of the s/w. > > I have several groups of signals that cross clock domains. Normally, > I've used the following and it works OK: > TIMESPEC "ts_os_x3a" = FROM FFS(u_os_if/rd_burst) to > FFS(upo_joey_if/xmit_data<*>) = 12; > TIMESPEC "ts_os_x3b" = FROM FFS(u_fx2if/reg_brst_rd) to > FFS(upo_joey_if/xmit_data<*>) = 12; > > > I then tried: > NET "u_os_if/rd_burst" TNM = x_rio_tx; > NET "u_fx2if/reg_brst_rd" TNM = x_rio_tx; > TIMESPEC "ts_os_x3" = FROM x_rio_tx to > FFS(upo_joey_if/xmit_data<*>) = 12; > > and I was VERY surprised at the result. Instead of applying the > constraint > from the rd_burst and reg_brst_rd signals to the xmit_data<*> signals, > it > instead constrained a path from xmit_data<8> to xmit_data<15>. > > Is this yet another Xilinx bug or am I mis-using the TNM constraint? > > Thanks! > > John Providenza > John - Did you ever figure this out? RobArticle: 109778
Jon Beniston schrieb: > > "We are in the process of completely redesigning the Web Registration > > system. Our existing system may be slow, but it is not that difficult > > to use. Remember, 1.5 million visitors come to our site every quarter > > and I haven't heard a complaint like this in years. > > Probably because the people who are too lazy to fill out the > registration form are too lazy to complain as well ;-) > > It's good of you to take these comments on board. > > Cheers, > Jon its not about the lazyness, but the overall 'feadback ratio' not so many people comlain and send feadback on their own. my estimate is that you can only expect that out of 10,000 1 to 10 people commit feadback (bad or good) - so for every feadback receive on the some topic, multiply it by 1000 at least and you get a more likely number of potentially unsatisfied customers. I meant that the fact there is not enough negative feadback on something doesnt mean it is done well. proper feadback is hard to obtain - the way Xilinx website requests surveys to be filled isnt really fulfilling the goal I think. if I want to download some appnote for CPLDs but have to fill out the same form again and again - its just plain annoying for the customer. one option would be to have on DVD with all downloadables from xilinx website (or set of 12 DVD's) so you want be looking at web all the time and get the registrations awaiting you at every corner. I am not much complaing actually, I am used to annoying websites, but I can see that not all are as forgiving as I am AnttiArticle: 109779
Eli Bendersky wrote:
> What does this technique lack to be the perfect solution for resets in
> FPGA designs ?
This method is simple and works well.
Nothing is perfect, but this is an excellent default method.
The optimum design depends on how the external
reset pulse is generated.
For an fpga, I don't want to do the reset procedure
until the logic image is downloaded and the device
is active. If a cpu is handling the download AND
if the cpu and fpga use the same clock, a cpu
port could deliver a synchronized reset pulse
to the fpga with no other logic required.
Thanks for your well-researched posting.
-- Mike Treseler
Article: 109780to my surprise I just heard comments about Xilinx giving up hard processor cores - well I think its not so, and that V5-FX has PPC440 cores in it, but isnt it about time that there would be some information update when V5FX is actually coming? Is it still planned for 2007Q1 or is the schedule changed? As much as I understand the PPC in V5 will have full linux support and also realtime linux support (from lynuxworks) - ok, sometimes it pays off to wait :) AnttiArticle: 109781
Robert wrote:
>> I am using Xilinx ISE software for an FPGA project.
>> Every time I do a small change in the HDL code I have to regenerate the
>> bitstream file and the ISE software takes a long time to do the job.
>> Is there a way to accelerate it?
Brannon wrote:
> Yeah. It's called L1/2/3 cache. It costs several hundred dollars for a
> fair amount of it. If you can cut your compile times from 20min to
> 15min by purchasing a $1000 CPU, how long would it take the company to
> pay for that with the made-up time?
I would prefer to spend the money on
a fast HDL simulator to check those
small changes without having to generate
a bitstream file.
-- Mike Treseler
Article: 109782It is up to marketing to orchestrate product announcements and press releases, and I will not steal their thunder. As usual, Antti is pretty well informed... Peter Alfke Antti wrote: > to my surprise I just heard comments about Xilinx giving up hard > processor cores - well I think its not so, and that V5-FX has PPC440 > cores in it, but isnt it about time that there would be some > information update when V5FX is actually coming? > > Is it still planned for 2007Q1 or is the schedule changed? > > As much as I understand the PPC in V5 will have full linux support and > also realtime linux support (from lynuxworks) - ok, sometimes it pays > off to wait :) > > AnttiArticle: 109783
Steven, here is another version: If yor Spartan device has the CLKFX option, then you just use one DCM to multiply by 16 and simultaneously divide by 25, which gives you a 48 MHz output. You can then use a simple 2-bit synchronous counter to divide by 3, and that gives you the 16 MHz accurately. Peter Alfke, Xilinx Applications (from home) Peter Alfke wrote: > Steven, if yor Spartan device has the CLKFX option, then you just use > one DCM to multiply by 16 and simultaneously divide by 15, which gives > you an 80 MHz output. You can then use a simple 3-bit synchronous > counter to divide by 5, and that gives you the 16 MHz accurately. > Peter Alfke, Xilinx Applications (from home) > ================ > moogyd@yahoo.co.uk wrote: > > Hi, > > > > We have an eval board with a spartan FPGA and a 75MHz XTAL > > Within ourt design, we require an accurate 16MHz clock. > > It is not possible to generate this frequency using a single DCM, is it > > possible to chain 2 DCM's together to generate the 16MHz clock ? > > > > (the obvious solution is to change the XTAL, but I'd like to know > > whether it is possible without changing the XTAL :-) ) > > > > Thanks for any feedback, > > > > StevenArticle: 109784
maxascent wrote:
> I am using synplify to synth a design with some xilinx core gen devices. I
> get warnings on some of the core gen edif files stating that there is an
> interface mismatch between the verilog and the edif. I can only assume
> that it is something that core gen is not doing correctly.
Synplify can handle these details for you if
code your buffer from their synthesis templates
instead of using coregen netlists directly.
-- Mike Treseler
Article: 109785
Suppose I have a state machine which is like following ( I have not
added other states)
if rising_edge(clk)
case state is
WHEN a =>
en <='1';
state <= b;
WHEN b =>
en <= '0';
state <= c;
WHEN c =>
A <= Qout;
B <= Bout;
state <= d;
WHEN d =>
if done ='1' THEN
if enable ='1' THEN
state <= a;
else
state <= d;
end if;
else
state <= e;
end if;
when e =>
Aout <= (OTHERS =>'0');
Bout <= (OTHERS =>'0');
state <= f;
.
.
.
.
add : Adder ( A=> Aout, B=> Bout , Q => Qout , ena => enable, clk
=>clk);
In the above state machine the input "enable" changes at a rate >=
10th of the clk( at least 10 or more cylces) . Now should I specify
it in the constraint file . Since logically if the enable changes at
the same rate as clk then the state machine may be erroneousif the
adder takes at least 5 clk cycles to get the result ready.
Can this cause timing errors in the ise?
Thanks,
D
in the state machine
KJ wrote:
> dhruvakshad@gmail.com wrote:
> > Hello KJ,
> > I have added exactly one flip flop in between the asycnhronous inputs
> > and the state machines since the asynchronous input is coming at a much
> > lower rate. is it ok?
> >
> > Thanks,
> > D
>
> I said two flip flops.
>
> "What
> you need to do there is first synchronize the signal with two flip
> flops and
> feed the output of the second flip flop to the rest of your design.
> The
> output of the first flip flop goes nowhere except for the input of the
> second flip flop"
>
> The 'lower rate' is irrelevant, if it's asynchronous you have no idea
> when it will come in relative to the clock that is sampling it.
>
> KJ
Article: 109786
rickman wrote:
> Over the years I have gotten a lot of junk email from Xilinx to email
> addresses that I have given out only to support and never to any
> marketing channel.
Get thunderbird (it's free)
and turn on the junk mail controls (they work well)
Most vendors set email defaults=ON in the fine print
whenever I fill out a registration form.
I no longer even bother trying to shut these things off.
I just click the Junk button on Thunderbird when
I get the first email. From then on, it all goes directly
to a junk folder for 14 days and then is converted
to wood chips.
-- Mike Treseler
note to vendors:
When I need something from you, I check your
web site, not my old emails. Drop the
email spew, and use the money to get new
information to your websites quickly,
where I can find it easily, and without filling
out more forms.
Article: 109787Hello KJ, Thanks for the reply. I will try that. D KJ wrote: > dhruvakshad@gmail.com wrote: > > Hello KJ, > > I have added exactly one flip flop in between the asycnhronous inputs > > and the state machines since the asynchronous input is coming at a much > > lower rate. is it ok? > > > > Thanks, > > D > > I said two flip flops. > > "What > you need to do there is first synchronize the signal with two flip > flops and > feed the output of the second flip flop to the rest of your design. > The > output of the first flip flop goes nowhere except for the input of the > second flip flop" > > The 'lower rate' is irrelevant, if it's asynchronous you have no idea > when it will come in relative to the clock that is sampling it. > > KJArticle: 109788
Hi Andrea,
I'm glad this seems to be helping.
>> What happens if your application is bigger than the BRAM resources
>> available
>> in the FPGA?
> Yeah! This is my nightmare!
In that case, you are lucky. I have had much worse nightmares than that! :-)
> Given that I have filled such non-volatile memory with the application
> (how to do that will be another question!) how should I tell to the
> FPGA that the program is in such memory? In this case the linker script
> has a role?
Yes. When the Microblaze processor core is released from its reset state, it
will jump to some pre-defined location in its memory space and start
fetching and executing instructions from there. All (all!) that is
necessary, therefore, is to attach this external memory to the FPGA in such
a way that the processor can address it. Then, you can run some code. If the
memory is of a standard type (as most off-the-shelf components will be) then
there is a good chance that the EDK will already have an appropriate memory
controller core that will handle the interfacing for you.
The linker script coordinates where the various sections of the program
(main code, data, read-only data, boot code, etc) should be placed when the
program is downloaded. It is usually auto-generated by EDK, although you
might end up having to edit part of it yourself. Let's hope not!
There are various ways of arranging to run the code from the external
memory, from the very simple to the very complex. You can map the NVRAM
directly to this "reset vector" location, or you can have the reset vector
point to some internal memory where the first instruction is simply a branch
to the start of the instructions in external memory - or you can have some
boot code to copy the whole program from NV RAM into volatile storage. Which
one you choose depends a lot on your performance requirements, and how much
volatile RAM you have in your system.
> One of the goals of my research is to demonstrate that the
> self-coordinating technique we propose, and that form a mathematical
> point of view are correct, can be implemented with a relative low cost.
> So it's very important for me to choose the right components for my
> control board.
Sounds interesting (although the paper is very mathematical and I must
confess that control systems was never my strong point!).
It sounds to me like you should perhaps look at the Spartan-3 FPGA series.
They are much lower cost than the Virtex-series parts, but are still capable
of implementing a MicroBlaze system with custom peripherals.
Once again, good luck with your project!
-Ben-
Article: 109789Frank van Eijkelenburg wrote: > Hi, > > I am new to the Nios II core. I have built a simple system with a timer > which is set as periodically timer. I have registered an interrupt > service routine: > > alt_irq_disable(TIMER_0_IRQ); > res = alt_irq_register(TIMER_0_IRQ, NULL, timer_isr); > > With this code I still come in my installed ISR. So registering is also > enable the interrupt. Is that correct, is there a way to register an ISR > and leave the interrupt disabled (until you decide to enable it manually)? Normally, you'll use the generated alt_sys_init() to set up the timers in alt_main(). This wants to happen after the call to alt_irq_init(ALT_IRQ_BASE). Take a look at the macros in alt_sys_init() to see the underlying process. > > Another question: where can I find a list with available routines for > the peripheral. For instance, I saw in an example the call > IOWR_ALTERA_AVALON_PIO_DATA to write to my io-pins. But where can I find > a complete list. It not in the software developer's handbook. Take a look in the components directory. For example, for pios, take a look at components/altera_avalon_pio/inc/altera_avalon_pio_regs.h. MarkArticle: 109790
http://www.xilinx.com/support/prealounge/protected/archive.htm Regards, Jens THANG NGUYEN schrieb: > Hi, > > "but i would suggest to use the ones from the xilinx website for PREAT8 flow. The Early Access Partial Reconfiguration Suite contains basic busmacros, examples, and much more. It may also be possible, if you, for whatever reason, not be able to use ISE8.1, to use the old patch for partial reconfiguration, based on ISE6.3. " > > Could you tell me where I can find it? I try to search but I did not find the patch for ISE 6.3i. Thank you so much. Thang NguyenArticle: 109791
Siva Velusamy wrote: > In the majority of cases, the issue is improper formatting of the CF. So > did you try again after reformatting? (Use Linux or mkdosfs to format). Yes indeed. After a mkdosfs -F16 under Linux and a fresh copy of the reference CF, the demos worked again. Unfortunately, the original problem remains: I can't seem to create .ace files myself, ie. I followed what seemed to be straight forward steps to transform my design to an .ace file, but after copying it to the CF card, overwriting one of the demos, the .ace file doesn't load (instead lights up the Err LED). Thanks, TommyArticle: 109792
hi 283 LEs 6% Cyclone II EP2C5T144C6 44 Warnings Still unverified. yes got it to compile at last after discovering a bit more about buses and naming of them. TEST16 toplevel object schematic encapsulates the indi16 with reset logic and tristate databus, to connect with external pins on the chip. Hopefully not a lot more editing needs to be done for the basic design, and i am now in a position to start puting together more architecture documentation. cheers p.s. the cpu is suitable for having a C compilier written for it and will not be limited to forth. http://indi.joox.net http://indi.microfpga.com http://indi.hpsdr.com all three url work but some do not have directory listing yet.Article: 109793
Tommy Thorn wrote: > Siva Velusamy wrote: > >>In the majority of cases, the issue is improper formatting of the CF. So >>did you try again after reformatting? (Use Linux or mkdosfs to format). > > > Yes indeed. After a mkdosfs -F16 under Linux and a fresh copy of the > reference CF, the demos worked again. Unfortunately, the original > problem remains: I can't seem to create .ace files myself, ie. I > followed what seemed to be straight forward steps to transform my > design to an .ace file, but after copying it to the CF card, > overwriting one of the demos, the .ace file doesn't load (instead > lights up the Err LED). > You might want to try using genace.tcl available in EDK. Use a clean CF card, generate the ACE file using genace and copy it to the CF. /SivaArticle: 109794
I was playing with this old design the other day and decided to "clean it up" a little bit (it was kinda messy). I moved some logic to their own modules for better readability. I also grouped some signals into VHDL records (don't know what its called, but if you ever browsed the LEON code, you know what i mean). I didn't change the functionality of the design (I did ran a large number of tests to be sure, of course). Furthermore, the changes were very isolated (only two files affected in a relatively large design) I was kind of surprised to see that after synthesis and PAR, I got a design that was: 1. 10% slower 2. marginally larger (few hundred LUTs) (yes, with same tool, same speed grade and so on) Has anyone seen this kind of behaviour before? Would this go away if I somehow "flattened" my design? brunsArticle: 109795
Antti wrote: > my estimate is that you can only expect that out of 10,000 > 1 to 10 people commit feadback (bad or good) - so for every > feadback receive on the some topic, multiply it by 1000 > at least and you get a more likely number of potentially > unsatisfied customers. Or you could do it like Mentor. Everything that is only remotely interesting you can only access after logging in. And once you've logged in, you get an email the next day asking you to participate in an online survey to improve "the only 5 star support in the industry". And if you don't react, you get another email the next day... Force people to feed back! :) cu, SeanArticle: 109796
burn.sir@gmail.com wrote: > Would this go away if I somehow "flattened" my design? I would back out the changes one at a time to find the culprit. Maybe adding the entities created a pipeline stage somehow. Also check the rtl viewer. -- Mike TreselerArticle: 109797
Robert Have a look at our TechiTip on incremntal synthesis here http://www.enterpoint.co.uk/techitips/techitips.html. It is a bit old now but the general techniques still are valid. John Adair Enterpoint Ltd. Robert Llu=EDs wrote: > Hi, > > I am using Xilinx ISE software for an FPGA project. > Every time I do a small change in the HDL code I have to regenerate the > bitstream file and the ISE software takes a long time to do the job. > Is there a way to accelerate it? > Is there a way to avoid synthesizing parts of the design that are > untouched since the last synthesis? What about the rest of tue > processes? > Is it faster to use a batch file instead of using the software GUI? >=20 > Thanks, > RobertArticle: 109798
burn.sir@gmail.com wrote: > >I was playing with this old design the other day and decided to >"clean it up" a little bit (it was kinda messy). I moved some >logic to their own modules for better readability. I also grouped >some signals into VHDL records (don't know what its called, but >if you ever browsed the LEON code, you know what i mean). > > >I didn't change the functionality of the design (I did ran a >large number of tests to be sure, of course). Furthermore, the changes >were very isolated (only two files affected in a relatively large >design) > >I was kind of surprised to see that after synthesis and PAR, >I got a design that was: > >1. 10% slower >2. marginally larger (few hundred LUTs) > >(yes, with same tool, same speed grade and so on) > > >Has anyone seen this kind of behaviour before? >Would this go away if I somehow "flattened" my design? Xilinx allows to flatten the design and optimize across module boundaries. From my experience, this does speed things up. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 109799
I am looking for ideas on how to implement SMPTE310 Tx and Rx interface. Algorithm/VHDL/Verilog examples would be helpful. Thanks.
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