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Dear Jens, I can't use the patch for 8.1i because I don't have the ISE 8.1i. I have only the ISE version 6.3i or ISE 8.2i. Do I misunderstand something? I read in the PREAT_install.doc, and it told me that the PartialFlow_v8.zip file has to be installed on the top of ISE 6.3.03i. But when I install it, the program told me that this only use for ISE 8.1i version. Is there another version of PartialFlow which use with ISE 6.3i??? I see in the link you just gave me there is only the PartialFlow_v8.zip. Can it install on ISE 6.3i? Thank Jens Thang NguyenArticle: 109876
I've implemented the whole Digilent USB protocol and already working in cblsrv-0.2 (with Impact). When I have some time, I will upload the latest version to sourceforge.net. Zoltan goss wrote: > Hi everybody, > > I'm going to build a USB JTAG cable and I don't know what protocol > should I use for communication. The only cable I can fully implement > this time is the Digilent USB cable... (according to the code of Zoltan > Csizmadia's cable server project) > I was trying to reverse engineer Xilinx's USB Platform cable protocol, > but after a point I gave up. (Mostly becouse the firmware of the cable > is shipped with the PC software, so they can easily modify the protocol > in the new version of ISE) > > So, some questions: > Is Digilent's protocol free to implement in my device? > > Is there any cable with open protocol? (with a GPL like license) > If exists an open protocol cable, is this well supported by > applications? > > Thanks, > gossArticle: 109877
Sorry, I misunderstood the question :) If you want to use it from cblsrv (using Impact), I 'd make the protocol very similar to the cblsrv protocol. One of the problem with Digilent protocol is it is not very efficient when you are doing a lot of short Shift-IR, Shift-DR operations. That is why reading or writing a platform flash is much slower with Digilent-USB than with Parallell III cable. Of course you should implement the very raw access to JTAG pins as well, but for performance reasons I 'd create some higher level command. (eg. cblsrv WRITE) ZoltanArticle: 109878
jacko wrote: > jacko wrote: > > hi > > > > MAX II EPM570T100C5 just fits at 68% utilization. > > altera quotes $13.30 per chip. If i can get io in there, and possibly > > change the way interrupts are done then bingo. 512 x 16 bit eeprom > > onboard and an external ram and rom. > > Changed design to only mirror P reg on super/user interrupt toggle pin, > and got down to 303 LEs in the MAX II EPM570T100C5. This gives more > free space for IO and control. Got it down to 222 LEs on the MAX II, not sure how to export to lattice devices from the altera tool, and how available is the lattice tool? Is it free??? > > > > TEST16 toplevel object schematic encapsulates the indi16 with reset > > > > logic and tristate databus, to connect with external pins on the chip. > > > > > > > > Hopefully not a lot more editing needs to be done for the basic design, > > > > and i am now in a position to start puting together more architecture > > > > documentation. > > > > > > > > cheers > > > > > > > > p.s. the cpu is suitable for having a C compilier written for it and > > > > will not be limited to forth. > > > > > > > > http://indi.joox.net > > > > http://indi.microfpga.com > > > > http://indi.hpsdr.com > > > > > > > > all three url work but some do not have directory listing yet.Article: 109879
jacko schrieb: > jacko wrote: > > jacko wrote: > > > hi > > > > > > MAX II EPM570T100C5 just fits at 68% utilization. > > > altera quotes $13.30 per chip. If i can get io in there, and possibly > > > change the way interrupts are done then bingo. 512 x 16 bit eeprom > > > onboard and an external ram and rom. > > > > Changed design to only mirror P reg on super/user interrupt toggle pin, > > and got down to 303 LEs in the MAX II EPM570T100C5. This gives more > > free space for IO and control. > > Got it down to 222 LEs on the MAX II, not sure how to export to lattice > devices from the altera tool, and how available is the lattice tool? > Is it free??? > sure its free! (for selected devices) www.latticesemi.com if you wrote in VHDL or verilog then should be no problem just create a project with ispLEVER PN and add hdl sources! AnttiArticle: 109880
KJ wrote:
> That's why it can be good to keep secrets from the boss at times ;)
Then there's the the Homer Simpson method:
"Great idea boss, let me write that in my notebook."
It is really up to the designer to get it right
whatever the obstacles may be.
-- Mike Treseler
Article: 109881
Robert wrote:
> Ah, I understand! And very little information to find on the subject
> indeed. Looks like the FPGA vendors really are not interested in
> supporting inter-vendor portability...
True, but the hdl synthesis manuals
for ISE, Quartus, etc. do show the basic
code templates, and most of these are portable.
-- Mike Treseler
Article: 109882Any idea about implementation of indi16 for xilinx spartan series? jacko wrote: > hi > > 283 LEs > 6% Cyclone II EP2C5T144C6 > 44 Warnings > Still unverified. > > yes got it to compile at last after discovering a bit more about buses > and naming of them. > > TEST16 toplevel object schematic encapsulates the indi16 with reset > logic and tristate databus, to connect with external pins on the chip. > > Hopefully not a lot more editing needs to be done for the basic design, > and i am now in a position to start puting together more architecture > documentation. > > cheers > > p.s. the cpu is suitable for having a C compilier written for it and > will not be limited to forth. > > http://indi.joox.net > http://indi.microfpga.com > http://indi.hpsdr.com > > all three url work but some do not have directory listing yet.Article: 109883
Dolphin schrieb: > Hello John, > > I can do recalibration in the video blanking time (this for a video > application). The step size doesn't have to be 1 ns and not all steps > need to have the same latency. However if I program it to 3.5ns it > should stay between 3 and 4 ns for the whole temperature range, a drift > of 0.5ns is acceptable. Calibration can be done during this sweep > through the temperature range. The temperature gradient won't be high > so you can assume that there are enough calibration cycles . Do you need to delay a clock or a data signal? In case of a clock, how about using a varicap to tune a RC filter do delay a clock and use a PLL to generate the delayed clock? Regards FalkArticle: 109884
avionion@gmail.com wrote: > Any idea about implementation of indi16 for xilinx spartan series? i am quite new to the altera tool, and have not used the xilinix one or the lattice one, i am using schematic entry, and am not sure how to export a netlist. vhdl will not be used fro the forseable future. i use the lpm funcs quite a bit in the design, and expect to get 6 MIPS at 60MHz in max II. Does anyone know how to make the quartus II give out a netlist which can be input into another design tool? or is there a netlist to vhdl converter in the public domain? what are the best size minimization options to place on quartus? to get good optimization? i am not doing other peoples homework, as i am not rich by any means, i would consider doing vhdl piad, but who pays? > jacko wrote: > > hi > > > > 283 LEs > > 6% Cyclone II EP2C5T144C6 > > 44 Warnings > > Still unverified. > > > > yes got it to compile at last after discovering a bit more about buses > > and naming of them. > > > > TEST16 toplevel object schematic encapsulates the indi16 with reset > > logic and tristate databus, to connect with external pins on the chip. > > > > Hopefully not a lot more editing needs to be done for the basic design, > > and i am now in a position to start puting together more architecture > > documentation. > > > > cheers > > > > p.s. the cpu is suitable for having a C compilier written for it and > > will not be limited to forth. > > > > http://indi.joox.net > > http://indi.microfpga.com > > http://indi.hpsdr.com > > > > all three url work but some do not have directory listing yet.Article: 109885
Dear Thang, hope i can clean this confusion: -the patch version you found on the xilinx website is for ISE 8.1.01 -the patch version in the link i gave to you is for ISE 6.3.03! Really! You can just install them on top of 6.3.03 as described in PREAT_install.doc in the link. Both versions are called PartialFlow_v8.zip because both are subversion 8 of the patch, e.g. there are also PartialFlow_v7.zip for both, ISE 6.3.03 and ISE 8.1.01. Just compare the PartialFlow_v8.zip from the link and the xilinx website, and you will see the difference. I personally used the 6.3.03 patch before the 8.1.01 was available, it is working! When install the patch, and you have multiple versions of ISE installed, make sure that the $XILINX enviroment variable point to the right installation. I asked about ISE 8.1.01 because i personally would prefer to use the newest version of the patch available, because of fixed bugs and other improvements, and i assumed that you have access to it, just because you have access to ISE 8.2. I apologize for any confusion i may have caused. Regards, Jens THANG NGUYEN schrieb: > Dear Jens, > > I can't use the patch for 8.1i because I don't have the ISE 8.1i. I have only the ISE version 6.3i or ISE 8.2i. Do I misunderstand something? I read in the PREAT_install.doc, and it told me that the PartialFlow_v8.zip file has to be installed on the top of ISE 6.3.03i. But when I install it, the program told me that this only use for ISE 8.1i version. Is there another version of PartialFlow which use with ISE 6.3i??? I see in the link you just gave me there is only the PartialFlow_v8.zip. Can it install on ISE 6.3i? > > Thank Jens Thang NguyenArticle: 109886
On Thu, 21 Sep 2006, Bob wrote: > I am new to FPGA and I can't find any info on this subject anywhere. Can the > USB on the Spartan-3E be used for I/O at run-time ... or is it just for > downloading configs? On Sat, 6 May 2006, BoroToro wrote: > I just received my Spartan 3e starter kit and had to share my > frustration ... > > The huge DRAM and the fast FPGA seem to make this board ideal for video > and sound processing. I read with interest the 2 messages above, as they raise an issue I've been thinking about recently. I'm considering buying a Spartan 3E Starter Kit, simply because it seems to offer a good balance between FPGA size, DRAM size, other peripherals and bundled development software, and crucially, cost. However, I am interested in testing basic video processing applications, and I'm concerned that the one thing this board doesn't have is any kind of facility for (relatively) high-bandwidth data I/O ? The USB port would've been ideal, as I'd like to be able to use an effective bandwidth of about 40 Mbit/s, but it seems from this thread that it would take a fair amount of hacking to convert the USB port from its nominal JTAG role into something that would offer only minimal bandwidth ? The only other alternative I see is the Ethernet port, but that would presumably require at least an Ethernet IP core programmed onto the FPGA. I am aware that such things can be had from a number of sources, but I have little idea of the ease-of-use or effectiveness of this solution. So in summary, I'm just interested in any comments on the above, or in any other suggestions for getting decent I/O bandwidth out of this board. To clarify, I should add that I'm most interested in communications between this board and a 'host' PC, rather than any other hardware. Thanks, Andy M.Article: 109887
RadioShox wrote: > But now for Altera. I cannot find a instantiatable primitive called M4K > in the documentation. I really have to use the MegaWizard, which is > fine, but not for this design. Using the wizard would mean that I have > to do it over and over again for each new Altera design, and go through > simulation and verification every time. So there goes the idea of > switching between brands using an generic map. There's a basic Altera-specific primitive called the ALTSYNCRAM. It's a generic synchronous RAM component that you can not only parametrize for width and depth, but also to only include M4Ks, what the maximum block depth is when generating a RAM block that is larger than an M4K etcetera. It's pretty well-documented in the Quartus online help. Best regards, BenArticle: 109888
On 5 Oct 2006 22:56:10 +0200, "Symon" <symon_brewer@hotmail.com> wrote: >Hi Brannon, >So, I guess we'd all like the tools to run faster, and you make some good >suggestions. >However, I wonder how often you _need_ to do a PAR cycle? Please excuse me >if I'm teaching you to suck eggs, but I just want to check you've considered >a development process where you simulate things before PAR. This way, your >logic errors are found in the simulator, not the real hardware. If you like >to try stuff out as you go, maybe you could run the PAR each evening before >heading out to the pub, that's what I sometimes do. :-) Excellent suggestion, but I find I usually need a drink *after* the PAR run. Bob Perlman Cambrian Design Works http://www.cambriandesign.comArticle: 109889
Two directions might get you close to where you want to be: In your Cyclone II, check what your LUT delay is and what your adjacent LAB routing delay is. You could put together a delay line sources on the left, travels through LEs/LUTs/LABs to the right, and returns through LEs that select between the rightward going path and the adjacent leftward going path. The coarseness is probably too much for your needs. Another approach could use the carry chain but the carries as implemented in the LABs might not have the regularity for a good, variable delay. One signal feeding the LAB could be "picked up" at various point along the carry chain for finer adjustments than the previous approach. You can work with combinations of features in your FPGA that give you consistent delays you can use. It depends on what you can get from your silicon as to how fine your resolution is. The actual delay can be measured by configuring the delay line as a ring oscillator with the injection point into your fixed-output delay line varied as you would vary the live signal. Measuring the ring oscillator frequency compared to your reference will give you the calibration points. The process variation could give you a 4:1 change in your delay line performance as PVT changes meaning the method would typically need to significantly overbuild "typical" to handle the fastest cases yet maintain the resolution for the slowest. With this added information on how it could be put together, do you still want to pursue this delay line? I have great results sampling and deskewing multiple low-quality 600 Mb/s data channels in a Spartan3E with similar techniques but this front end of mine is overbuilt and doesn't deliver "delay" as you appear to want it. If you do experiment along the FPGA silicon delay lines, try to keep your signal inverting as it goes through the chain to avoid "duty cycle compression" where the ones and zeros get lopsided in their size. Ring oscillators use multiple inverters in stages for a reason. - John_H "Dolphin" <Karel.Deprez@gemidis.be> wrote in message news:1160146231.100489.312710@m73g2000cwd.googlegroups.com... > Hello John, > > I can do recalibration in the video blanking time (this for a video > application). The step size doesn't have to be 1 ns and not all steps > need to have the same latency. However if I program it to 3.5ns it > should stay between 3 and 4 ns for the whole temperature range, a drift > of 0.5ns is acceptable. Calibration can be done during this sweep > through the temperature range. The temperature gradient won't be high > so you can assume that there are enough calibration cycles . > > best regards, > DolphinArticle: 109890
PeteS wrote: > The crashes are, no doubt, because of the increasing complexity of each > part of the process required to be evaluated by the tools. The *nix way > was always 'do one thing and do it well' which used to exemplify the > Xilinx tools. As they have got more complex, they have added things to > each tool, such that they are now doing more than one thing. Adding such > complexity adds exponential sources of problems. > > I suggest each tool be completely re-evaluated - and if it's doing more > than one thing, separate those things back out - to 'Do one thing and do > it well'. When a vendor doesn't have time to do it right, there is always the shared Open Source development model where BOTH the vendor and the customers work to make the tools right, with a shared interest and investment.Article: 109891
I'd like to turn the question around. Does Xilinx have something like ALTSYNCRAM? That is one module that is completely parameterizable, rather that a plethora of fixed dimension modules. Like the original post, I want to do it without coregen so that I can write parameterized code. Also, inferring doesn't seem to work because of mixed read and write widths, meaning in some cases the the end result will be a mix of RAM and luts.Article: 109892
If your were talking 2 ns I would suggest using the DDR structure of an I/O cell and opposite phases of clocks to use a 250MHz clock if this is to the outside world. If you were using a more expensive part like a Virtex-4 you could probably go to 1 nS resolution. Spartan-3/3E might but it is beyond the spec. Otherwise, and possible slightly horrible, is to have 4 phases of 250 MHz clock, driving 4 flops, which are put through a LUT acting as a OR. Your logic would have to figure out inputs to the flops to drive the appropriate one against necessary delay. This scheme would give some variance timing due voltage, batch etc. in the backend LUT and routing. It would need to be hand placed within the FPGA using something like FPGA Editor to get closely balanced paths otherwise you are very likely to get non linear steps in your delay. John Adair Enterpoint Ltd. Dolphin wrote: > Hello, > > For a future project I need to design a programmable delay line. The > specifications are: steps of +/- 1 ns, range of 0 to 8 ns. I have no > PLLs left so I can't use a high-speed pipeline to design this. Note > that the delay should be fixed when temperature varies, this means that > I'll probably need some calibration. > I think that Xilinx uses something like this to delay the DQS signal in > the S3E DDR controller. > Has anybody got an idea how I should implement this? > > best regards, > DolphinArticle: 109893
I can't help dez.ambr...@gmail.com with the Xilinx question, but I thought I would chime in with some more Altera information and point you to documentation... Previous posters are correct about manually modifying the Megafunction. I've seen designers do this when they have a lot of differently-sized memory blocks and they don't want to use the MegaWizard every time. There is some information about manually modifying a MegaWizard-generated file for memory in the Designing with Low_Level Primtives user guide: http://www.altera.com/literature/ug/ug_low_level.pdf. See page 1-9 in the document or page 15 of the PDF (in document version 2.0). You can refer to Quartus II Help for more information about some of the parameters. I would also agree with the folks that suggested inferring. That way your code is vendor-independent generic HDL! Although it is worth pointing out that the Altera and Xilinx memory architectures may be slightly different and by targeting the architecture (using registers where the device architecture is registered etc) you can often get better results and eliminate the need to create any logic outside the RAM to implement the exact functionality described in your HDL code. For examples of inferring RAM, refer to the Recommended HDL Coding Styles chapter of the Quartus II handbook at http://www.altera.com/literature/hb/qts/qts_qii51007.pdf. RAM information starts on page 12 (in the 6.0.0 version of the document). When you infer a RAM, the software will place it in the appropriate memory block for its size etc. If you want to drive an inferred RAM into a specific size of device memory (like an M4K specifically), Quartus II integrated synthesis provides the ramstyle synthesis attribute to specify the RAM type. Refer to Quartus II Integrated Synthesis chapter at http://www.altera.com/literature/hb/qts/qts_qii51008.pdf, page 42 (in the 6.0.0 version of the document). Jennifer Stephenson AlteraArticle: 109894
Xilinx has started an investigation. Please help us when we ask for evidence. What you guys described is a totally unacceptable situation, and one we will not tolerate. Peter ================ rickman wrote: > Thanks Peter. Of all the things a vendor can do to tick me off, spam > is pretty high on the list. I would really appreciate any help in > getting Xilinx to stop this. > > I once received similar junk email to an address I had given only to > Altera. When I contacted them they had no idea how it was given out, > or at least that is what they told me. So Xilinx is not alone. > > >Article: 109895
"Amontec, Larry" <laurent.gauch@ANTI-SPAMamontec.com> writes: > Checkout JTAGkey and JTAGkey-Tiny from http://www.amontec.com . Looks very nice! And the pricing on JTAGkey-Tiny is certainly very attractive. Aside from lower price and not having a molded plastic case, are there any other differences between JTAGkey and JTAGkey-Tiny? Thanks, EricArticle: 109896
Peter Alfke wrote: > Xilinx has started an investigation. Please help us when we ask for > evidence. > What you guys described is a totally unacceptable situation, and one we > will not tolerate. > Peter > ================ > rickman wrote: > > Thanks Peter. Of all the things a vendor can do to tick me off, spam > > is pretty high on the list. I would really appreciate any help in > > getting Xilinx to stop this. > > > > I once received similar junk email to an address I had given only to > > Altera. When I contacted them they had no idea how it was given out, > > or at least that is what they told me. So Xilinx is not alone. > > for me to use xilinx the following would have to be rectified, 1. the ISE download page has to work, or a binary via email option. 2. send at most 1 e-mail per month, with all bulitins in it. this leads to a more focused read rather than snippits. which i treat as unwanted hype. 6 emails telling me welcome and no binary is just piss poor. cheers.Article: 109897
jacko wrote: > avionion@gmail.com wrote: > > Any idea about implementation of indi16 for xilinx spartan series? > > i am quite new to the altera tool, and have not used the xilinix one or > the lattice one, i am using schematic entry, and am not sure how to > export a netlist. vhdl will not be used fro the forseable future. i use > the lpm funcs quite a bit in the design, and expect to get 6 MIPS at > 60MHz in max II. Does anyone know how to make the quartus II give out a > netlist which can be input into another design tool? or is there a > netlist to vhdl converter in the public domain? > > what are the best size minimization options to place on quartus? to get > good optimization? > > i am not doing other peoples homework, as i am not rich by any means, i > would consider doing vhdl piad, but who pays? > Hi using FPGA vendor sch tools is ok in some cases, but it should not be used for developing IP cores - sch to hdl or edif conversion to not offer quality portable hdl from schematic entry. so unfortunatly you may end up doing manual conversion or most likely it means you just have to rewrite it hdl from scratch. if you think that your processor has some use at all then you should take that effort and do the conversion to VHDL (or verilog) AnttiArticle: 109898
Antti wrote: > jacko wrote: > > avionion@gmail.com wrote: > > > Any idea about implementation of indi16 for xilinx spartan series? > > > > i am quite new to the altera tool, and have not used the xilinix one or > > the lattice one, i am using schematic entry, and am not sure how to > > export a netlist. vhdl will not be used fro the forseable future. i use > > the lpm funcs quite a bit in the design, and expect to get 6 MIPS at > > 60MHz in max II. Does anyone know how to make the quartus II give out a > > netlist which can be input into another design tool? or is there a > > netlist to vhdl converter in the public domain? > > > > what are the best size minimization options to place on quartus? to get > > good optimization? > > > > i am not doing other peoples homework, as i am not rich by any means, i > > would consider doing vhdl piad, but who pays? > > > > Hi > > using FPGA vendor sch tools is ok in some cases, but it > should not be used for developing IP cores - sch to hdl or edif > conversion to not offer quality portable hdl from schematic entry. > > so unfortunatly you may end up doing manual conversion or > most likely it means you just have to rewrite it hdl from scratch. > > if you think that your processor has some use at all then you > should take that effort and do the conversion to VHDL (or verilog) not a top priority for me at present, maybe some pay design later :) cheers. p.s. is there an altera specific IP section on there site as i can not find it if there?Article: 109899
> >Eli Bendersky wrote: > > What does this technique lack to be the perfect solution for resets in > FPGA designs ? It seems that it evades all the common disadvantages of > conventional sync and async resets. > > The only thing I see that this technique lacks is the ability to filter (for noise, glitches) the incoming reset signal. This approach can filter on the LO-HI transition of reset, but not on the HI-LO assertion. So, if there is any noise or glitching on the reset input resulting in a HI-LO transition, all logic in the FPGA is instantly reset (i.e. asynchronous reset). Most designs I work with use some form of analog circuitry to provide the main reset to the FPGA. I do like the fact that reset will be applied even in the absence of a clock. However, I have not yet implemented this technique because I am not sure how to provide filtering on the HI-LO transition of the input reset signal without requiring a clock. Can anyone help with this? What are your ideas?
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