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Markus Zingg wrote: > Hi group > > This must sound like a dumb question. How can I update from ISE and > EDK 8.1 to 8.2? > > I downlaoded and installed the available patches for 8.1 and there are > patches available for 8.2 but I can't see an option / way to actually > update 8.1 into 8.2. Do I just have to downlaod and install the 8.2 > patches (haven't tried this since I'm afraid to screw things up). Is > there another way? > I usually do a fresh install for .x releases. Cheers, JonArticle: 109426
Markus Zingg wrote: > Hi group > > This must sound like a dumb question. How can I update from ISE and > EDK 8.1 to 8.2? 8.2i is not an update to 8.1i. It is a new product. --- Joe Samson Pixel VelocityArticle: 109427
Markus Zingg schrieb: > Hi group > > This must sound like a dumb question. How can I update from ISE and > EDK 8.1 to 8.2? > > I downlaoded and installed the available patches for 8.1 and there are > patches available for 8.2 but I can't see an option / way to actually > update 8.1 into 8.2. Do I just have to downlaod and install the 8.2 > patches (haven't tried this since I'm afraid to screw things up). Is > there another way? > > TIA > > Markus it depends on your license if you are able to download 8.2 or not. there is no automatic upgrade if your license is expired or does not allow electronic delivery of the ISE/EDK you cant just install 8.2 patches, you need the 8.2 DVD or DVD image AnttiArticle: 109428
If you are on an active maintenance you should get 8.2 in the mail. You can also ask for access to downloadable version. If your maintenance has expired you will have to buy it again... /Mikhail "Markus Zingg" <m.zingg@nct.ch> wrote in message news:84qih21cmljcenbnu2etliv8175jjploln@4ax.com... > Hi group > > This must sound like a dumb question. How can I update from ISE and > EDK 8.1 to 8.2? > > I downlaoded and installed the available patches for 8.1 and there are > patches available for 8.2 but I can't see an option / way to actually > update 8.1 into 8.2. Do I just have to downlaod and install the 8.2 > patches (haven't tried this since I'm afraid to screw things up). Is > there another way? > > TIA > > Markus >Article: 109429
John Larkin wrote: > On Mon, 25 Sep 2006 22:26:56 -0400, Ray Andraka <ray@andraka.com> > wrote: > > >>John Larkin wrote: >> >> >>> >>>An opamp-based allpass 90 degree phase shifter is pretty simple; 8 >>>opamp sections, 8 caps, 24 resistors gives nice quadrature signals >>>over the voice range. And simulating a R-C section in an FPGA is >>>trivial. So it seems to me that one could do a nice Hilbert with a >>>fairly small amount of FPGA resources by just mimicing the opamp >>>circuit in discrete time. That would be a lot smaller than a FIR >>>implementation. >>> >>>Anybody done it this way? >>> >>>John >>> >> >>That's an IIR implementation. Generally speaking, IIR filters do not >>have the phase linearity required by many of the modern modulation >>schemes. They are fine for AM/FM, but when you start dealing with phase >>modulation, the non-linearity can make it extremely difficult to >>demodulate the signal. > > > Maybe so, but my trusty old Williams filter book has, for a 10-element > opamp-based allpass network, > > 26:1 frequency range, 0.007 degree error > > 57:1, 0.026 > > 286:1, 0.21 > > 1146:1, 0.66 > > > which look pretty good. And a digital implementation should nail the > pole/zero locations exactly. I do lowpass filters this way some > times... just design an active analog filter, and simulate it > digitally. > > John > Those don't have linear phase. There are also the issues with finite precision in IIR filters which lead to limit cycles and misplaced poles/zeros. For digital comms applications, we generally use FIR filters because they eliminate those issues, albiet with some added computational complexity. For downconversion, the Hilbert transform can generally be done with a complex mixer and the low pass filters you'd need anyway.Article: 109430
On Tue, 26 Sep 2006 14:30:48 -0400, "MM" <mbmsv@yahoo.com> wrote: >If you are on an active maintenance you should get 8.2 in the mail. You can >also ask for access to downloadable version. If your maintenance has expired >you will have to buy it again... > > >/Mikhail Hmmm, odd - I just got my developper kit from AVNet ~6 weeks ago. I don't know if this means I'm able to get 8.2 now or not. Thanks anyways, I will try if I can find out by going through our purchase departement.... MarkusArticle: 109431
On Tue, 26 Sep 2006 14:48:28 -0400, Ray Andraka <ray@andraka.com> wrote: >John Larkin wrote: > >> On Mon, 25 Sep 2006 22:26:56 -0400, Ray Andraka <ray@andraka.com> >> wrote: >> >> >>>John Larkin wrote: >>> >>> >>>> >>>>An opamp-based allpass 90 degree phase shifter is pretty simple; 8 >>>>opamp sections, 8 caps, 24 resistors gives nice quadrature signals >>>>over the voice range. And simulating a R-C section in an FPGA is >>>>trivial. So it seems to me that one could do a nice Hilbert with a >>>>fairly small amount of FPGA resources by just mimicing the opamp >>>>circuit in discrete time. That would be a lot smaller than a FIR >>>>implementation. >>>> >>>>Anybody done it this way? >>>> >>>>John >>>> >>> >>>That's an IIR implementation. Generally speaking, IIR filters do not >>>have the phase linearity required by many of the modern modulation >>>schemes. They are fine for AM/FM, but when you start dealing with phase >>>modulation, the non-linearity can make it extremely difficult to >>>demodulate the signal. >> >> >> Maybe so, but my trusty old Williams filter book has, for a 10-element >> opamp-based allpass network, >> >> 26:1 frequency range, 0.007 degree error >> >> 57:1, 0.026 >> >> 286:1, 0.21 >> >> 1146:1, 0.66 >> >> >> which look pretty good. And a digital implementation should nail the >> pole/zero locations exactly. I do lowpass filters this way some >> times... just design an active analog filter, and simulate it >> digitally. >> >> John >> > >Those don't have linear phase. There are also the issues with finite >precision in IIR filters which lead to limit cycles and misplaced >poles/zeros. For digital comms applications, we generally use FIR >filters because they eliminate those issues, albiet with some added >computational complexity. > >For downconversion, the Hilbert transform can generally be done with a >complex mixer and the low pass filters you'd need anyway. Given a signal frequency range F1 to F2, and, say 0.5 degree or less error, do you have any wild/rough guess as to the minimum clock frequency and number of taps for an FIR Hilbert phase shifter? I assume that, as absolute minimum conditions, the delay line must be at least long enough to store 180 degrees of the waveform at F1, and that the clock has to be at least 2 times F2. What sort of real-life numbers do people use? I'm thinking here about digitizing AC voltage and current waveforms in stationary and aircraft power systems and extracting the real and imaginary power components, so I'd need a wideband (say, 40 to 800 Hz) 90 degree phase shifter good to a fraction of a degree. JohnArticle: 109432
solo wrote: > I am searching for a new topic related to FPGAs and that is > publishable? > Any ideas? > I was thinking of area, performance, speed and interconnection > optimization. Please provide me with some interesting ideas and I will > do the rest of the work. > Thanks! how about single inline fpga which use veroboard spacing, and can be broken off at one pin intervals. place 4 pins in prigrammer for power, clk, and program data, and then break off to length specified by fpga compilier. available in 1m strips maybe. needs comparator for analog input, and as much logic in 1 pin segment as possible. flash on board prefered, with some 4 cycle dram too, for compactness. is this the kind of thing u meant??Article: 109433
> Hmmm, odd - I just got my developper kit from AVNet ~6 weeks ago. I > don't know if this means I'm able to get 8.2 now or not. Thanks > anyways, I will try if I can find out by going through our purchase > departement.... You are definitely eligible for the upgrade. Talk to Xilinx directly and ask for access to downloadable version. /MikhailArticle: 109434
Hello, I know that this has been discussed here a few times but I still can't find a definitive answer so here we go again... What is the best way (with Xilinx flow) to ensure that registers are packed into IOB? In my case I want three registers to be packed into the IOB for a bidirectionnal signal (in, out and oe). The registers in question are buried in a vhdl module two hierchical levels down. This module is synthesized separately into a ngc file (as most of my other modules) to create an "incremental" flow. I'm not using xst own incremental flow however (i.e. I'm not using a xcf file with -incremental_synthesis flags). To make matters a little more difficult, I would really like to keep the hierarchy as it makes it much easier to debug with Chipscope. I read quite a bit about the issue and the standard tricks seem to be: 1- Use the IOB = "true" constraint in the HDL code for the registers 2- Use the flag -iob true for xst (redundant with #1) 3- Use -pr b at the map stage 4- Duplicate the oe registers and use equivalent_register_removal = "NO" to prevent xst from optimizing them away 5- Make sure that the fanout of output registers and fanin of input registers is 1. 6- Run map with the option -ignore_keep_hierarchy to flatten the design. 7- From Xilinx WP231: When using hierarchy: "Place all I/O components including any instantiated I/O buffers, registers, DDR circuitry, SerDes, or delay elements on the top-level of the design. If it is not possible to place them on the top-level, ensure that they are all contained within a single hierarchy." Now I followed the above tricks except #7. For the moment I'd be happy even if I don't keep hierarchy. The best I could acheive so far is that the input registers are in the IOB. The out and oe registers however are not. Now maybe if I followed trick #7, I could make it work but it seems very ugly to me. I don't want logic on the top level that is related to a sub module two levels down. Furthermore, using the flag ignore_keep_hierarchy at the map stage should produce the same result, shouldn't it? Any suggestions? Thank you. Patrick DuboisArticle: 109435
This gives a whole new meaning to the term "partial reconfiguration" Todd jacko wrote: > how about single inline fpga which use veroboard spacing, and can be > broken off at one pin intervals. > > place 4 pins in prigrammer for power, clk, and program data, and then > break off to length specified by fpga compilier. > > > available in 1m strips maybe. > > > needs comparator for analog input, and as much logic in 1 pin segment > as possible. > > > flash on board prefered, with some 4 cycle dram too, for compactness. > > > is this the kind of thing u meant??Article: 109436
Hello,
On Wed, Sep 13, 2006 at 05:15:24PM -0700, funkrhythm wrote:
> Benedikt Wildenhain wrote:
> > Now I want to try sending some IP packets accross the wire, but both
> > xilnet and lwip insist on using either opb_ethernet or -lite. Are there
> > any adjusted versions for one of these?
> don't know about that, i am running linux on the V4FX12 and the EDK
> generates an ethernet driver (xilinx_gige) that works with the
> PLB_TEMAC
How did you compile a matching kernel? I tried to compile a 2.4 kernel
(I tried several branches, but finally got farest with the branch from
bee2.eecs.berkeley.edu as it already has integrated the xilinx_gige
driver) with the BSP for Montavista Linux 3.1. As (menu|x)config doesn't
offer my board I set CONFIG_MEMEC_2VPX=y, tried to compile it with
support for uartlite (for the serial console) and xilinx_gige, but
linking the kernel fails with
/space/benedikt/crosstool/gcc-3.4.1-glibc-2.3.3/powerpc-405-linux-gnu/bin/powerpc-405-linux-gnu-ld -T arch/ppc/vmlinux.lds -Ttext 0xc0000000 -Bstatic arch/ppc/kernel/head_4xx.o init/main.o init/version.o init/do_mounts.o \
--start-group \
arch/ppc/kernel/kernel.o arch/ppc/platforms/platform.o arch/ppc/mm/mm.o arch/ppc/lib/lib.o kernel/kernel.o mm/mm.o fs/fs.o ipc/ipc.o arch/ppc/math-emu/math-emu.o arch/ppc/xmon/x.o \
drivers/char/char.o drivers/block/block.o drivers/misc/misc.o drivers/net/net.o drivers/macintosh/macintosh.o drivers/media/media.o \
net/network.o \
/space/benedikt/tfc/bee2.eecs.berkeley.edu/linuxppc-2.4/lib/lib.a \
--end-group \
-o vmlinux
arch/ppc/platforms/platform.o(.text.init+0x3e): In function `board_io_mapping':
: undefined reference to `rs_table'
arch/ppc/platforms/platform.o(.text.init+0x46): In function `board_io_mapping':
: undefined reference to `rs_table'
arch/ppc/xmon/x.o(.text+0x64): In function `xmon_map_scc':
: undefined reference to `__sysrq_put_key_op'
make: *** [vmlinux] Error 1
Later I tried to create an auto-config.in with the BSP for uclinux, but
this also failed:
Running generate for OS'es, Drivers and Libraries ...
#--------------------------------------
# uClinux BSP generate...
#--------------------------------------
ERROR:MDT - ERROR FROM TCL:- uclinux () - expected integer but got ""
while executing
"format "0x%08x" $mem_start"
(procedure "do_memory_setup" line 64)
invoked from within
"do_memory_setup $config_file $os_handle "FLASH_MEMORY" CONFIG_XILINX_FLASH"
(procedure "::sw_uclinux_v1_00_d::generate" line 23)
invoked from within
"::sw_uclinux_v1_00_d::generate 148725840"
TARGET_PERIPH: hard_temac_0
ARG: C_PHY_TYPE VALUE: 0
ERROR:MDT - Error while running "generate" for processor ppc405_0...
make: *** [ppc405_0/lib/libxil.a] Error 2
--
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Mit freundlichen Gruessen | Kun afablaj salutoj (www.esperanto.org)
May the tux be with you. :wq 73
Article: 109437We may have to teach Mr Solo some basic facts: First you must have an interesting idea or some valuable specific knowledge. Then, and only then, do you start writing an article. He seems to have this ass-backwards. Beyond that it might also be wise not to insult this newsgroup with arrogant statements about the lust for capitalization. Peter Alfke ============= Todd Fleming wrote: > This gives a whole new meaning to the term "partial reconfiguration" > > Todd > > jacko wrote: > > how about single inline fpga which use veroboard spacing, and can be > > broken off at one pin intervals. > > > > place 4 pins in prigrammer for power, clk, and program data, and then > > break off to length specified by fpga compilier. > > > > > > available in 1m strips maybe. > > > > > > needs comparator for analog input, and as much logic in 1 pin segment > > as possible. > > > > > > flash on board prefered, with some 4 cycle dram too, for compactness. > > > > > > is this the kind of thing u meant??Article: 109438
Hello all, Forgive me in advance for the long plea for help. Would anyone be kind enough to troubleshoot my implementation of the EDK 8.1i flow for my production board? I have implemented a good deal of my project firmware on the Spartan 3 evaluation board with great success. However, upon receipt of my 3E based prototype hardware, I have had nothing but problems successfully porting my design from evalution hardware to prototype hardware. NOTE: On occasion, the firmware will operate as expected on the prototype board ruling out (hopefully) any board level issues. My issues seem to be more related to the EDK flow itself or perhaps my lack of understanding of aforementioned EDK flow. ## Physical Differences ## The only differences between the prototype hardware and the evaluation platform wrt the FPGA are as follows: (1) 500E vs. 200 (2) 100MHz LVDS clock vs. 50 MHz I have inserted the differential-to-single-ended buffers as per the Xilinx app note regarding differntial clocks. ## The Working Hack ## I can take the previous design targeted for the evaluation board (Spartan 3 Starter) and do the following: (1) Change the target hardware to the Spartan 3E 500E (2) Insert the differential input buffer (3) Modify the evaluation board UCF to accomadate the prototype implementation This method works. However, the boad rate (9600bps) is off by a factor of the clock speed multiple (x2). ## The Failed Flow ## Creating a new project targeted towards my prototype hardware (3E@100MHz) fails miserably. Despite repeated efforts across many variations on a theme, I can't even implement a STDIO RS232 interface executing the puked up diagnostic routines. PAR takes a rediculously long period of time and timing constraints seem to complicate the issue. I'm sure I haven't provided enough pertinent information to characterize my problem. So, if anyone has any ideas or question which would lead me in the correct direction I'd be very appreciative. This exercise seems very straight forward and I'm at a loss as to why I'm having such a hard time doing something so simple. Thanks :)Article: 109439
Todd Fleming wrote: > This gives a whole new meaning to the term "partial reconfiguration" > > Todd sure does > jacko wrote: > > how about single inline fpga which use veroboard spacing, and can be > > broken off at one pin intervals. > > > > place 4 pins in prigrammer for power, clk, and program data, and then > > break off to length specified by fpga compilier. > > > > > > available in 1m strips maybe. > > > > > > needs comparator for analog input, and as much logic in 1 pin segment > > as possible. > > > > > > flash on board prefered, with some 4 cycle dram too, for compactness. > > > > > > is this the kind of thing u meant?? if the pin ga to pin ga joints are flexi then 10m reels may be more gerber amenable. i think it could work. another great public domain idea provided by K Ring Technologies Semiconductor http://indi.joox.netArticle: 109440
mjackson wrote: > Hello all, > > Forgive me in advance for the long plea for help. > > Would anyone be kind enough to troubleshoot my implementation of the > EDK 8.1i flow for my production board? > > I have implemented a good deal of my project firmware on the Spartan 3 > evaluation board with great success. However, upon receipt of my 3E > based prototype hardware, I have had nothing but problems successfully > porting my design from evalution hardware to prototype hardware. > > NOTE: On occasion, the firmware will operate as expected on the > prototype board ruling out (hopefully) any board level issues. > > My issues seem to be more related to the EDK flow itself or perhaps my > lack of understanding of aforementioned EDK flow. > > ## Physical Differences ## > The only differences between the prototype hardware and the evaluation > platform wrt the FPGA are as follows: > > (1) 500E vs. 200 > (2) 100MHz LVDS clock vs. 50 MHz > > I have inserted the differential-to-single-ended buffers as per the > Xilinx app note regarding differntial clocks. > > ## The Working Hack ## > I can take the previous design targeted for the evaluation board > (Spartan 3 Starter) and do the following: > > (1) Change the target hardware to the Spartan 3E 500E > (2) Insert the differential input buffer > (3) Modify the evaluation board UCF to accomadate the prototype > implementation > > This method works. However, the boad rate (9600bps) is off by a factor > of the clock speed multiple (x2). > > ## The Failed Flow ## > Creating a new project targeted towards my prototype hardware > (3E@100MHz) fails miserably. Despite repeated efforts across many > variations on a theme, I can't even implement a STDIO RS232 interface > executing the puked up diagnostic routines. PAR takes a rediculously > long period of time and timing constraints seem to complicate the > issue. > > I'm sure I haven't provided enough pertinent information to > characterize my problem. So, if anyone has any ideas or question which > would lead me in the correct direction I'd be very appreciative. This > exercise seems very straight forward and I'm at a loss as to why I'm > having such a hard time doing something so simple. > > Thanks :) put a single T flip flop to divide clock for baud rate.Article: 109441
hi having difficulty doing a ftp logon need new ad free webserver space 50MB (no budget) any offers?? http://indi.joox.netArticle: 109442
"jacko" <jackokring@gmail.com> wrote in message news:1159302368.009079.245040@k70g2000cwa.googlegroups.com... > > solo wrote: >> I am searching for a new topic related to FPGAs and that is >> publishable? >> Any ideas? >> I was thinking of area, performance, speed and interconnection >> optimization. Please provide me with some interesting ideas and I will >> do the rest of the work. >> Thanks! > > how about single inline fpga which use veroboard spacing, and can be > broken off at one pin intervals. > > place 4 pins in prigrammer for power, clk, and program data, and then > break off to length specified by fpga compilier. > > > available in 1m strips maybe. > > > needs comparator for analog input, and as much logic in 1 pin segment > as possible. > > > flash on board prefered, with some 4 cycle dram too, for compactness. > > > is this the kind of thing u meant?? > i THINK IT SHOULD BE A möBIUS STRIP fpga. sPECIFICALLY, A fpga SHAPED LIKE A möBIUS STRIP. tO BE PRECISE, A TWO DIMENSIONAL kLEIN BOTTLE. i URGE YOU TO UPDATE YOUR UNDERSTANDING OF MY CLEAR AND ACCCURATE ADVICE. hth< YOURS 7TC< sYMSXArticle: 109443
Link to entire thread
http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/6d594b2ab04beb4b/e39055a323c18cd6#e39055a323c18cd6
Thanks for that, KJ. Meditating on timing issues, and looking at the
mapper timing report resulted in me setting the input setup times and
output valid delays in the testbench to exceed the maximum figures of
"Setup to clk (edge)" and "clk (edge) to pad" that were reported. I
took the additional conservative step of halving the clock frequency.
Now my post-map sim. is giving me correct results. It is odd that
improper timing would cause byte mixup like that, but I can certainly
contemplate types of interconnections that might behave that way. The
only other thing that I think helped was making my design synchronous
by registering all data in clocked registers. One thing I clued into is
that you can't, at least in Xilinx, set a signal in two or more
different processes, because that results in multiple sourcing and
unknown ('X') output. Also, if something like the following is written,
which is the correct way to write a register:
MY_PROC : process (clk, rst) is
begin
if (rst = '0') then
a <= '1';
elsif (clk'event and (clk = '1')) then
if (b = '0') then
a <= '1';
else
a <= '0';
end if;
end if;
end process MY_PROC;
Whatever is put in for "rst" will be the reset, and if you try to put
other signals, that you use for something else elsewhere, in the place
of "rst" in the above, Xilinx will connect them to your input port's
reset signal and create all sorts of mess.
Best regards,
-James
Article: 109444Symon wrote: > "jacko" <jackokring@gmail.com> wrote in message > news:1159302368.009079.245040@k70g2000cwa.googlegroups.com... > > > > solo wrote: > >> I am searching for a new topic related to FPGAs and that is > >> publishable? > >> Any ideas? > >> I was thinking of area, performance, speed and interconnection > >> optimization. Please provide me with some interesting ideas and I will > >> do the rest of the work. > >> Thanks! > > > > how about single inline fpga which use veroboard spacing, and can be > > broken off at one pin intervals. > > > > place 4 pins in prigrammer for power, clk, and program data, and then > > break off to length specified by fpga compilier. > > > > > > available in 1m strips maybe. > > > > > > needs comparator for analog input, and as much logic in 1 pin segment > > as possible. > > > > > > flash on board prefered, with some 4 cycle dram too, for compactness. > > > > > > is this the kind of thing u meant?? > > > i THINK IT SHOULD BE A m=F6BIUS STRIP fpga. sPECIFICALLY, A fpga SHAPED L= IKE A > m=F6BIUS STRIP. tO BE PRECISE, A TWO DIMENSIONAL kLEIN BOTTLE. i URGE YOU= TO > UPDATE YOUR UNDERSTANDING OF MY CLEAR AND ACCCURATE ADVICE. > hth< YOURS 7TC< sYMSX leads to problems of orientability. i have studied topology in the mathematical sense. paypal donations to k ring tech semi using : jackokring@yahoo.com email. would also help in transfering my webserver to another space (50mb) as no budget at moment. also looking for funding to get an office off the ground, profit share a possibility.Article: 109445
solo wrote: > David Ashley wrote: > >>solo wrote: >> >>>I am searching for a new topic related to FPGAs and that is >>>publishable? >>>Any ideas? >>>I was thinking of area, performance, speed and interconnection >>>optimization. Please provide me with some interesting ideas and I will >>>do the rest of the work. >>>Thanks! >>> >> >>Any improvements that can be made in the place + route >>burden would be publishable, as well as make you $$$. >> >>-Dave > Hey Dave, > > Can you be more specific in your advice please? > > Thanks! I'm told there haven't been any improvements to the place + route for the last 15 years, most of the improvements have been in integrating lots of different applications into single ones. Place + route = what has to be done automatically to map a netlist to actual fpga hardware. It is extremely computationally intensive. If you can improve the process, perhaps utilize fpga's to accelerate it somehow...people will be interested. -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 109446
Symon wrote: > i THINK IT SHOULD BE A möBIUS STRIP fpga. sPECIFICALLY, A fpga SHAPED LIKE A > möBIUS STRIP. tO BE PRECISE, A TWO DIMENSIONAL kLEIN BOTTLE. i URGE YOU TO > UPDATE YOUR UNDERSTANDING OF MY CLEAR AND ACCCURATE ADVICE. > hth< YOURS 7TC< sYMSX This _really_ cracked me up. I'm still laughing... -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 109447
jacko wrote: > hi > > having difficulty doing a ftp logon > > need new ad free webserver space 50MB (no budget) > > any offers?? > > http://indi.joox.net > What were you planning putting on the web site? I tried to go to the URL on your email but no go. I have offered sub domains to people on my web site that had content that I was interested in. But my domains have to do with Radio's which is hy I'm interested in FPGA's and programming languages such as Forth, ErLang, Lisp...etc -- Cecil KD5NWA www.qrpradio.com www.hpsdr.com "Sacred Cows make the best Hamburger!" Don Seglio Batuna From spampostmaster@comcast.net Tue Sep 26 17:33:05 2006 Path: newssvr21.news.prodigy.com!newsdbm04.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.comcast.com!news.comcast.com.POSTED!not-for-mail NNTP-Posting-Date: Tue, 26 Sep 2006 19:32:21 -0500 From: Phil Hays <spampostmaster@comcast.net> Subject: Re: Pack registers (from submodule) into IOB for bidirectionnal signal Date: Tue, 26 Sep 2006 17:33:05 -0700 User-Agent: Pan/0.14.2.91 (As She Crawled Across the Table) Message-Id: <pan.2006.09.27.00.33.04.313633@comcast.net> Newsgroups: comp.arch.fpga References: <1159306383.253393.143560@b28g2000cwb.googlegroups.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 18 NNTP-Posting-Host: 24.16.63.21 X-Trace: sv3-rJMNQ7i6efWowpRhN5/xsZ2E0OKcbGux+AZWV76Ot9GIzaAmq0IzIdQeJlaz5IWEqx12mvBxR5mJ+g9!1pFOLuDJssoHoqg8dBqvaEs8+gnMgIBgLAMsiC7ExdXdPSYpsVmKY/RzXX3DahGVUVsOjBoZPiSX!Xfpddg== X-Complaints-To: abuse@comcast.net X-DMCA-Complaints-To: dmca@comcast.net X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.32 Xref: prodigy.net comp.arch.fpga:120363 Patrick Dubois wrote: > What is the best way (with Xilinx flow) to ensure that registers are > packed into IOB? In my case I want three registers to be packed into the > IOB for a bidirectionnal signal (in, out and oe). <trimmed> Make sure that the FFs can fit into the IOB. For Virtex, for example, the clock and reset are common between the FFs in the IOB. If the input FF is on clock_foo and the output FF is on clock_blah, then both FFs can not fit into an IOB. If a reset is generated to the FFs, it must be the same reset signal for all FFs that are reset, or again the FFs can not be in the same IOB. -- Phil Hays (Xilinx, but speaking for myself)Article: 109448
Adnan wrote: > One thing more do any one of you guys have PCI core without > wishbone, as I think I am supposed to implement wishbone master to talk > with wishbone slave and wishbone slave to talk with wishbone master > (Please correct me if I am wrong). You'll only need a wishbone master if you're going to be mastering the PCI bus. Otherwise you'll only need to implement a wishbone slave interface on your PCI peripherals, and that's about as trivial as you can get. For example, for a simple register with a 1-clock turn-around all you need is a clocked process that drives a qualified wb_cyc_i onto wb_ack_o. Even requiring a master, depending on your application, really isn't a big deal. Given a core without wishbone, you'd *still* be doing the same thing anyway - it just wouldn't be wishbone complaint. And for some cores I've seen, you would actually be required to do *more* work than you do for wishbone. No free lunches here. > Thanks alot for your valuable opionion, I am trying hard with the > testbench. I need test bench because first we need to run simulation > after integrating PCI core with our logic. So that things could run > smoothly on FPGA. As bundled, the testbench exercises the PCI core and tests for corner conditions etc. If you want to be able to simulate meaningful PCI accesses to your back-end peripherals, you'll need to extract and probably modify the functions from the testbench that perform PCI read and write transactions. You'll also have to retain the portions that configure the bridge at the start of it all. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 109449
On 27 Sep 2006 01:46:33 +0200, "Symon" <symon_brewer@hotmail.com> wrote: >"jacko" <jackokring@gmail.com> wrote in message >news:1159302368.009079.245040@k70g2000cwa.googlegroups.com... >> >> solo wrote: >>> I am searching for a new topic related to FPGAs and that is >>> publishable? >>> Any ideas? >>> I was thinking of area, performance, speed and interconnection >>> optimization. Please provide me with some interesting ideas and I will >>> do the rest of the work. >>> Thanks! >> >> how about single inline fpga which use veroboard spacing, and can be >> broken off at one pin intervals. >> >> place 4 pins in prigrammer for power, clk, and program data, and then >> break off to length specified by fpga compilier. >> >> >> available in 1m strips maybe. >> >> >> needs comparator for analog input, and as much logic in 1 pin segment >> as possible. >> >> >> flash on board prefered, with some 4 cycle dram too, for compactness. >> >> >> is this the kind of thing u meant?? >> >i THINK IT SHOULD BE A möBIUS STRIP fpga. sPECIFICALLY, A fpga SHAPED LIKE A >möBIUS STRIP. tO BE PRECISE, A TWO DIMENSIONAL kLEIN BOTTLE. i URGE YOU TO >UPDATE YOUR UNDERSTANDING OF MY CLEAR AND ACCCURATE ADVICE. >hth< YOURS 7TC< sYMSX I have already patented this idea, whatever it is. Please refer to Pat. 23764598, "Eine Kleine Bottle/Nachtmusik." Royalty payments are of course welcome. Bob Perlman Cambrian Design Works
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