Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
I'would rather not use the HW TCP/IP stack if possible (logic resources, portability...). Use the SW implemented instead. You have several options: xilnet - Xilinx EDK stack (limitations about MACs) uip and lwip - Adam Dunkels free stack Treck - high performance stack (not free) I suggest you try the MicroBlaze uClinux with networking included (Dr John Williams) http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/ It is very lightweight (far more than separate stacks)!!! Cheers, Guru Sudhir.Singh@email.com wrote: > check out > http://www.itee.uq.edu.au/~peters/xsvboard/stack/stack.htm > > David wrote: > > hi > > i am new whit FPGA i just buy the spartan-3e starter kit, > > i am looking a tcp/ip stack to use whit the kit ( a free one) > > if any one have some info it will we great > > thanks > > DavidArticle: 106801
zlotawy wrote: > > and do you know if ucf file is the same for all V2P family? > > I have error: > > "LOC constraint W32 on P_IO_DQ<10> is invalid: No such site on > the device. To bypass this error set the environment variable > 'XIL_MAP_LOCWARN'." > > I used xc2vp2-6ff672 > Is it possible to be correct for xc2vp30-6ff1152 ? No. Each package has a different pin definition. Here's a link to the V2Pro complete data sheet. Module 4 has the package pinouts: http://direct.xilinx.com/bvdocs/publications/ds083.pdf --- Joe Samson Pixel VelocityArticle: 106802
Jim, http://direct.xilinx.com/bvdocs/publications/ds123.pdf claims 20,00 program/erase cycles. Is this what you are asking about? If you desire more information, I can look into it, AustinArticle: 106803
Austin Lesea wrote: > Jim, > > http://direct.xilinx.com/bvdocs/publications/ds123.pdf > > claims 20,00 program/erase cycles. > > Is this what you are asking about? If you desire more information, I > can look into it, If those are what's on the PCB under discussion, thanks. That sounds like a few design iterations ! :) I guess one way to determine if this is some early failure mode in FLASH ( or some marginal SW/timing issue) is to change the FLASH. The OP could try that ? <paste> burn.sir@gmail.com wrote: > The error rate is something like 2-3%. Does this mean it fully pases 97-98% of the time ( fails only one in 30 downloads ), or that the memory compare, shows a cell-match failure of 2-3%, and a download never fully works ? -jgArticle: 106804
"A.D." <no.mail@nowhere.xyz> wrote in message news:KsnFg.74988$_J1.738667@twister2.libero.it... > Hi guys! > I'm experiencing same problems with don't care conditions in > VHDL (with ISE / ModelSim)... > I'm wondering if using don't cares in VHDL is a safe > practice, since it seems that different tools treat them in > different ways! For example, if I test "1110 0010" against > "---- 0010" (with if, case, when and so on...) I expect to > obtain a match, since the four specified bits are the same. You need to use the std_match() function instead of the '=' operator. KJArticle: 106805
David M. Palmer wrote: asking about block floating point > > It all depends on what you are doing. > > If you are searching for tones in noisy data, where the strengths of > the tones and the noise aren't determined at design time, then > shift-if-you-need-it is a good strategy because you don't care about > the noise in frequency space, only the strongest signal. It gives you > overall dynamic range between, but not within, measurements. > > If you are trying to filter out an interfering frequency to see what's > underneath it, then losing everything below 2^-n of the largest > frequency tone is sub-optimal. If you use floating point with too few > bits in the significand, then there will be significance loss in a > complicated pattern in frequency space. > Exactly. It is useful when the dynamic range within a set is not large, but the dynamic range of possible inputs is largeArticle: 106806
Yes, that is referred to as block floating point. It is fairly common for hardware FFT engines. David M. Palmer wrote: > > Does anybody do the following thing?: At each step, the adders check > for whether the high order bit of any result is set. (Just an N-way OR > gate). If so, then the next step includes a right-shift (for all > elements), otherwise there is no right-shift. In the end, you get an > FFT result which must be scaled by 2^number-of-right-shifts, but has as > much resolution as is possible given the number of bits (for the > largest-magnitude components). > > Sort of similar to floating point, except that there is only one > exponent for all components. >Article: 106807
FlyingPenguin wrote: > Hi! I'm a newbie at designing circuits on FPGA and I have found out > something I cannot understand very well. I've written the VHDL > description of some Linear Feedback Shift Registers and I have > synthesised them with Xilinx's xst using different optimisations: for > Speed and for Area. I've noticed that, even if the Speed optimisation > leads in many cases to a faster circuit, sometimes it produces a slower > circuit than the Area optimisation. Though, this is quite infrequent. > The real problem, is with the Area optimisation, that, according to > xst's Synthesis Report, often produces a circuit with more flipflops, > used slices, and bonded IOBs than Speed optimisation. The only > unchanged or lower values are the number of BELs and LUTs used. How > can this be? Am I looking at the wrong values to see whether the area > has been reduced or not? Or is it a problem with some XST parameter? > Thanks in advance to everyone who will answer! FlyingPenguin It actually isn't unusual for optimizing area to produce slightly better timing figures. The router is trying to shrink the amount of space the design uses, so the timing *can* improve due to shorter routes between signals. On the other hand, it may also result in worse timing. However, as Mike pointed out, you don't get much more than just using auto. In general, you only need to mess with those settings when your design either doesn't make timing by a small margin, or won't fit by a small margin. Sometimes, you can get the design to make timing, or fit, with a little extra effort, and that's what those settings do - they tell the software to push a little harder in one direction or the other. If you are comfortably making timing, and easily fit in your target device, you shouldn't see much difference at all.Article: 106808
Raymond wrote: > Hi there > > When I synthesis my design I get some warning messages. > > A strange on is this: <<WARNING:Xst:647 - Input <clk> is never used.>> > > It is declared in the Entity: > entity RS232 is > Port ( > reset : in std_logic; > clk : in STD_LOGIC; > rx : in STD_LOGIC; > PData : out STD_LOGIC_VECTOR (7 downto 0); > PDataAcc : out STD_LOGIC); > end RS232; > > It is used in a process: > SmallClkPros : process(clk, reset) > begin > ... > ... > end process SmallClkPros; > > Why do I get this warning? > > Raymond > It simply means you are not using the signal in a synthesisable statement. Process signal enumerations are only relevant for simulation. Clock signals must be used in "if rising_edge(clk) then" statements to infer FFs in synthesis and extra conditions are used to infer clock-enable and mux logic. -- Daniel Sauvageau moc.xortam@egavuasd Matrox Graphics Inc. 1155 St-Regis, Dorval, Qc, Canada 514-822-6000Article: 106809
> A strange on is this: <<WARNING:Xst:647 - Input <clk> is never used.>> I am going to assume that you have something in your process that uses clk. In that case, the next likely candidate is that the synthesis tool has found no outgoing signals in that process, that is, signals that connect to output pins, or signals that connect to signals that go to output pins, and has therefore been eliminated. I believe that causes this warning in Xilinx ISE. Brad Smallridge aivisionArticle: 106810
vijayvithal jahagirdar wrote: > A few months ago a similar Idea was posted on an ASIC and Digital > design community at Orkut. The basic Idea was > a) To collect class notes/Presentation on a particular topic and expand > it to a book or > b) A person will come up with the book outline and others will submit > articles on specific topics and flesh it out > The final goal being to get a set of books on hardware design. You can > check the details at http://edaindia.com/books/ > > Regards > H.H.I Tracy Why not go with Wikipedia? It's so easy for anyone to add to. Just host the wikipedia software on some other server, if Wikipedia's policies aren't satisfactory. -DaveArticle: 106811
Brad Smallridge skrev: > > A strange on is this: <<WARNING:Xst:647 - Input <clk> is never used.>> > > I am going to assume that you have something > in your process that uses clk. In that case, > the next likely candidate is that the synthesis > tool has found no outgoing signals in that process, > that is, signals that connect to output pins, or > signals that connect to signals that go to output pins, > and has therefore been eliminated. I believe that > causes this warning in Xilinx ISE. > > Brad Smallridge > aivision Actually, the process generates an other "controllable" clock that clocks an other process that has signals that is connected to other signals that in turn goes to output pins. (puh) RaymondArticle: 106812
David Ashley <dash@nowhere.net.dont.email.me> writes: > vijayvithal jahagirdar wrote: >> A few months ago a similar Idea was posted on an ASIC and Digital >> design community at Orkut. The basic Idea was >> a) To collect class notes/Presentation on a particular topic and expand >> it to a book or >> b) A person will come up with the book outline and others will submit >> articles on specific topics and flesh it out >> The final goal being to get a set of books on hardware design. You can >> check the details at http://edaindia.com/books/ > > Why not go with Wikipedia? It's so easy for anyone to add to. > Just host the wikipedia software on some other server, if > Wikipedia's policies aren't satisfactory. One could use http://wikibooks.org or http://wikia.com/ for hosting. I too think that such a book project is doomed if the hurdle for contributing is too high. Cheers, ColinArticle: 106813
Hi with Virtex-4 I did a bad decision, namly I ordered the first board announced as available what was the Avnet-LX25 board. Avnet shipment delayed so much that at the time board was actually delivered other boards with better value for money had been available for some time already. I dont wanna make the same bad choice again by ordering the first available Virtex-5 board. But the information about real availability isnt much better then it was at the times Virtex-4 did come to the real world customers. 1) Xilinx online shop says that V5-AFX boards will become available June 2006. June 2006 is way past. 2) Xilinx eval board matrix document for Q2 2006 has a picture of ML501. We are now living mid Q3 2006. Is that all the info about Virtex-5 board availability? My guess is that this time the best board (best price-performance) and first board available will be from Xilinx, so I will not go running to buy some 3rd party board before ML501 availability is known - but WHEN !? AnttiArticle: 106814
Antti wrote: > Hi > > with Virtex-4 I did a bad decision, namly I ordered the first board > announced as available what was the Avnet-LX25 board. Avnet shipment > delayed so much that at the time board was actually delivered other > boards with better value for money had been available for some time > already. I dont wanna make the same bad choice again by ordering the > first available Virtex-5 board. But the information about real > availability isnt much better then it was at the times Virtex-4 did > come to the real world customers. But the Avnet-LX25 is not that bad. It was late, but it is nice ... > 1) Xilinx online shop says that V5-AFX boards will become available > June 2006. June 2006 is way past. > 2) Xilinx eval board matrix document for Q2 2006 has a picture of > ML501. We are now living mid Q3 2006. Just remember, how much later the spartan 3e board came. So, I would expect the same for a ml501 :(Article: 106815
Grrrrr! Has anyone got ISE 7.1 working with EDK in Windows? Ever seen this error before? I installed ISE/EDK per instructions, and got the titular error as soon as I tried to generate a netlist inside Platform Studio. I assumed it was something stupid I did/forgot to do, so I followed the tutorial at <http://direct.xilinx.com/direct/ise7_tutorials/EDK7.1_ML403.pdf>. When I click OK on the step at page 21 where a netlist is generated, I get the exact same error: Xilinx Platform Studio Xilinx EDK 7.1.2 Build EDK_H.12.5.1 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. XPS% Evaluating file c:/xilprj/myproject/project_navigator/__projnav/system.synth.tcl system.make:171: *** target pattern contains no `%'. Stop ERROR:MDT - Error while running "make -f system.make netlist" No changes to be saved in MSS file No changes to be saved in XMP file It's hard to imagine a more vanilla installation than the one I'm using, it's a WinXP install with everything defaulted. However I have a spare unused laptop in its box here, with NOTHING but WinXP on it - so I'm going to while away the hours installing the Xilinx software on that machine. By the way, line 171 of system.make is the @mkdir line in the following stanza: ################################################################# # BOOTLOOP ELF FILES ################################################################# $(PPC405_0_BOOTLOOP): $(PPC405_BOOTLOOP) @mkdir -p $(BOOTLOOP_DIR) cp -f $(PPC405_BOOTLOOP) $(PPC405_0_BOOTLOOP) Xilinx is well on the way to being my least favorite semiconductor vendor of all time. Apart from their obnoxious software licensing, there's a one business day delay in merely signing up for the privilege of asking a question, let alone actually receiving an answer. And they apparently never test their development software. I remember hating Altera's tools when I last used them (I can still see the gray hairs from that battle every time I look in a mirror), but at least their tutorials worked! Anyhow - if anyone has seen this error before (Google found nothing relevant), hints would be appreciated!Article: 106816
Colin Marquardt wrote: > David Ashley <dash@nowhere.net.dont.email.me> writes: > > > > Why not go with Wikipedia? It's so easy for anyone to add to. > > Just host the wikipedia software on some other server, if > > Wikipedia's policies aren't satisfactory. > > One could use http://wikibooks.org or http://wikia.com/ for hosting. > I too think that such a book project is doomed if the hurdle for > contributing is too high. > > Cheers, > Colin Most of the contributors to this thread seem to agree that writing a Speciality book does not justify the effort that needs to be put in. The reasons stated are 1> Small number of Digital designers. 2> Long time required to finish writing the book. As an example suppose I decide to write a document on "VHDL/Verilog coding style for Low Power mixed signal designs" which basically collates the various material available on this topic in Public domain and presents it in an easy to read and implement format. Out of the estimated 10,000 Digital design engineers only a couple of hundreds engineers (for e.g. those working on chips for handheld applications) will actually find the book useful to the work at hand and will be actually interested in buying the book. This makes the effort put in writing the book commerically unviable. Now suppose as a part of my normal work(either academic or otherwise) I come up with a similar document which my funding organisation allows me to put in public domain. I would rather prefer to put it as is(ppt,word,pdf,ps,html etc.) and move on to the next pending work, rather than rewrite the document in the format required by wiki. I think in such a situation one of the following approach may be suitable 1> Upload the document to my personal website and post the url to usenet and other forums. 2> Upload the document to a common repository(Some place for electronic documents similar to what CPAN is for Perl code or CTAN for tex macros) say a sharepoint or a twiki or an interface similar to CPAN. Collecting a set of similar articles, say on the topic of "digital design in a low power mixed signal design" written by different authors would give those 200 engineers working in this field a standard reference. Due to the different formats and writing styles it would not be a proper book but it can act as a loosely bound reference material At a later date if this does turn out to be a hot topic and a demand exists for a published text then it should be possible to get the proper permissions form the respective authors and cleanup the formatting linearise the content and publish the book. Regards VijayArticle: 106817
radarman wrote: > In general, you only need to mess with those settings when your design > either doesn't make timing by a small margin, or won't fit by a small > margin. Sometimes, you can get the design to make timing, or fit, with > a little extra effort, and that's what those settings do - they tell > the software to push a little harder in one direction or the other. > > If you are comfortably making timing, and easily fit in your target > device, you shouldn't see much difference at all. Actually, I have no target device at all. I just had to synthesise those components using many different devices and settings, and gather all the data. I had some trouble interpreting them, but your and Mike's answers are exactly what I was looking for. Thanks! FlyingPenguinArticle: 106818
For implementing the higher level protocols for my Spartan 3E starter kit TCP/IP stack implementation, I plan to use a CPU, because I think this needs less gates than in pure VHDL. The instruction set could be limited, because more instructions and less gates is good, and it doesn't need to be fast, so I can design a very orthogonal CPU, which maybe needs even less gates. The first draft: http://www.frank-buss.de/vhdl/cpu.html It is some kind of a 68000 clone, but much easier. What do you think of it? Any ideas to reduce the instruction set even more, without the drawback to need more instructions for a given task? -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 106819
Why not use PicoBlaze, which is freely available ? Or MicroBlaze if you need more speed? Peter Alfke, from home. Frank Buss wrote: > For implementing the higher level protocols for my Spartan 3E starter kit > TCP/IP stack implementation, I plan to use a CPU, because I think this > needs less gates than in pure VHDL. The instruction set could be limited, > because more instructions and less gates is good, and it doesn't need to be > fast, so I can design a very orthogonal CPU, which maybe needs even less > gates. The first draft: > > http://www.frank-buss.de/vhdl/cpu.html > > It is some kind of a 68000 clone, but much easier. What do you think of it? > Any ideas to reduce the instruction set even more, without the drawback to > need more instructions for a given task? > > -- > Frank Buss, fb@frank-buss.de > http://www.frank-buss.de, http://www.it4-systems.deArticle: 106820
Peter Alfke schrieb: > Why not use PicoBlaze, which is freely available ? > Or MicroBlaze if you need more speed? > Peter Alfke, from home. > > > Frank Buss wrote: > > For implementing the higher level protocols for my Spartan 3E starter kit > > TCP/IP stack implementation, I plan to use a CPU, because I think this > > needs less gates than in pure VHDL. The instruction set could be limited, > > because more instructions and less gates is good, and it doesn't need to be > > fast, so I can design a very orthogonal CPU, which maybe needs even less > > gates. The first draft: > > > > http://www.frank-buss.de/vhdl/cpu.html > > > > It is some kind of a 68000 clone, but much easier. What do you think of it? > > Any ideas to reduce the instruction set even more, without the drawback to > > need more instructions for a given task? > > > > -- > > Frank Buss, fb@frank-buss.de > > http://www.frank-buss.de, http://www.it4-systems.de To Peter, I can answer 1) PicoBlaze is too small 2) MicroBlaze is not free the OP is really going to try to make a full SoC with DDR memory controller and ethernet! as much as I have understood his reasons. sure it would be WAY CHEAPER to just use MicroBlaze !!! cheaper means in terms of money. The time and effort to make anything comparable to what you can achive with EDK and a few mouseclicks, defenetly costs more than 495USD unless your personal time doesnt count at all. To Frank, I was wondering (what you are up) well doing some 16 bit doesnt make much sense, a small 32 bit RISC isnt much larger. you could also use OpenFire and add wishbone interfaces, makes more sense then trying it all from scratch. unless you just want todo everything by yourself (and that is your goal, not achiving the best with least effort) BTW - 16 bit, I was looking at ColdFire, and well there is no coldfire FPGA clone yet, but that may make sense (kind 68000, but more RISClike, 16 bit instruction bus) AnttiArticle: 106821
Peter Alfke wrote: > Why not use PicoBlaze, which is freely available ? > Or MicroBlaze if you need more speed? PicoBlaze looks a bit like my idea: http://www.xilinx.com/bvdocs/ipcenter/data_sheet/picoblaze_productbrief.pdf But it has more instructions and it is not as much orthogonal as my CPU, so I think I can synthesize my CPU with less gates. But using memory instead of registers means that it is slower than PicoBlaze, but this is no problem for me. But maybe the main reason is, that it is fun to design CPUs :-) -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 106822
jetq88 wrote: > which one should I go in term of easy to learn and use, has more > support tool and low cost. > they both have web version of development software, is it enough to do > general work? > > thanks > From my experience I would suggest that you first try and get pricing for small order quantities. If X (A) parts are easily/readily available in small order quantities where you live then download the web tools and start coding. The worst thing you can do is start coding for a particular manufacturers parts only to realise that they are not available where you live BenArticle: 106823
Mark McDougall wrote: > category. I've done a few years work with Altera and have recently > cracked open ISE to play with a Spartan-3. I'm finding it an unpleasant > experience but I'm sure that I went through similar over the years when > getting my head around Quartus too?!? So I admit I'm biased atm... I'm going through the same thing, except that I _clearly_ remember how difficult I found it to use Altera's stuff. I think all this software is used by such a tiny number of people that you're just expected to get the ritual tattoos and piercings in order to join the cult that understands it. Since the developer community for each product is so small, usability is no priority at all. I wrestled with ISE for more than an hour just trying to put down something other than an ACC_16. At that time, I discovered that if you open ISE at 1024x768 resolution, the controls autosize themselves in such a way that the drop-down list to select a different part is invisible. I've yet to be convinced that the software is even functional...Article: 106824
I see that to run a process from an other process can be avoided (Like
I do now) so I tried to put everything in the same process, same
warnings.
////////////////////////// Warnings //////////////////////
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <reset> is never used.
WARNING:Xst:647 - Input <rx> is never used.
WARNING:Xst:646 - Signal <SmallCountReg> is assigned but never used.
WARNING:Xst:646 - Signal <RPData> is assigned but never used.
WARNING:Xst:646 - Signal <CountReg> is assigned but never used.
////////////////////////////////////////////////////////////////
////////////////////////// CODE ///////////////////////////
entity RS232 is
Port (
reset : in std_logic;
clk : in STD_LOGIC;
rx : in STD_LOGIC;
PData : out STD_LOGIC_VECTOR (7 downto 0);
PDataAcc : out STD_LOGIC);
end RS232;
architecture Behavioral of RS232 is
signal RPData : std_logic_vector(9 downto 0);
signal CountReg : std_logic_vector(12 downto 0);
signal SmallCountReg : std_logic_vector(3 downto 0);
signal RPDataAcc : std_logic;
begin
SmallClkPros : process(clk, reset)
begin
if(reset <= '1') then
CountReg <= conv_std_logic_vector(0, 13);
SmallCountReg <= conv_std_logic_vector(0, 4);
RPData <= conv_std_logic_vector(0, 10);
RPDataAcc <= '0';
elsif(rising_edge(clk)) then
if(rx = '0' and CountReg < conv_std_logic_vector(2604, 13) and
SmallCountReg = conv_std_logic_vector(0, 4)) then
CountReg <= CountReg + 1;
RPDataAcc <= '0';
elsif(rx = '0' and CountReg = conv_std_logic_vector(2604, 13) and
SmallCountReg = conv_std_logic_vector(0, 4)) then
CountReg <= CountReg + 1;
SmallCountReg <= SmallCountReg + 1;
RPData(0) <= rx;
RPData(9 downto 1) <= RPData(8 downto 0);
elsif(CountReg < conv_std_logic_vector(2604, 13) and
SmallCountReg < conv_std_logic_vector(10, 4) and
SmallCountReg > conv_std_logic_vector(0, 4)) then
CountReg <= CountReg + 1;
SmallCountReg <= SmallCountReg + 1;
RPData(0) <= rx;
RPData(9 downto 1) <= RPData(8 downto 0);
elsif(CountReg < conv_std_logic_vector(5208, 13) and
SmallCountReg > conv_std_logic_vector(0, 4) and
SmallCountReg < conv_std_logic_vector(10, 4)) then
CountReg <= CountReg + 1;
elsif(CountReg = conv_std_logic_vector(5208, 13) and
SmallCountReg > conv_std_logic_vector(0, 4) and
SmallCountReg < conv_std_logic_vector(10, 4)) then
CountReg <= conv_std_logic_vector(0, 13);
elsif(CountReg = conv_std_logic_vector(5208, 13) and
SmallCountReg = conv_std_logic_vector(10, 4)) then
SmallCountReg <= conv_std_logic_vector(0, 4);
CountReg <= conv_std_logic_vector(0, 13);
RPDataAcc <= '1';
end if;
end if;
end process SmallClkPros;
PData <= RPData(8 downto 1);
PDataAcc <= RPDataAcc;
end Behavioral;
////////////////////////////////////////////////////////////////////////
Raymond
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z