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Frank Buss schrieb: > Antti wrote: > > > 1) PicoBlaze is too small > > For me it looks like it is too large :-) > > > the OP is really going to try to make a full SoC with DDR memory > > controller and ethernet! as much as I have understood his reasons. > > Yes, and mainly for learning VHDL, so using finished products doesn't help > me and is not as much fun as doing it all by myself. > > > well doing some 16 bit doesnt make much sense, a small 32 bit RISC isnt > > much larger. > > The first use case for this CPU will be executing programs from block RAM, > for accessing all the hardware of the Spartan 3E starter kit. For this 32 > bit is not needed, but I'll use generics for the bit width, because when > using more memory than 64 kB or for more complicated tasks, 32 bit may be > more useful. > > > you could also use OpenFire > > Do you have a link? Searching for OpenFire at Google returns only ads for > fireplaces :-) http://www.ccm.ece.vt.edu/~amarschn/openfire/tools.html search openfire in google groups comp.arch.fpga and you get it a first hit AnttiArticle: 106851
peter.kampmann@googlemail.com schrieb: > I just didn't knew that I have to use the bootloop load the program via > xmd from memory. > Thougt that would work via Download Bitstream .... > "bootloops" are simple eternal loops that just loopforever - the are as default init programs in the case the actual program is loaded later. in such casesd the bootloop.elf will be placed into BRAMS and is loaded with bitfile when you configure the FPGA. When FPGA is released the bootloop, just loops forever - the only for reason for this is to make sure the processor isnt running wild but is kept doing something useful. like looping forever. when XMD is started it can then over the processor without letting the processor run loose. similarly if load the external memory via ACE file that uses the processor debug interface then the bootloop keeps the processor busy looping so it want disturb. when the download is done, then processor PC is set to the start address and the actual program starts. if you are not using systemACE or XMD then the bootloop is no use and you need a real bootloader instead AnttiArticle: 106852
> Next, In my project only 3 to 4 files are changed frequently. Rest > other files are not disturbed at all. > But still I am recompiling all files. Are there any commands available > so that I can skip compiling files which are not changed at all? > If you use Modelsim's project file you can simply right click and select 'Compile->Out of Date'. If not, then you need to use make. KJArticle: 106853
Frank Buss wrote: > For implementing the higher level protocols for my Spartan 3E starter kit > TCP/IP stack implementation, I plan to use a CPU, because I think this > needs less gates than in pure VHDL. The instruction set could be limited, > because more instructions and less gates is good, and it doesn't need to be > fast, so I can design a very orthogonal CPU, which maybe needs even less > gates. The first draft: > > http://www.frank-buss.de/vhdl/cpu.html > > It is some kind of a 68000 clone, but much easier. What do you think of it? > Any ideas to reduce the instruction set even more, without the drawback to > need more instructions for a given task? > > -- > Frank Buss, fb@frank-buss.de > http://www.frank-buss.de, http://www.it4-systems.de If you are interested in learning more than producing an actual product, I suggest designing your own CPU as well. I have been working on an 8-bit RISC processor, and it has definitely been eye-opening. I posted recently about my v8 uRISC/Arclite clone, which is currently not working while I'm implementing a deeper pipeline. I've learned a great deal about microprocessor design and optimization as a result. I now have a design capable of running at > 110MHz (by itself). By understanding what the processor is actually doing in each step (state), you can often find ways to squeeze extra functionality out of each clock cycle. For example, since my memory is pipelined, I was able to add a 16-bit auto-increment to the indexed load/store instructions at no cost (cycle-wise). I was also able to increment a DBNZ (decrement and branch if not zero) instruction at no cost. This saves 5 clock cycles per loop for memory copies. Doesn't sound like much, but remember that is per iteration. I can do a standard memory copy in 3 instructions - 5, if the loop count is greater than 256. I've identified several other areas of the design that could be optimized as well. Best of all, it's been fun - kind of like being in college all over again, without the final. -SethArticle: 106854
HI all i used antti's web page referance (as he said) and entered it into google translation web site. http://translate.google.com/translate?u=http%3A%2F%2Fwww.geocities.jp%2Fkwhr0%2Fhard%2Fpc8001.html&langpair=ja%7Cen&hl=en&ie=UTF8 Regards IAN. "BM" <osainto@free.fr> wrote in message news:1155879438.079757.149850@b28g2000cwb.googlegroups.com... Did translate another page from the original link : http://osainto.free.fr/USBHOST/UKP/Version%20traduite%20de%20la%20page%20http--www_asahi-net_or_jp-~qx5k-iskw-robot-usbhost.htm This one does contain actual material for HW connection aspects Great ! BM a écrit : > Thanks Antti ! > Put the tranlsated page here : > http://osainto.free.fr/USBHOST/UKP/Version%20traduite%20de%20la%20page%20http--www_geocities_jp-kwhr0-hard-pc8001.htm > > Not sure it does contain what i'm looking for (direct connection from > I/O pins to USB) but interesting anyway ..... > > > > Antti a écrit : > > > rickman schrieb: > > > > > Antti wrote: > > > > bm schrieb: > > > > > > > > > Interesting ...Any pointer ? > > > > > > > > you really learn how to goofle ! :) > > > > > > > > just enter "usb fpga ukp" as search term and there you, first hit! > > > > > > Was this a typo? I get a bunch of links to sites giving pricing in > > > Brittish pounds. > > > > > > Maybe you were referring to this... > > > > > > http://www.opencores.org/projects.cgi/web/usb_phy/overview > > NO. > > and NO typo. > > > > google search web search from my PC with keywords "usb fpga ukp" > > returns as first hit the following URL (I just rechecked!) > > > > http://www.geocities.jp/kwhr0/hard/pc8001.html > > > > AnttiArticle: 106855
Hi,
I work for a small company and we're looking at replacing some of our old
designs FPGAs (in this case because of part availability). This also
happens to be my first FPGA design so the learning curve is kind of
steep :)
The board takes data from a digitiser and averages it - it is complicated by
the fact that it is for a radar system so it is divided into range gates.
Each I/Q channel has its own averager board. The averager stores the
intermediate result in a FIFO and uses an ALU to add or subtract the next
result to the intermediate result (eg if there is phase flipping during
transmition). The averaged result is stored in a final FIFO to be read out
[a short time] later.
/16 /16
Dig -----> ALU ----+-> Right Shift -----> FIFO
^ |
| FIFO
|/32 |
| |
+------+
Unfortunately while it works in a behavioural simulation, a PAR simulation
doesn't. I imagine I have used an incorrect construct somewhere so I am not
synthesising what I want, although the RTL diagram looks OK to me.
Strangely I find that the results are fine but the final FIFO is either not
clocking the data in properly, or not clocking it out properly.. However if
I test it in isolation it works fine.
Also, due to the fact that this is supposed to be a drop in replacement I
can't change the overall design.. This is bad because it's quite old and
has some pretty dubious features - eg there are no smarts on the card as
such - they are all driven by a separate card in the rack, so there are
several effective clock signals :(
I have applied some basic timing constraints, and when looking at the
resulting timing diagrams it seems that there is plenty of time for the
data to be valid on the input side of the final FIFO before the write clock
is applied.
I am using Xilinx WebPack 8.2 with a Spartan 3.
Any hints where to look would be much appreciated.
--
Daniel O'Connor software and network engineer
for Genesis Software - http://www.gsoft.com.au
"The nice thing about standards is that there
are so many of them to choose from."
-- Andrew Tanenbaum
GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8C
Article: 106856Phil Tomson wrote: > I'm trying to use xc3sprog to program a XCF3s1500fg456 using a parallel > cable III. I get the following error: > > $ ./xc3sprog pci_7seg.bit > Release 0.5 > Cannot find device having IDCODE=05045093 > > I noticed the following line in devlist.txt: > > 05045093 8 XCF02S devlist.txt needs to be in the current working directory, unfortunately that is the only place it looks. I have thought about patching it to have a guess based on argv[0] but haven't actually got around to it yet. -- Daniel O'Connor software and network engineer for Genesis Software - http://www.gsoft.com.au "The nice thing about standards is that there are so many of them to choose from." -- Andrew Tanenbaum GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8CArticle: 106857
I get the same thing myself, I'm having to add the xco file and re-generate. I'm using 8.1 sp 3. Does anyone know if this is fixed in later versions, or have a better idea what's causing the problem? regards, Robin Gerhard Hoffmann wrote: > On Fri, 11 Aug 2006 17:25:59 +1000, Mark McDougall <markm@vl.com.au> wrote: > > >Hi, > > > >I'm tearing my hair out and I can't find the answer to this in any of > >the Xilinx solutions!!! > > > >---8<------8<------8<------8<------8<------8<------8<------8<------8<--- > >NgdBuild:604 - logical block 'pace_inst/U_Game/vram_inst' with type > >vram' could not be resolved. A pin name misspelling can cause this, a > >missing edif or ngc file, or the misspelling of a type name. Symbol > >'vram' is not supported in target 'spartan3'. > >---8<------8<------8<------8<------8<------8<------8<------8<------8<--- > > > >'vram' was generated with coregen and is a block memory. I copied the > >.NGC file to my project directory and associated it with the instance in > >the source tree. The VHDL file in which it is instantiated has a > >component entry for vram. > > I get this error if I do not import the vram.xco file into the project explicitely by hand. > Even though the core generator asks for the project and should know what is needed. > I think earlier versions than ISE 8.1.? worked without that, but I'm not sure. > (I use virtex4, Ise8.1.current_sp) > > > >I also notice during synthesis I get... > > > >WARNING:Xst:766 - line 453: Generating a Black Box for component <vram>. > > You can declare the black box yourself, then you get only 1999 warnings > instead of 2000. > > What annoys me more is self critic like "You use dirty and unsave coding tricks > like clock gating" that comes from inside the MicroBlaze and endless lists > of unconnected and removed signals from inside of automatically generated > FIR-filters or multipliers. > > Why can't ISE respect it when I explicitely write > > .... > carry_out => open, > .... > > It's not that I forgot to connect the pin. > Now use name mangling like > > carry_out => carry_out_unused678, > > and leave that unconnected. Then the false alarm is obvious at first glance. > > > regards, GerhardArticle: 106858
I am trying to meet an offset timing constraint, but I'm not sure I
understand the timing report. What's the deal with the long IOB FF to
PAD delay from Tiockp? It seems highly dependent on the DCM clock path
prior, so I'm not sure how to improve this...
Thanks,
-Brandon
<SNIP>
================================================================================
Timing constraint: COMP "S0_BPLK_OUT<1>" OFFSET = OUT 4 ns AFTER COMP
"DSP_CLK" HIGH;
1 item analyzed, 1 timing error detected.
Minimum allowable offset is 4.315ns.
--------------------------------------------------------------------------------
Slack: -0.315ns (requirement - (clock arrival + clock
path + data path + uncertainty))
Source: reg_data_2_1_1 (FF)
Destination: S0_BPLK_OUT<1> (PAD)
Source Clock: DSP_CLKi rising at 0.000ns
Requirement: 4.000ns
Data Path Delay: 4.686ns (Levels of Logic = 0)
Clock Path Delay: -0.371ns (Levels of Logic = 3)
Clock Uncertainty: 0.000ns
Timing Improvement Wizard
Clock Path: DSP_CLK to reg_data_2_1_1
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tiopi 0.723 DSP_CLK
dsp_clk_ibufg_ins
net (fanout=1) 0.798 DSP_CLKibufg
Tdcmino -5.744 dsp_clk_dcm_ins
net (fanout=1) 0.839 DSP_CLKubi
Tgi0o 0.589 dsp_clk_bufg_ins
net (fanout=414) 2.424 DSP_CLKi
---------------------------- ---------------------------
Total -0.371ns (-4.432ns logic, 4.061ns route)
Data Path: reg_data_2_1_1 to S0_BPLK_OUT<1>
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tiockp 4.686 reg_data_2_1_1
S0_BPLK_OUT_1_OBUF
S0_BPLK_OUT<1>
---------------------------- ---------------------------
Total 4.686ns (4.686ns logic, 0.000ns route)
(100.0% logic, 0.0% route)
--------------------------------------------------------------------------------
</SNIP>
Article: 106859Daniel O'Connor wrote: > Unfortunately while it works in a behavioural simulation, a PAR simulation > doesn't. I imagine I have used an incorrect construct somewhere so I am not > synthesising what I want, although the RTL diagram looks OK to me. > Many times this symptom is a result of a timing violation. Check that the setup time and the clock frequency as reported by the place and route timing report is being met by whatever simulation model you have driving the design. Also, check the list of warnings that pop out of the synthesis to look for things that you shouldn't try to do in an FPGA. If you find them, you'll probably need to get rid of them. Things like... - Transparent latches - Generating your own internal clocks (can be done, but only with care). - Other warnings that pop out should also be perused to make sure you understand why it is a warning and if this is a concern in your design. As with software, many times a compile time warning is a run time (or in your case timing simulation) error. > Strangely I find that the results are fine but the final FIFO is either not > clocking the data in properly, or not clocking it out properly.. > This might be a clue as to where timing is being violated. Since this was from an 'old' board I'm guessing that the FIFOs there were the garden variety async FIFOs. Hopefully inside the FPGA you didn't try to implement that but used a standard synchronous type instead. > However if I test it in isolation it works fine. When you're testing it in isolation though I'll bet that the timing in and out of the FIFO is not really the same as it is when inside the full FPGA. When testing in isolation, if you were to apply stimulus at the exact same time to this isolated FIFO it would not work in the same manner as you're seeing it not work for you now. If it is a synchronous FIFO then are the clocks free running or gated? If gated, then how that gating logic is implemented could be the problem (once again though, this is just a manifestation of a timing failure which can also be caught by full static timing analysis). > > I have applied some basic timing constraints, and when looking at the > resulting timing diagrams it seems that there is plenty of time for the > data to be valid on the input side of the final FIFO before the write clock > is applied. What about all the timing inside of the device though? What is the timing report telling you there? If there are multiple clocks involved then moving data from one clock domain to the other needs to be done properly. KJArticle: 106860
Maybe compiler has to be taken into account as well. Although very nice hand-made code is possible, most of code is generated by compiler. For a new instruction set, it's possible to modify gcc for that but I am not sure the efficiency. /Wayne Frank Buss wrote: > Jim Granville wrote: > > > A drawback of registers is that the step-up from reg to memory can give > > quite a code hit, and with FPGA BRAM, there is no speed penalty in a > > memory block much larger than most uC register fields. > > I wonder if there is some more scientific study about this. When I'm trying > to write a typical piece of code, it looks like registers are really > better: > > ; swap 6 byte source and destination MACs > .base = 0x1000 > p1: .dw 0 > p2: .dw 0 > tmp: .db 0 > move #5, p1 > move #11, p2 > loop: move.b (p1), tmp > move.b (p2), (p1) > move.b tmp, (p2) > sub.b p2, #1 > sub.b p1, #1 > bcc.b loop > > 40 bytes with my instruction set. > > The same with something like a 68000 instruction set: > > move #5, a0 > loop: move.b $0(a0), d0 > xchg.b $6(a0), d0 > move.b d0, $0(a0)- ; register indirect with displacement and post-dec > bcc.b loop > > 12 bytes, if I need 2 bytes per instruction for the larger range of > addressing modes with registers. How much logic gates do I need for > supporting registers? Maybe not too much, if I can design it without too > much special cases. > > I don't need it, but for a really fast CPU something like MIPS should work: > > http://www.mrc.uidaho.edu/mrc/people/jff/digital/MIPSir.html > > Every instruction, including arguments, is 32 bit. When reading it from 32 > bit block RAM, this should be really fast. How much memory needs a program? > > xor $1, $1, $1 > addi $1, $0, #6 > loop: lb $3, ($1) > sb $3, ($2) > addi $1, $1, #1 > addi $2, $2, #1 > xori $1, $4, #6 > bne loop > > 32 bytes (but maybe shorter, I don't know MIPS assembler very good). > > And something like the good old 6502: > > ldx# 6 > loop: lda 0, x > tay > lda 6, x > sta 0, x > tya > sta 6, x > decx > bcc loop > > 13 bytes. > > Maybe a CPU like MIPS, with fixed 32 bit instructions, but as easy to write > assembler for it like for the 68000 would be a good idea? > > Forth looks interesting, too: http://www.ultratechnology.com/f21cpu.html > > -- > Frank Buss, fb@frank-buss.de > http://www.frank-buss.de, http://www.it4-systems.deArticle: 106861
1) what family and speed grade, 2) what IOB Standard, and 3) what are your expectations and why? "Brandon Jasionowski" <killerhertz@gmail.com> wrote in message news:1156172416.044682.197320@i42g2000cwa.googlegroups.com... >I am trying to meet an offset timing constraint, but I'm not sure I > understand the timing report. What's the deal with the long IOB FF to > PAD delay from Tiockp? It seems highly dependent on the DCM clock path > prior, so I'm not sure how to improve this... > > Thanks, > -Brandon > > <SNIP> > ================================================================================ > Timing constraint: COMP "S0_BPLK_OUT<1>" OFFSET = OUT 4 ns AFTER COMP > "DSP_CLK" HIGH; > > 1 item analyzed, 1 timing error detected. > Minimum allowable offset is 4.315ns. > -------------------------------------------------------------------------------- > Slack: -0.315ns (requirement - (clock arrival + clock > path + data path + uncertainty)) > Source: reg_data_2_1_1 (FF) > Destination: S0_BPLK_OUT<1> (PAD) > Source Clock: DSP_CLKi rising at 0.000ns > Requirement: 4.000ns > Data Path Delay: 4.686ns (Levels of Logic = 0) > Clock Path Delay: -0.371ns (Levels of Logic = 3) > Clock Uncertainty: 0.000ns > Timing Improvement Wizard > Clock Path: DSP_CLK to reg_data_2_1_1 > Delay type Delay(ns) Logical Resource(s) > ---------------------------- ------------------- > Tiopi 0.723 DSP_CLK > dsp_clk_ibufg_ins > net (fanout=1) 0.798 DSP_CLKibufg > Tdcmino -5.744 dsp_clk_dcm_ins > net (fanout=1) 0.839 DSP_CLKubi > Tgi0o 0.589 dsp_clk_bufg_ins > net (fanout=414) 2.424 DSP_CLKi > ---------------------------- --------------------------- > Total -0.371ns (-4.432ns logic, 4.061ns route) > > Data Path: reg_data_2_1_1 to S0_BPLK_OUT<1> > Delay type Delay(ns) Logical Resource(s) > ---------------------------- ------------------- > Tiockp 4.686 reg_data_2_1_1 > S0_BPLK_OUT_1_OBUF > S0_BPLK_OUT<1> > ---------------------------- --------------------------- > Total 4.686ns (4.686ns logic, 0.000ns route) > (100.0% logic, 0.0% route) > > -------------------------------------------------------------------------------- > </SNIP> >Article: 106862
1) Virtex 2, -4 speed 2) There isn't an IOSTANDARD specified for the IO pins in the project UCF the board vendor supplied me with. What does this default to? Do I need to contact the vendor to ask them what the board can support? 3) I was told by the vendor this number would be appropriate to meet timing over the board traces to another FPGA I am also using. John_H wrote: > 1) what family and speed grade, > 2) what IOB Standard, and > 3) what are your expectations and why? > > > "Brandon Jasionowski" <killerhertz@gmail.com> wrote in message > news:1156172416.044682.197320@i42g2000cwa.googlegroups.com... > >I am trying to meet an offset timing constraint, but I'm not sure I > > understand the timing report. What's the deal with the long IOB FF to > > PAD delay from Tiockp? It seems highly dependent on the DCM clock path > > prior, so I'm not sure how to improve this... > > > > Thanks, > > -Brandon > > > > <SNIP> > > ================================================================================ > > Timing constraint: COMP "S0_BPLK_OUT<1>" OFFSET = OUT 4 ns AFTER COMP > > "DSP_CLK" HIGH; > > > > 1 item analyzed, 1 timing error detected. > > Minimum allowable offset is 4.315ns. > > -------------------------------------------------------------------------------- > > Slack: -0.315ns (requirement - (clock arrival + clock > > path + data path + uncertainty)) > > Source: reg_data_2_1_1 (FF) > > Destination: S0_BPLK_OUT<1> (PAD) > > Source Clock: DSP_CLKi rising at 0.000ns > > Requirement: 4.000ns > > Data Path Delay: 4.686ns (Levels of Logic = 0) > > Clock Path Delay: -0.371ns (Levels of Logic = 3) > > Clock Uncertainty: 0.000ns > > Timing Improvement Wizard > > Clock Path: DSP_CLK to reg_data_2_1_1 > > Delay type Delay(ns) Logical Resource(s) > > ---------------------------- ------------------- > > Tiopi 0.723 DSP_CLK > > dsp_clk_ibufg_ins > > net (fanout=1) 0.798 DSP_CLKibufg > > Tdcmino -5.744 dsp_clk_dcm_ins > > net (fanout=1) 0.839 DSP_CLKubi > > Tgi0o 0.589 dsp_clk_bufg_ins > > net (fanout=414) 2.424 DSP_CLKi > > ---------------------------- --------------------------- > > Total -0.371ns (-4.432ns logic, 4.061ns route) > > > > Data Path: reg_data_2_1_1 to S0_BPLK_OUT<1> > > Delay type Delay(ns) Logical Resource(s) > > ---------------------------- ------------------- > > Tiockp 4.686 reg_data_2_1_1 > > S0_BPLK_OUT_1_OBUF > > S0_BPLK_OUT<1> > > ---------------------------- --------------------------- > > Total 4.686ns (4.686ns logic, 0.000ns route) > > (100.0% logic, 0.0% route) > > > > -------------------------------------------------------------------------------- > > </SNIP> > >Article: 106863
For LVTTL (12mA) - the default for no IOB - the Tiockp is 2144 ps according to the speedprint utility. An extra 2626 ps is needed for the "slow" outputs for a total Tiockp of 4870 ps which is closer to your 4689 value but not precise. Specifying FAST constraints on the outputs should help out significantly. Take a look at the IOB Properties in the ISE GUI's Design Overview section. There you'll have a list of the I/Os, the standards, drive strengths, and slew rates specified. Tweak those values with Xilinx User Constraints and you should get your timing. The different parameters you see - values other than LVTTL, 12 mA, slow - or the version of tools you're running should be responsible for the difference I noted above. - John_H "Brandon Jasionowski" <killerhertz@gmail.com> wrote in message news:1156175827.967303.291440@74g2000cwt.googlegroups.com... > 1) Virtex 2, -4 speed > 2) There isn't an IOSTANDARD specified for the IO pins in the project > UCF the board vendor supplied me with. What does this default to? Do I > need to contact the vendor to ask them what the board can support? > 3) I was told by the vendor this number would be appropriate to meet > timing over the board traces to another FPGA I am also using. > > John_H wrote: >> 1) what family and speed grade, >> 2) what IOB Standard, and >> 3) what are your expectations and why? >> >> >> "Brandon Jasionowski" <killerhertz@gmail.com> wrote in message >> news:1156172416.044682.197320@i42g2000cwa.googlegroups.com... >> >I am trying to meet an offset timing constraint, but I'm not sure I >> > understand the timing report. What's the deal with the long IOB FF to >> > PAD delay from Tiockp? It seems highly dependent on the DCM clock path >> > prior, so I'm not sure how to improve this... >> > >> > Thanks, >> > -Brandon >> > >> > <SNIP> >> > ================================================================================ >> > Timing constraint: COMP "S0_BPLK_OUT<1>" OFFSET = OUT 4 ns AFTER COMP >> > "DSP_CLK" HIGH; >> > >> > 1 item analyzed, 1 timing error detected. >> > Minimum allowable offset is 4.315ns. >> > -------------------------------------------------------------------------------- >> > Slack: -0.315ns (requirement - (clock arrival + clock >> > path + data path + uncertainty)) >> > Source: reg_data_2_1_1 (FF) >> > Destination: S0_BPLK_OUT<1> (PAD) >> > Source Clock: DSP_CLKi rising at 0.000ns >> > Requirement: 4.000ns >> > Data Path Delay: 4.686ns (Levels of Logic = 0) >> > Clock Path Delay: -0.371ns (Levels of Logic = 3) >> > Clock Uncertainty: 0.000ns >> > Timing Improvement Wizard >> > Clock Path: DSP_CLK to reg_data_2_1_1 >> > Delay type Delay(ns) Logical Resource(s) >> > ---------------------------- ------------------- >> > Tiopi 0.723 DSP_CLK >> > dsp_clk_ibufg_ins >> > net (fanout=1) 0.798 DSP_CLKibufg >> > Tdcmino -5.744 dsp_clk_dcm_ins >> > net (fanout=1) 0.839 DSP_CLKubi >> > Tgi0o 0.589 dsp_clk_bufg_ins >> > net (fanout=414) 2.424 DSP_CLKi >> > ---------------------------- --------------------------- >> > Total -0.371ns (-4.432ns logic, 4.061ns route) >> > >> > Data Path: reg_data_2_1_1 to S0_BPLK_OUT<1> >> > Delay type Delay(ns) Logical Resource(s) >> > ---------------------------- ------------------- >> > Tiockp 4.686 reg_data_2_1_1 >> > S0_BPLK_OUT_1_OBUF >> > S0_BPLK_OUT<1> >> > ---------------------------- --------------------------- >> > Total 4.686ns (4.686ns logic, 0.000ns route) >> > (100.0% logic, 0.0% route) >> > >> > -------------------------------------------------------------------------------- >> > </SNIP> >> > >Article: 106864
PeteS wrote: > Do you want a processor you can simply instantiate, or are you willing > to tweak so you get the features you want? If so, you could take one of > the less ambitious cores and adjust the instruction set to optimise it > for your application. Adjusting the instruction set to the problem domain is a good idea. I'll try to write the functions, first, maybe using domain specific instructions (like a block copy command), and then I'll implement the core for it. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 106865
In article <12eje62m9q1o4b4@corp.supernews.com>, Daniel O'Connor <darius@dons.net.au> wrote: >Phil Tomson wrote: >> I'm trying to use xc3sprog to program a XCF3s1500fg456 using a parallel >> cable III. I get the following error: >> >> $ ./xc3sprog pci_7seg.bit >> Release 0.5 >> Cannot find device having IDCODE=05045093 >> >> I noticed the following line in devlist.txt: >> >> 05045093 8 XCF02S > >devlist.txt needs to be in the current working directory, unfortunately that >is the only place it looks. > Yes, I noticed that. I ran it from the same directory as devlist.txt. It almost seems like the wrong number is listed for that device in the devlist.txt. It says it can't find a device having IDCODE=05045093 and that's the IDCODE for XCF02S not the XCF3s1500. I tried swapping them in the devlist.txt, but that didn't work either. PhilArticle: 106866
Has anyone hooked in a DDR controller into OpenRISC? Anyone have any comments or suggestions for this task? I have OpenRISC in a running state with onchip RAM on a XUPV2P board, and now am just getting into integrating in an external DDR RAM controller. ThanksArticle: 106867
>> > If you use Modelsim's project file you can simply right click and select > 'Compile->Out of Date'. If not, then you need to use make. > I'm using PE 5.8e and I just call VCOM from my editor to recompile the one file I have edited, restart and ModelSim picks up the change just fine. You see it saying "# Loading work.whatever" /MikeJArticle: 106868
Hi JK, <krishna.janumanchi@gmail.com> wrote in message news:1156152360.053695.23550@75g2000cwc.googlegroups.com... > Hi, > > I use Modelsim SE 6.0 simulator for my projects. Update to 6.1f if you can, 6.0 has some annoying GUI bugs. > My Project is very big and it takes nearly 15 min for compilation. > As the license is network one, after compilation, it says simulation > license error - if license is not available. Is there a command > available in modelsim to check license on network? Sound like a network issue, you can issue "lmstat -f" to see how many Modelsim licenses are available, perhaps they are all used? Under windows (Dosbox/Cygwin) you need to change the command to "lmutil lmstat -f". > Next, In my project only 3 to 4 files are changed frequently. Rest > other files are not disturbed at all. > But still I am recompiling all files. Are there any commands available > so that I can skip compiling files which are not changed at all? Yes, look in the manual for the vmake command. Hans www.ht-lab.com > > Please help.. > > Regards, > JK >Article: 106869
http://www.xilinx.com/ise/embedded/edk82i_whatsnew.htm EDK 8.2 SP1 is also available AnttiArticle: 106870
Antti wrote: > Peter Alfke schrieb: > > > Why not use PicoBlaze, which is freely available ? > > Or MicroBlaze if you need more speed? > > Peter Alfke, from home. > > > > > > Frank Buss wrote: > > > For implementing the higher level protocols for my Spartan 3E starter kit > > > TCP/IP stack implementation, I plan to use a CPU, because I think this > > > needs less gates than in pure VHDL. The instruction set could be limited, > > > because more instructions and less gates is good, and it doesn't need to be > > > fast, so I can design a very orthogonal CPU, which maybe needs even less > > > gates. The first draft: > > > > > > http://www.frank-buss.de/vhdl/cpu.html > > > > > > It is some kind of a 68000 clone, but much easier. What do you think of it? > > > Any ideas to reduce the instruction set even more, without the drawback to > > > need more instructions for a given task? > > > > > > -- > > > Frank Buss, fb@frank-buss.de > > > http://www.frank-buss.de, http://www.it4-systems.de > > To Peter, > > I can answer > > 1) PicoBlaze is too small > 2) MicroBlaze is not free > > 1) PicoBlaze is too small > 2) MicroBlaze is not free Then perhaps there should be a "NanoBlaze"? ;) (micro, nano, pico) > the OP is really going to try to make a full SoC with DDR memory > controller and ethernet! as much as I have understood his reasons. > > sure it would be WAY CHEAPER to just use MicroBlaze !!! cheaper means > in terms of money. The time and effort to make anything comparable to > what you can achive with EDK and a few mouseclicks, defenetly costs > more than 495USD unless your personal time doesnt count at all. > > To Frank, > > I was wondering (what you are up) > > well doing some 16 bit doesnt make much sense, a small 32 bit RISC isnt > much larger. you could also use OpenFire and add wishbone interfaces, > makes more sense then trying it all from scratch. unless you just want > todo everything by yourself (and that is your goal, not achiving the > best with least effort) > > BTW - 16 bit, I was looking at ColdFire, and well there is no coldfire > FPGA clone yet, but that may make sense (kind 68000, but more RISClike, > 16 bit instruction bus) > > > Antti -Dave PollumArticle: 106871
Dave Pollum schrieb: > Antti wrote: > > Peter Alfke schrieb: > > > > > Why not use PicoBlaze, which is freely available ? > > > Or MicroBlaze if you need more speed? > > > Peter Alfke, from home. > > > [] > Then perhaps there should be a "NanoBlaze"? ;) > (micro, nano, pico) > -Dave Pollum Dave, NanoBlaze is already (R) registered trademark of Xilinx Inc. AnttiArticle: 106872
Hi Has anyone experience with prgramming a serial prom/flash like the EPCS16 using a 8051 compatible uP. It looks like srunner C code from Altera has some some useable rutines but a 8051 device driver and file driver is needed. Hi PeterArticle: 106873
Antti wrote: > Dave Pollum schrieb: > >> Antti wrote: >>> Peter Alfke schrieb: >>> >>>> Why not use PicoBlaze, which is freely available ? >>>> Or MicroBlaze if you need more speed? >>>> Peter Alfke, from home. >>>> > [] >> Then perhaps there should be a "NanoBlaze"? ;) >> (micro, nano, pico) > >> -Dave Pollum > > Dave, > > NanoBlaze is already (R) registered trademark of Xilinx Inc. > > Antti > Damn, I'm working on a 16 bits RISC cpu optimized for S3/V4 and I was thinking of nanoblaze ... gotta find some other name now ... SylvainArticle: 106874
Sylvain Munaut wrote: > Antti wrote: > >>Dave Pollum schrieb: >> >> >>>Antti wrote: >>> >>>>Peter Alfke schrieb: >>>> >>>> >>>>>Why not use PicoBlaze, which is freely available ? >>>>>Or MicroBlaze if you need more speed? >>>>>Peter Alfke, from home. >>>>> >> >>[] >> >>>Then perhaps there should be a "NanoBlaze"? ;) >>>(micro, nano, pico) >> >>>-Dave Pollum >> >>Dave, >> >>NanoBlaze is already (R) registered trademark of Xilinx Inc. >> >>Antti >> > > > Damn, I'm working on a 16 bits RISC cpu optimized for S3/V4 > and I was thinking of nanoblaze ... gotta find some other name > now ... If it is going to be open source, how about NanoFire ? -jg
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