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On Oct 10, 12:46 pm, Philipp Klaus Krause <p...@spth.de> wrote: > ruby...@gmail.com schrieb: > > > It seems that the launchbird site has disappeared. I had heard that > > Confluence was superceded by HDCaml, but it looks like that site is > > dead as well. I'm currently learning OCaml and would like to play > > with HDCaml - anyone know if the source code is still available? > > Confluence is to be replaced by Atom, a Haskell-based HDL. > > Philipp When you say "replaced by Atom" what exactly does that mean? I would assume that the source code to HDCaml (and confluence) still exists - if the author of those has moved on to Atom, is it still possible to obtain the source for HDCaml? Also, if the Confluence/HDCaml author has moved on to Atom (and thus away from OCaml ) it would be interesting to find out why - anyone know? philArticle: 124926
"Duane Clark" <junkmail@junkmail.com> wrote news:SC9Pi.2128$lE2.2099@newssvr22.news.prodigy.net... > DoVHDL wrote: >> I'm using Xilinx ISE WebPack for my design. I have 4 ADC interface >> entities that operaates on a 80MHz clk that I'm creating from an external >> 20MHz clock with a DCM. The calculation part (having a MAC-operation) >> must run on a 40MHz clock (divided from the 80MHz clock). > > Are you going to have a separate clock domain clocked at 40MHz? Then you > put a 25nS period constraint on the entire domain, not an entity. The same > kind of constraint as on your 80MHz clock. But how are you handling > getting data across the domain boundaries? That can be tricky. > > Or are you going to clock everything at 80MHz, but have an enable in your > "calculation part" that toggles, effectively operating it at 40MHz? This > would be a better idea. You would apply a multicycle constraint, but that > also can be a tricky thing to get right. > > But the best thing to do would be to figure out why your MAC cannot > operate at 80MHz, and fix it. How you do that depends somewhat on what > device you are using. Are you using a device with builtin hardware > multipliers? Then the first step would be to look in the project.syr file, > and look for the word "pipeline". Look down through that section and see > if there is something like: > INFO:Xst:2385 - HDL ADVISOR - You can improve the performance of the > multiplier Mmult__mult0004 by adding 1 register level(s). > If so, you probably just need to pipeline your multipliers more. Make sure > to go through the file and find all instances of the word "pipeline". When the ADC-interface has a sample ready it signals this by setting a signal high for two 80MHz clk cycles. The calculator enity operates at 40MHz from the divided 80MHz clock. The clock division is simply made vith a t flip-flop in an entity. The ADC-interface entity must be clocked at 80MHz to be able to sample at a specific rate. And the calculations (an IIR filter from an older design) only rund at max 50MHz (so i want to run it stable at 40MHz). So i would like to make sure that it meets that timing constraint. I like to design with a top schematic where I connect all sub entities. Is there a way to insert the timing constraints in the schematic?Article: 124927
Ron N. wrote: > Which vendor's FPGA development and USB download tools have > people found to work reliably on a Mac or MacBook under either the > Parallels or VMware virtualizers, running Windows XP, 2k or linux? > If so, which virtualization environments worked with which USB > FPGA download cables? How much memory was needed? I've been running both Xilinx Foundation and old Ise versions under VMware for years. I haven't popped for the later Ise versions, but no reason they shouldn't work, too. VMware is a VERY good product. I use it under Linux on PCs, and the serial and parallel cable III both work fine. I don't have a USB download cable. JonArticle: 124928
Which vendor's FPGA development and USB download tools have people found to work reliably on a Mac or MacBook under either the Parallels or VMware virtualizers, running Windows XP, 2k or linux? If so, which virtualization environments worked with which USB FPGA download cables? How much memory was needed? Thanks, rhn A.T nicholson d.0.t C-o-M (IMHO & speaking only for myself)Article: 124929
Phil Tomson schrieb: > I would > assume that the source code to HDCaml (and confluence) still exists - > if the author of those has moved on to Atom, is it still possible to > obtain the source for HDCaml? Confluence, HDCaml and Atom sources can be found at http://funhdl.org/download/ PhilippArticle: 124930
Phil Tomson schrieb: > Also, if the Confluence/HDCaml author has moved on to Atom (and thus > away from OCaml ) it would be interesting to find out why - anyone > know? He mentioned Inspiration by work from Prof. Arvind at MIT. PhilippArticle: 124931
DoVHDL wrote: > > When the ADC-interface has a sample ready it signals this by setting a > signal high for two 80MHz clk cycles. The calculator enity operates at 40MHz > from the divided 80MHz clock. The clock division is simply made vith a t > flip-flop in an entity. After it goes through the flip flop, it had better go through a global clock buffer, or your circuit is almost gauranteed not to work. > > The ADC-interface entity must be clocked at 80MHz to be able to sample at a > specific rate. And the calculations (an IIR filter from an older design) > only rund at max 50MHz (so i want to run it stable at 40MHz). So i would > like to make sure that it meets that timing constraint. You seem to think attaching a timing constraint to the 40MHz piece will magically make your circuit work right. But it sounds like you have data crossing between the 80MHz domain and the 40MHz domain. If you simply allow the data to cross between them, it is likely your circuit will be flaky at best. So again, I will repeat. How are you handling getting data across the domain boundaries? I think you really do want to fix your IIR to run at 80MHz; that will insure your circuit works right the first time, and every time. Oh, and why are you using schematics ;)Article: 124932
On Oct 10, 2:27 pm, Jon Elson <el...@wustl.edu> wrote: > Ron N. wrote: > > Which vendor's FPGA development and USB download tools have > > people found to work reliably on a Mac or MacBook under either the > > Parallels or VMware virtualizers, running Windows XP, 2k or linux? > > If so, which virtualization environments worked with which USB > > FPGA download cables? How much memory was needed? > > I've been running both Xilinx Foundation and old Ise versions under VMware > for years. I haven't popped for the later Ise versions, but no reason > they shouldn't work, too. VMware is a VERY good product. I use it > under Linux on PCs, and the serial and parallel cable III both work > fine. I don't have a USB download cable. Current Mac's (and many Wintel laptops) don't have serial or parallel ports; so I'm most interested in whether either VMware or Parallels on a MacBook works with, or has problems with, the USB download cables that one would get with the various FPGA vendors development kits. (e.g. I don't want to buy an FPGA dev kit, and find out I can't use it with any of my personal computers or laptops.) Thanks, rhn A.T nicholson d.0.t C-o-M (IMHO & speaking only for myself)Article: 124933
Hi all, I've got a design that can be built in 2 different configurations, controlled via a VHDL constant / if-generate in a sub-module. Each configuration uses a particular set of I/O pins and leaves the others dangling. The Xilinx tools won't let me generate a bit file for this design. ERROR:PhysDesignRules:10 - The network <B_MEMCS16_N_OBUF> is completely unrouted. I've tried tri-stating the unused I/O pins (pin <= 'Z') but the problem persists. I can't drive 0 or 1 because they're effectively open-collector. Is there any way I can circumvent this error? Turn if off? Or fool it? BTW it's perhaps complicated by the fact that I inherited this design - the top level is a massive schematic and it is built using Altium's DXP. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 124934
On 11 Okt, 00:17, "Ron N." <rhnlo...@yahoo.com> wrote: > Which vendor's FPGA development and USB download tools have > people found to work reliably on a Mac or MacBook under either the > Parallels or VMware virtualizers, running Windows XP, 2k or linux? > If so, which virtualization environments worked with which USB > FPGA download cables? How much memory was needed? > > Thanks, > > rhn A.T nicholson d.0.t C-o-M > (IMHO & speaking only for myself) I have been using Xilinx FPGA tools (ISE and EDK) running on my MacBook using VMware Fusion and Ubuntu Linux. I works perfectly fine. See my blog : http://www.fpgafromscratch.com The only problem I had was the USB driver. This is how I fixed it. http://svenand.blogdrive.com/archive/55.html SvenArticle: 124935
When changing the order of 8bit words (integer) into the encoder from a)...236 - 237 - 238 - 239... to b)...236 - 8 - 238 ... (encoded word of 8 has negative disparity) the error detection module does not show an error for the 0x1C7 (encoded word of 238). The question is how to find the error in the encoder description ... Rgds AndreArticle: 124936
> But in the debug symbols what is the deffierence between symbols for > debugging (-g)and symbols for assembly(-gstabs). ? Probably the standard used for the debug info (stabs / dwarf). > And for inline > assembly what is the best settings? I would use -g3. Not sure if you're going to get any debug info for inline assembly though. What are you expecting? Cheers, JonArticle: 124937
<dan.walmsley@gmail.com> wrote in message news:1192004800.613653.202520@y42g2000hsy.googlegroups.com... >I need to find a cheap UK supplier for a spartan 3 development kit, > prepherably USB, it needs to be suitable to implement a small softcore > processor and ideal for someone with no previous experience. > > I can find lots of products in the US but none in the UK. > > Dan Walmsley > Hi Dan, What's wrong with US products? Those yanks have invented a thing called FedEx. Perhaps you've heard of it? Using one of their other inventions, Visa and Mastercard, along with one some British bloke invented, the WWW, getting stuff from the US is much quicker than getting UK stuff via Royal Mail. Because the bastards are on strike. HTH, Syms. p.s. My tongue is in my cheek! Although, I would say that getting the right product is much more important than where it ships from.Article: 124938
On Thu, 11 Oct 2007 10:57:46 +0100, "Symon" <symon_brewer@hotmail.com> wrote: ><dan.walmsley@gmail.com> wrote in message >news:1192004800.613653.202520@y42g2000hsy.googlegroups.com... >>I need to find a cheap UK supplier for a spartan 3 development kit, >> prepherably USB, it needs to be suitable to implement a small softcore >> processor and ideal for someone with no previous experience. >> >> I can find lots of products in the US but none in the UK. >> >> Dan Walmsley >> >Hi Dan, >What's wrong with US products? > >Those yanks have invented a thing called FedEx. Perhaps you've heard of it? >Using one of their other inventions, Visa and Mastercard, along with one >some British bloke invented, the WWW, getting stuff from the US is much >quicker than getting UK stuff via Royal Mail. Because the bastards are on >strike. >HTH, Syms. Problem is it can cost a fortune - not just the shipping cost, but the excessive brokerage/handling fees these carriers often charge. Unfortunately rather few US companies will ship by the much more reasonably priced USPS Incidentally, parcels sent by USPS come via Parcel Force, who are not on strike.Article: 124939
"Mike Harrison" <mike@whitewing.co.uk> wrote in message news:i80sg3lhien41bd2td311a760v8heha65d@4ax.com... > On Thu, 11 Oct 2007 10:57:46 +0100, "Symon" <symon_brewer@hotmail.com> > wrote: >>Hi Dan, >>What's wrong with US products? >> >>Those yanks have invented a thing called FedEx. Perhaps you've heard of >>it? >>Using one of their other inventions, Visa and Mastercard, along with one >>some British bloke invented, the WWW, getting stuff from the US is much >>quicker than getting UK stuff via Royal Mail. Because the bastards are on >>strike. >>HTH, Syms. > > Problem is it can cost a fortune - not just the shipping cost, but the > excessive brokerage/handling > fees these carriers often charge. > Unfortunately rather few US companies will ship by the much more > reasonably priced USPS > Incidentally, parcels sent by USPS come via Parcel Force, who are not on > strike. > Hi Mike, True enough! My serious point, although hidden by the sarcasm, is it's often worth shelling out up front to get what you really want, rather than saving a few quid on something that might end up taking a while to adapt. YMMV, Syms. p.s. Thanks for the heads up on Parcel Force; I can see this postal strike thing dragging on for months.Article: 124940
On Thu, 11 Oct 2007 12:30:30 +0100, "Symon" <symon_brewer@hotmail.com> wrote: >"Mike Harrison" <mike@whitewing.co.uk> wrote in message >news:i80sg3lhien41bd2td311a760v8heha65d@4ax.com... >> On Thu, 11 Oct 2007 10:57:46 +0100, "Symon" <symon_brewer@hotmail.com> >> wrote: >>>Hi Dan, >>>What's wrong with US products? >>> >>>Those yanks have invented a thing called FedEx. Perhaps you've heard of >>>it? >>>Using one of their other inventions, Visa and Mastercard, along with one >>>some British bloke invented, the WWW, getting stuff from the US is much >>>quicker than getting UK stuff via Royal Mail. Because the bastards are on >>>strike. >>>HTH, Syms. >> >> Problem is it can cost a fortune - not just the shipping cost, but the >> excessive brokerage/handling >> fees these carriers often charge. >> Unfortunately rather few US companies will ship by the much more >> reasonably priced USPS >> Incidentally, parcels sent by USPS come via Parcel Force, who are not on >> strike. >> >Hi Mike, >True enough! My serious point, although hidden by the sarcasm, is it's often >worth shelling out up front to get what you really want, rather than saving >a few quid on something that might end up taking a while to adapt. >YMMV, Syms. >p.s. Thanks for the heads up on Parcel Force; I can see this postal strike >thing dragging on for months. One word of warning - when they receive a parcel with charges to pay, they hold at the depot and send a note in the post (or sometimes forget to...) - make sure you get a tracking# from the sender so you know when it arrives...Article: 124941
On Oct 10, 3:59 pm, Duane Clark <junkm...@junkmail.com> wrote: > DoVHDL wrote: > > > When the ADC-interface has a sample ready it signals this by setting a > > signal high for two 80MHz clk cycles. The calculator enity operates at 40MHz > > from the divided 80MHz clock. The clock division is simply made vith a t > > flip-flop in an entity. > > After it goes through the flip flop, it had better go through a global > clock buffer, or your circuit is almost gauranteed not to work. > > > > > The ADC-interface entity must be clocked at 80MHz to be able to sample at a > > specific rate. And the calculations (an IIR filter from an older design) > > only rund at max 50MHz (so i want to run it stable at 40MHz). So i would > > like to make sure that it meets that timing constraint. > > You seem to think attaching a timing constraint to the 40MHz piece will > magically make your circuit work right. But it sounds like you have data > crossing between the 80MHz domain and the 40MHz domain. If you simply > allow the data to cross between them, it is likely your circuit will be > flaky at best. So again, I will repeat. How are you handling getting > data across the domain boundaries? > > I think you really do want to fix your IIR to run at 80MHz; that will > insure your circuit works right the first time, and every time. > > Oh, and why are you using schematics ;) There may be other issues with you design, but to solve your immediate problem you can declare the 40MHz clock a separate clock/timing group.Article: 124942
Jim Granville wrote: > Noway2 wrote: > >> Group, >> >> I have the need to copy a Max 7000s device that was originally >> developed under Max+Plus II. I am not able to locate the original >> project file (my bad) but I do have a working device that I can copy >> from. Originally the device was programmed under Max+Plus II using a >> byteblaster cable, but today I only have a USB blaster. >> >> My problem appears to be a double whammy: that Max+Plus II does not >> seem to support the USB Blaster and Quartus does not support the >> Examine feature for 7000S devices (according to what I discovered in a >> search of this group). > > > Both pathways must have a means to verify a device. > The question you need to ask, is "has the device you have been secured?" > >> I am presenlty at a loss for ideas. > > > Surely not ? > > Idea #1 : Find/Build a cable that MAX+II does support > Idea #2 : Look harder for the source file(s) > >> >> If anyone has any suggestions of how I could copy this device, I would >> greatly appreciate your help. > > > -jg > JG, Thank you for the suggestion. It turns out that building an old style programmer would be pretty easy. As I am still unable to locate the original design files, I am likely going to go that route. From laurent.pinchart@skynet.be Thu Oct 11 07:59:32 2007 Path: newssvr11.news.prodigy.net!newsdbm04.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin1!goblin.stu.neva.ru!feeder.news-service.com!news.astraweb.com!border2.a.newsrouter.astraweb.com!hwmnpeer01.ams!news.highwinds-media.com!kramikske.telenet-ops.be!nntp.telenet.be!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Message-Id: <470e3a54$0$22310$ba620e4c@news.skynet.be> From: Laurent Pinchart <laurent.pinchart@skynet.be> Subject: Re: [ANN] FPGAOptim - Do you know where your slices are going...? Newsgroups: comp.arch.fpga Date: Thu, 11 Oct 2007 16:59:32 +0200 References: <u3ax4p5ka.fsf@trw.com> <ubqb9oql8.fsf@trw.com> <470a0fc5$0$22313$ba620e4c@news.skynet.be> <uk5pxvh1m.fsf@trw.com> User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 26 Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 7c6a26fd.news.skynet.be X-Trace: 1192114772 news.skynet.be 22310 194.78.198.49:59061 X-Complaints-To: usenet-abuse@skynet.be Xref: prodigy.net comp.arch.fpga:136923 Hi Martin, Martin Thompson wrote: > Laurent Pinchart <laurent.pinchart@skynet.be> writes: >>> Martin Thompson <martin.j.thompson@trw.com> writes: >>> >>> Anyone who downloaded this utility and is experiencing crashes on >>> large designs, please download a new installer from the same location, >>> or send me a mail if you need the link again. I've fixed a bug which >>> was crashing the tree viewer - sorry about that! >> >> Any plan for an open-source Linux version ? > > There may be a Linux version, you are the third person to ask (four > including me). > > There are no plans to open-source it though - would that matter to people? I think it would, yes. That kind of niche product is obviously useful for a very limited set of people, and the ability to fine-tune the software and add very specific functionalities then matters. Cheers, Laurent PinchartArticle: 124943
fpgabuilder wrote: > > There may be other issues with you design, but to solve your immediate > problem you can declare the 40MHz clock a separate clock/timing group. > Yes, that is what I said in my first post in this thread ;)Article: 124944
I just got an email from Altera, saying:
ear Altera Customer,
The new Quartus® II Web Edition Software version 7.2 is now available
for download.
New features include:
[...blah...]
* Get complete OS support for Linux in addition to 64-bit Windows
Vista
However, on the download page they still have:
For Solaris or Linux support, purchase an Altera software subscription.
Anyone knows what the deal is?
-hpa
Article: 124945H. Peter Anvin wrote: > However, on the download page they still have: > For Solaris or Linux support, purchase an Altera software subscription. > Anyone knows what the deal is? Last I checked, the web edition is windows only with no rtl viewer and no oem modelsim. -- Mike TreselerArticle: 124946
I could run all the latest Xilinx tools (EDK / ISE / Chipscope) without any problem on Windows XP with VMWare Fusion on my MAC.. -- parag On Oct 10, 8:58 pm, "Ron N." <rhnlo...@yahoo.com> wrote: > On Oct 10, 2:27 pm, Jon Elson <el...@wustl.edu> wrote: > > > Ron N. wrote: > > > Which vendor's FPGA development and USB download tools have > > > people found to work reliably on a Mac or MacBook under either the > > > Parallels or VMware virtualizers, running Windows XP, 2k or linux? > > > If so, which virtualization environments worked with which USB > > > FPGA download cables? How much memory was needed? > > > I've been running both Xilinx Foundation and old Ise versions under VMware > > for years. I haven't popped for the later Ise versions, but no reason > > they shouldn't work, too. VMware is a VERY good product. I use it > > under Linux on PCs, and the serial and parallel cable III both work > > fine. I don't have a USB download cable. > > Current Mac's (and many Wintel laptops) don't have serial > or parallel ports; so I'm most interested in whether either > VMware or Parallels on a MacBook works with, or has problems > with, the USB download cables that one would get with the > various FPGA vendors development kits. (e.g. I don't want > to buy an FPGA dev kit, and find out I can't use it with > any of my personal computers or laptops.) > > Thanks, > > rhn A.T nicholson d.0.t C-o-M > (IMHO & speaking only for myself)Article: 124947
I am not sure if Xilinx's KEEP attribute might help or not.. Please check the Xilinx's constraints Guide, may be that might help you. #################################################### Eg: in UCF -- NET "xyz" KEEP; #################################################### -- parag On Oct 10, 11:18 pm, Mark McDougall <ma...@vl.com.au> wrote: > Hi all, > > I've got a design that can be built in 2 different configurations, > controlled via a VHDL constant / if-generate in a sub-module. Each > configuration uses a particular set of I/O pins and leaves the others > dangling. The Xilinx tools won't let me generate a bit file for this design. > > ERROR:PhysDesignRules:10 - The network <B_MEMCS16_N_OBUF> is completely > unrouted. > > I've tried tri-stating the unused I/O pins (pin <= 'Z') but the problem > persists. I can't drive 0 or 1 because they're effectively open-collector. > > Is there any way I can circumvent this error? Turn if off? Or fool it? > > BTW it's perhaps complicated by the fact that I inherited this design - > the top level is a massive schematic and it is built using Altium's DXP. > > Regards, > > -- > Mark McDougall, Engineer > Virtual Logic Pty Ltd, <http://www.vl.com.au> > 21-25 King St, Rockdale, 2216 > Ph: +612-9599-3255 Fax: +612-9599-3266Article: 124948
As I understand it: 1st byte - always K28.5- - ordered set delimiter & character sync 2nd byte - function code - differentiate SOF/R_RDY/etc types 3rd byte - Straighten out disparity to RD+ 4th byte - Reverses disparity to RD- This is not based on any particular source, only my observations, so I could be completely wrong. ken Walters wrote: > Would some one know why SOF/EOF of Fiber Channel frame is 4 bytes? > > Thanks > Walters >Article: 124949
Hi all, We are building a very simple SOC ( PPC 405, internal memory, UART light) in a V4FX60, with a very simple firmware. The point is that when we use the PLB_BRAM memory, the GDB debugger works fine, but wneh we use the OCM memories, the debugger behaves in astrange way. When we download the file then it goes in a assembly state and executes nothing, I guess it went in some exceptions or executed some unexpected instructions. Is there something to know to use the OCM memories ? Are there some configuration to make in EDK ? Thanks for your help. Stéphane.
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