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On Sep 26, 1:37 pm, Gabor <ga...@alacron.com> wrote: > On Sep 25, 6:48 pm, Wei Wang <camww...@gmail.com> wrote: > > > > > > > On Sep 25, 9:31 pm, Gabor <ga...@alacron.com> wrote: > > > > On Sep 25, 2:12 pm, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > > On Sep 25, 8:51 am, Wei Wang <camww...@gmail.com> wrote: > > > > > > All I can find is a one-page specification of "Kingston > > > > > KVR100X64C2/128", but I do not know about the input and output > > > > > interface of this SDRAM, e.g., what are the input and output signals, > > > > > and how the input and output signals are wired into each Synchronous > > > > > DRAM (Infineon HYB39S128800CT-8) module. Many thanks, -Wei > > > > > Hi, > > > > Go to Infineon or Micron, or Samsung to search for similar SDRAM > > > > chips. > > > > > Kingston is not a chip manufacture, but a DIMM manufacture. > > > > > All SDRAM chips are almost same with Micron having the tighest > > > > requirements. > > > > > You may print Micron 128800CT-8 SDRAM to see if there is a document > > > > over there. Maybe they are all out of date. > > > > > Weng > > > > A good source for DIMM data is JEDEC. On their website, jedec.org, > > > you > > > can find standard connections for all standard DIMM types. If you > > > know > > > the type of chip and number of chips on your module you can generally > > > narrow down the choices to one JEDEC standard. > > > > Their website is a little hard to navigate, but the search feature > > > generally gets you to the information you need, and all of the > > > standards > > > include reference schematics so you can see the chip connections. > > > > HTH, > > > Gabor- Hide quoted text - > > > > - Show quoted text - > > > Thanks Tianxiang and Gabor for your inputs, but I was a little > > confused with the description in Kingston KVR100X64C2/128 "The > > components on this module > > include sixteen 8M x 8-bit (2M x 8-bit x 4 Bank / PC100 components) > > SDRAM in TSOP packages", but when I look at Infineon HYB39S128800CT-8, > > the chip has four banks inside, > > each bank is 8 bits wide with 4M address, so each chip is 4Mx8bitx4, > > which is 16MB. As the Kingston is 128 MB big and it has 8 Infineon > > chips fitted, so I don't see why the KVR specification says the module > > contains sixteeen 8Mx8-bit SDRAM. Should it be 8 16Mx8-bit SDRAM, then > > I could not find this in JEDEC standard while I could find the JEDEC > > standard for sixteen 8Mx8bit? Could somebody give me some hints on > > this, thanks!!! > > The data sheet also notes: > > "Note: The module defined in this data sheet is one of several > configurations available under this part number. While all > configurations are compatible, the DRAM combination and/or the > module height may vary from what is described here." > > I'm not sure what they consider "compatible" in the case of modules > with different memory organizations under the same part number, > but I also noticed that they offer "Free Technical Support". > > Perhaps someone at Kingston can address the issue? > > Regards, > Gabor- Hide quoted text - > > - Show quoted text - Many thanks again for your input, I've called Kingston US support line yesterday, but I was told that they could not provide anything in more detail beyond the one-page specification found on their website. I've however managed to find something very similar, such as the Samsung KMM366S1723T datasheet which provides a better view of chip organization.Article: 124551
Hi KS, Good comments and I think it is based on good and reasonable judgement. I really appreciate the following comment: You are extraordinarily stubborn. It is one of my personal characteristics. I really throw away all trashes into my backyard garbage bin in the topics. I will think a few days to give you a satisfactory answer. WengArticle: 124552
"Andy Peters" <google@latke.net> wrote in message news:1190763448.554163.146770@57g2000hsv.googlegroups.com... > On Sep 25, 9:00 am, jinke...@hotmail.com wrote: >> On Sep 25, 6:51 am, cs_post...@hotmail.com wrote: >> >> >> >> > Ordered a license for Quartus a month ago. Order is processed, rep >> > says she needs NIC ID and host ID from PC, we explain that a new PC is >> > on order and we will need to license software to old machine now, then >> > move it. She says we have to wait. >> >> > Okay, not good as a project is already behind schedule, but can live >> > with that. >> >> > New computer comes in. Get rep to clarify that host ID means volume >> > serial number. Provide it. No response. Wait four days and ask what >> > happened - told that LICENSE CANNOT BE ISSUED FOR AT LEAST ANOTHER >> > FOUR DAYS. >> >> > What the ???? >> >> > I have work to do here, and you guys can't email me a tiny text file ? >> >> > Going back to Xilinx... project is already halfway working on their >> > eval board, which has a chip supported by their web version. >> >> Mike, >> >> Sorry to hear you had a bad experience. I would like to help now if I >> can. First, Quartus II Subscription Edition includes a free 30-day >> trial (no license needed - just download and install). This should get >> you up an running with compiling a 2S60. Second, our sales team should >> be able to cut you an additional 60-day evaluation license. I'm happy >> to do so now - just email me your NIC ID. I can also help you with >> license you purchased. >> >> Happy to get you up and runnning today. >> >> Jordon Inkeles >> Altera Software Marketing >> jinke...@altera-nospam-.com <remove the -nospam-> > > Somebody PLEASE explain to me why a license key is needed for software > that does one thing only: implement designs in the vendor's specific > logic family. > > I can't use Altera's software to do Xilinx chips, nor can I use it to > play Doom 3, nor can I use it to make my morning coffee. So why why > why why why do the FPGA vendors insist on license keys for their > tools? > > -a > SO that when the license expires .. they can ding you for another years worth of a new license.Article: 124553
AFAIK there are not good multi level optimization algorithms that take mapping effects into account. Instead logic optimization is done independently of mapping. Usually, first a technology independent multi level logic optimization is performed. (Based on transformations, ATPG or implications). There should be academic implementations for that around. Most of them quite old. Afterwards technology mapping is performed. Mapping for LUTs can be done delay optimal in polynomial time. (Flow map). For 6-LUT FPGAs it might make sense to combine mapping with retiming to balance the amount of logic between stages. There is a paper by Sunil Khatri on optimization for networks of PLAs. A 6-LUT might be large enough to benefit from that approach. (I doubt it) Kolja Sulimma On 25 Sep., 23:30, dudesinmex...@gmail.com wrote: > I am looking for open source software for logic minimization (a la > espresso) > targeted to a lookup table based architecture that can take advantage > of six > inputs LUTs (as you can imagine I have in mind a LUT6/Virtex 5 > implementation). > Is there such a beast? > > thanks much > > -ArrigoArticle: 124554
Altera claims to have a snazzy early power estimator that needs MXCOMCT2.OCX. I wonder if anyone has managed to get this solution to work? I spreadsheet works (did not have to use the fix) on my personal laptop but does not work (fix does not help) on my work machine. I downloaded the OCX file as instructed but that didn't help. So I filed a case with Altera Online Support. But those guys pretty much told me go and figure it out myself. I would reserve my gripes about the support in a raging debate going on in a separate thread about the price of the tools, support, etc. But I am more eager to make the spreadsheet work. So I would appreciate the help if anyone can share if and how they managed to get the fix to work. Thank you. Best regards, SanjayArticle: 124555
On Sep 25, 11:30 pm, "Sylvain Munaut <Some...@SomeDomain.com>" <246...@gmail.com> wrote: > Hi, > > > - Why are there 32 global clock lines for a chip? It seems quite a > > lot... > > Yes, this may seem high at first. And it's indeed unlikely a design > will > use all of them. But that's on purpose, so that it doesn't become a > limitation. > > In a real life design, the number of BUFG tends to grow quickly. > > Let's take a "simple" design where you receive a gigabit network flow, > store it in DDR2, do some processing an display the result on a DVI > screen : > > - The gigabit ethernet is gonna take you 3 BUFG, one for the RX > clock, one for the TX clock and one for your reference clock. > - The DDR2 controller can take up to 5 BUFG (clock 125 MHz, clock 250 > MHz, each one in phase 0 and in phase 90 + 1 BUFG for the IDELAY > 200MHz clock) ... > - The processing might be done at another higher frequency, so that's > another BUFG > - The DVI will also need it's BUFG. > > So you see I'm already at 10 BUFG with a not so complex design ... > > > - It states 8 global clock lines can be used in a single region, > > although why would you want 8 lines going into a single region? How > > does the region then know which clock signal to use? > > Each synchronous element in a region (FF, BRAM, ...) can choose > independently what clock to use from those 8 lines. > > > - If each region is running at a different clock speed, how is > > communication between regions (and so different clock speeds) handled? > > You can cross clock inside region too ... and when you need to cross > clock > domain, you need to be careful. Depending on what must cross, the > techniques > vary ... > > Sylvain Think of the resources published in the datasheet of an fpga as something that you have as your tools to achieve the design goals. So you may or may not use it. At times you may find that replicating the clocks can help the operating frequency by easing the loading on the clock tree and therefore you may be able to run the design faster. -sanjayArticle: 124556
"Symon" <symon_brewer@hotmail.com> wrote: >"Andy Peters" <google@latke.net> wrote in message >news:1190763448.554163.146770@57g2000hsv.googlegroups.com... >> >> I can't use Altera's software to do Xilinx chips, nor can I use it to >> play Doom 3, nor can I use it to make my morning coffee. So why why >> why why why do the FPGA vendors insist on license keys for their >> tools? >> >> -a >> >Hi Andy, >I guess economics? The FPGA company has to pay to develop their silicon and >to develop their software. As the customer, we have to pay for both of >these, one way or another. If they gave the software away, they'd have to >charge more for the devices. This would be unfair to customers that use a >lot of devices in their products over customers that use fewer parts. >HTH., Syms. Not really. Big customers get big discounts. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 124557
Hi friends i've just made some updates on the YARDstick website: http://electronics.physics.auth.gr/people/nkavv/yardstick/ A summary of the updates: 1. Overview section 2. Screenshots section 3. A0-size poster that was used for presenting YARDstick at the DATE'07 University Booth. 4. Update on the download status/politics. Kind regards Nikolaos KavvadiasArticle: 124558
On Sep 25, 6:50 pm, John_H <newsgr...@johnhandwork.com> wrote: > Mark McDougall wrote: > > Symon wrote: > > >> If they gave the software away, they'd have to > >> charge more for the devices. > > > No - the money they make off development tools is a drop in the ocean > > compared to that made from selling silicon. > > > I - for the life of me - cannot work out why they'd even _want_ to charge > > for development tools. They're in the business of moving silicon - and I > > would've thought the _best_ way to do that is get as many people as > > possible programming that silicon?!? And the best way to do that is give > > away free development tools. > > > Ditto for the obscene price they charge for USB Blasters... > > > I guess their argument is that the web edition is free - but that only > > goes so far, as the OP has discovered. > > > We need an OQPE program (One Quartus Per Engineer)! ;) > > > Regards, > > Have you ever priced support? > With the software license comes an expectation for quick, accurate > support. If anybody and their brother got support free of charge, the > cost to support the hobbyist in designs becomes severe. The free tools > don't come with bottomless phone support as far as I'm aware. Serious > users need serious support. > > They could go to a pricing model where the tools are free but support > costs. Not many businesses are happy to pay for this model since "the > product should be doing everything I want in the first place so why > should I pay?" > > - John_H I personally haven't been thrilled about Altera's support. I thought Xilinx had a good first line of defence with their answer browser. Altera has started something called knowledge base but it hasn't helped me much so far. Most of my cases have been resolved by my own research. Further they have a couple of forums, the utility of which is also questionable. The only time Altera's support helps is when Altera forgets to include a key piece of information in their documentation such as an errata or help file, etc. Nevertheless, I agree that Q2 is getting complicated enough that they need a group to answer questions and act as first line of defence. Unfortunately, so far it is hasn't been reliable. -sanjayArticle: 124559
On Sep 26, 3:14 pm, Wei Wang <camww...@gmail.com> wrote: > On Sep 26, 1:37 pm, Gabor <ga...@alacron.com> wrote: > > > > > > > On Sep 25, 6:48 pm, Wei Wang <camww...@gmail.com> wrote: > > > > On Sep 25, 9:31 pm, Gabor <ga...@alacron.com> wrote: > > > > > On Sep 25, 2:12 pm, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > > > On Sep 25, 8:51 am, Wei Wang <camww...@gmail.com> wrote: > > > > > > > All I can find is a one-page specification of "Kingston > > > > > > KVR100X64C2/128", but I do not know about the input and output > > > > > > interface of this SDRAM, e.g., what are the input and output signals, > > > > > > and how the input and output signals are wired into each Synchronous > > > > > > DRAM (Infineon HYB39S128800CT-8) module. Many thanks, -Wei > > > > > > Hi, > > > > > Go to Infineon or Micron, or Samsung to search for similar SDRAM > > > > > chips. > > > > > > Kingston is not a chip manufacture, but a DIMM manufacture. > > > > > > All SDRAM chips are almost same with Micron having the tighest > > > > > requirements. > > > > > > You may print Micron 128800CT-8 SDRAM to see if there is a document > > > > > over there. Maybe they are all out of date. > > > > > > Weng > > > > > A good source for DIMM data is JEDEC. On their website, jedec.org, > > > > you > > > > can find standard connections for all standard DIMM types. If you > > > > know > > > > the type of chip and number of chips on your module you can generally > > > > narrow down the choices to one JEDEC standard. > > > > > Their website is a little hard to navigate, but the search feature > > > > generally gets you to the information you need, and all of the > > > > standards > > > > include reference schematics so you can see the chip connections. > > > > > HTH, > > > > Gabor- Hide quoted text - > > > > > - Show quoted text - > > > > Thanks Tianxiang and Gabor for your inputs, but I was a little > > > confused with the description in Kingston KVR100X64C2/128 "The > > > components on this module > > > include sixteen 8M x 8-bit (2M x 8-bit x 4 Bank / PC100 components) > > > SDRAM in TSOP packages", but when I look at Infineon HYB39S128800CT-8, > > > the chip has four banks inside, > > > each bank is 8 bits wide with 4M address, so each chip is 4Mx8bitx4, > > > which is 16MB. As the Kingston is 128 MB big and it has 8 Infineon > > > chips fitted, so I don't see why the KVR specification says the module > > > contains sixteeen 8Mx8-bit SDRAM. Should it be 8 16Mx8-bit SDRAM, then > > > I could not find this in JEDEC standard while I could find the JEDEC > > > standard for sixteen 8Mx8bit? Could somebody give me some hints on > > > this, thanks!!! > > > The data sheet also notes: > > > "Note: The module defined in this data sheet is one of several > > configurations available under this part number. While all > > configurations are compatible, the DRAM combination and/or the > > module height may vary from what is described here." > > > I'm not sure what they consider "compatible" in the case of modules > > with different memory organizations under the same part number, > > but I also noticed that they offer "Free Technical Support". > > > Perhaps someone at Kingston can address the issue? > > > Regards, > > Gabor- Hide quoted text - > > > - Show quoted text - > > Many thanks again for your input, I've called Kingston US support line > yesterday, but I was told that they could not provide anything in more > detail beyond the one-page specification found on their website. I've > however managed to find something very similar, such as the Samsung > KMM366S1723T datasheet which provides a better view of chip > organization.- Hide quoted text - > > - Show quoted text - The signals are pretty similar in either Samsung or Kingston, but I'm not entirely sure with the chip select signals. Just wondering whether the select signals should be the same for sdrams with same number of chips.Article: 124560
On Sep 24, 10:14 am, gilbert1219...@gmail.com wrote: > When I implement the reconfigure module, after ngdbuild, map and > continue with par there show some error but look like the same thing. > Did I place the busmacro in wrong place? My environment is > ISE9.1.02_PR2. Follow are error messages. Could any one tell me how to > fix these error, thanks. > Check two things. First that your busmacros are correctly placed between the static and partial reconfiguration region. Remember that busmacros are either 4 or 8 slices wide (depending on narrow or wide variety) and must evenly straddle the static and prr. Also remember that depending on which Virtex flavor of chip you are using, BM can only be loced into certain slices. Forexample on the V4, BM must be loced to even numbered slices. Second check that you are using the correct constraint file. At least in the EA flow you have to manually copy the top.ucf file to the appropriate directories. Hope this helps.Article: 124561
Is it possible to infer wide adders that require multiple DSP48s? In my experiments with Synplify, I found that it will infer a DSP48-based adder when the inputs are up to 36 bits wide, but when I use 37-bit inputs, the adder is synthesized in fabric. Is there a way to get this to work? XST won't do this either, at least according to the user's guide. -KevinArticle: 124562
Can anyone help on finding a home for the Altera Stratix GX chips. I am in a situation where one of my contracted accounts has purchased the Altera Stratix GX product prematurely. They are not going to be doing the build the product was procured for. Basically they are in a situation where they will let product go significantly below factory direct pricing. Please let me know if you know anyone who would be interested in the following chips. 106pcs EP2SGX90FF40C3N 60pcs EP2C35F672C6N 400pcs EP2S60F672C5N Regards, Jon E. Hansen (949)864-7745Article: 124563
On Sep 25, 6:47 pm, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal Murray) wrote: > >I guess economics? The FPGA company has to pay to develop their silicon and > >to develop their software. As the customer, we have to pay for both of > >these, one way or another. If they gave the software away, they'd have to > >charge more for the devices. This would be unfair to customers that use a > >lot of devices in their products over customers that use fewer parts. > > They have to pay for the software development anyway. > I think the economics term is "sunk costs". > > Support is a different matter. It might make sense to give > away the software and charge for support. But then, they would > get complaints about buggy software or lousy documentation. I agree with the concept of "sell the support." (Malcolm McLaren called "Step 3: Sell the Swindle.") Anyways, they already get complaints about buggy software and lousy documentation. Hopefully, though, charging for other than web knowledgebase support weeds out the hobbyists and timewasters so the support people could arguably do a better job. > Another argument is that if you are buying a lot of chips, > the cost of software is not important to your total cost. Indeed, but what's the cost of a license server crash over the weekend when you need to ship Monday morning? -aArticle: 124564
"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message news:fde7dq$mol1@cnn.xilinx.com... > Is it possible to infer wide adders that require multiple DSP48s? In my > experiments with Synplify, I found that it will infer a DSP48-based adder > when the inputs are up to 36 bits wide, but when I use 37-bit inputs, the > adder is synthesized in fabric. Is there a way to get this to work? XST > won't do this either, at least according to the user's guide. -Kevin From the Synplicity FPGA Synthesis Reference Manual (v8.9) syn_dspstyle Attribute In Virtex-4 and Virtex-5 designs, determines if an operator, register, or module/architecture is placed in the DSP48 component.Article: 124565
On Sep 25, 7:37 pm, Andy Peters <goo...@latke.net> wrote: > Somebody PLEASE explain to me why a license key is needed for software > that does one thing only: implement designs in the vendor's specific > logic family. Figured we'd end up there sooner or later... Theory I'm contemplating is that perhaps it's a form of vendor lock-in - the idea being that if you've invested money into being able to do the larger devices from X or A, you won't trivially jump ship and do a project on the other just because you got a good price on parts. The third-party ingredients idea can't be the whole story, or at least it's no excuse for the web versions of the suite being unable to target the entire range of silicon at the same level of tool functionality as is provided for the lower end parts.Article: 124566
Kevin Neilson wrote: > Is it possible to infer wide adders that require multiple DSP48s? In my > experiments with Synplify, I found that it will infer a DSP48-based > adder when the inputs are up to 36 bits wide, but when I use 37-bit > inputs, the adder is synthesized in fabric. Is there a way to get this > to work? XST won't do this either, at least according to the user's > guide. -Kevin I don't think any of the synthesis tools do it currently. You can, however write your RTL as a cascade of registered 36 bit adders and as long as the structure matches the DSP48 it should synthesize.Article: 124567
On Sep 25, 8:48 pm, Marc Randolph <mr...@my-deja.com> wrote: > On Sep 25, 4:30 pm, dudesinmex...@gmail.com wrote: > > > I am looking for open source software for logic minimization (a la > > espresso) targeted to a lookup table based architecture that can take advantage > > of six inputs LUTs (as you can imagine I have in mind a LUT6/Virtex 5 > > implementation). Is there such a beast? > > Howdy, > > You peaked my curiosity. Could you explain why you need this? Sure. I am working at a Virtex 5 design with *lots* of squarer circuits (Z=A*B with A=B) where the input is a signed 9 bit value in the [-255,255] range. I am wondering if the LUT6 would give any advantage compared to other implementations. Then, looking at Ray Andraka's page on multipliers I realized that a "Partial product LUT multiplier" looks like a good architecture for the squarer (since A=B the number of LUTs is cut in half), and that the LUT6 probably does not buy you more than a LUT4 since the carry chain limits the number of bits to four per slice. -ArrigoArticle: 124568
>Sure. I am working at a Virtex 5 design with *lots* of squarer >circuits (Z=A*B with A=B) where the input >is a signed 9 bit value in the [-255,255] range. 9 bits is a small number. Have you considered table lookup? -- These are my opinions, not necessarily my employer's. I hate spam.Article: 124569
dudesinmexico@gmail.com wrote: > On Sep 25, 8:48 pm, Marc Randolph <mr...@my-deja.com> wrote: > >>On Sep 25, 4:30 pm, dudesinmex...@gmail.com wrote: >> >> >>>I am looking for open source software for logic minimization (a la >>>espresso) targeted to a lookup table based architecture that can take advantage >>>of six inputs LUTs (as you can imagine I have in mind a LUT6/Virtex 5 >>>implementation). Is there such a beast? >> >>Howdy, >> >>You peaked my curiosity. Could you explain why you need this? > > > Sure. I am working at a Virtex 5 design with *lots* of squarer > circuits (Z=A*B with A=B) where the input > is a signed 9 bit value in the [-255,255] range. I am wondering if > the LUT6 would give any advantage > compared to other implementations. Then, looking at Ray Andraka's page > on multipliers I realized that > a "Partial product LUT multiplier" looks like a good architecture for > the squarer (since A=B the number of LUTs is cut in half), and that > the LUT6 probably does not buy you more than a LUT4 since the carry > chain limits the number of bits to four per slice. > > -Arrigo > > > The LUT size isn't related directly to the carry chain pitch. The 6 input LUTs (12 per partial product for a 6bit in, 12 bit out LUT) make your partial products, and then you add those together with the appropriate shifting for the weighting of the partials to arrive at the complete square. For 9 input bits though, you really only need 4 and 5 input LUTs. A 6 LUT implementation is still going to have 4 partial products, so there is no savings over 4/5 input LUTs. That said, you could use dual port BRAMs as direct look-ups instead and get two 9 bit squarers per BRAM (one on each port).Article: 124570
I wrote: > No, it may mean that the chip vendor is absorbing the license cost, and > making more profit on the non-M1. Antti wrote: > well, no, as the non-M1 silicon was available before the Cortex > agreement. > so if the actel FPGA have now M1 option, and the price of normal > silicon > has not changed then it would mean there are no hidden cost at all. I don't see how that precludes the possibility that Actel may be choosing to absorb the Cortex license cost when they sell you an M1-enabled part.Article: 124571
drop669@gmail.com writes: > Just interesting, how often some company is able to develope their own > RISC soft-core processor for their needs, without any need to publish > that fact or reveal any details? As often as they want to, and can afford to pay the engineers. Given the low cost of licensing existing soft cores (no charge for some), it seems that it would not be cost effective for most companies to develop their own, unless their requirements are so extreme that it doesn't make sense to customize an existing core.Article: 124572
On Sep 26, 3:57 pm, Ray Andraka <r...@andraka.com> wrote: > dudesinmex...@gmail.com wrote: > > On Sep 25, 8:48 pm, Marc Randolph <mr...@my-deja.com> wrote: > > >>On Sep 25, 4:30 pm, dudesinmex...@gmail.com wrote: > > >>>I am looking for open source software for logic minimization (a la > >>>espresso) targeted to a lookup table based architecture that can take advantage > >>>of six inputs LUTs (as you can imagine I have in mind a LUT6/Virtex 5 > >>>implementation). Is there such a beast? > > >>Howdy, > > >>You peaked my curiosity. Could you explain why you need this? > > > Sure. I am working at a Virtex 5 design with *lots* of squarer > > circuits (Z=A*B with A=B) where the input > > is a signed 9 bit value in the [-255,255] range. I am wondering if > > the LUT6 would give any advantage > > compared to other implementations. Then, looking at Ray Andraka's page > > on multipliers I realized that > > a "Partial product LUT multiplier" looks like a good architecture for > > the squarer (since A=B the number of LUTs is cut in half), and that > > the LUT6 probably does not buy you more than a LUT4 since the carry > > chain limits the number of bits to four per slice. > > > -Arrigo > > The LUT size isn't related directly to the carry chain pitch. The 6 > input LUTs (12 per partial product for a 6bit in, 12 bit out LUT) make > your partial products, and then you add those together with the > appropriate shifting for the weighting of the partials to arrive at the > complete square. For 9 input bits though, you really only need 4 and 5 > input LUTs. A 6 LUT implementation is still going to have 4 partial > products, so there is no savings over 4/5 input LUTs. > > That said, you could use dual port BRAMs as direct look-ups instead and > get two 9 bit squarers per BRAM (one on each port). Ray, nice to hear from you. Yes, I have considered BRAMs as lookup tables. In fact, we noticed that Synplify does something pretty cool: it packs two multipliers in a single BRAM18, using one port for each multiplier. Of course this is possible since they share the same table. According to the documentation, one can use a BRAM36 as two BRAM18s, however PlanAhead refuses to place a pblock with two BRAM18s on any area with just one BRAM36. This could be either a PlanAhead bug or simply that the BRAM36 still has just two ports...Article: 124573
dudesinmexico@gmail.com wrote: > On Sep 26, 3:57 pm, Ray Andraka <r...@andraka.com> wrote: > >>dudesinmex...@gmail.com wrote: >> >>>On Sep 25, 8:48 pm, Marc Randolph <mr...@my-deja.com> wrote: >> >>>>On Sep 25, 4:30 pm, dudesinmex...@gmail.com wrote: >> >>>>>I am looking for open source software for logic minimization (a la >>>>>espresso) targeted to a lookup table based architecture that can take advantage >>>>>of six inputs LUTs (as you can imagine I have in mind a LUT6/Virtex 5 >>>>>implementation). Is there such a beast? >> >>>>Howdy, >> >>>>You peaked my curiosity. Could you explain why you need this? >> >>>Sure. I am working at a Virtex 5 design with *lots* of squarer >>>circuits (Z=A*B with A=B) where the input >>>is a signed 9 bit value in the [-255,255] range. I am wondering if >>>the LUT6 would give any advantage >>>compared to other implementations. Then, looking at Ray Andraka's page >>>on multipliers I realized that >>>a "Partial product LUT multiplier" looks like a good architecture for >>>the squarer (since A=B the number of LUTs is cut in half), and that >>>the LUT6 probably does not buy you more than a LUT4 since the carry >>>chain limits the number of bits to four per slice. >> >>>-Arrigo >> >>The LUT size isn't related directly to the carry chain pitch. The 6 >>input LUTs (12 per partial product for a 6bit in, 12 bit out LUT) make >>your partial products, and then you add those together with the >>appropriate shifting for the weighting of the partials to arrive at the >>complete square. For 9 input bits though, you really only need 4 and 5 >>input LUTs. A 6 LUT implementation is still going to have 4 partial >>products, so there is no savings over 4/5 input LUTs. >> >>That said, you could use dual port BRAMs as direct look-ups instead and >>get two 9 bit squarers per BRAM (one on each port). > > > Ray, nice to hear from you. Yes, I have considered BRAMs as lookup > tables. > In fact, we noticed that Synplify does something pretty cool: it packs > two multipliers > in a single BRAM18, using one port for each multiplier. Of course this > is possible since > they share the same table. > According to the documentation, one can use a BRAM36 as two BRAM18s, > however > PlanAhead refuses to place a pblock with two BRAM18s on any area with > just one BRAM36. > This could be either a PlanAhead bug or simply that the BRAM36 still > has just two ports... > > It is a limitation of the BRAM36.Article: 124574
<dudesinmexico@gmail.com> wrote in message
news:1190849356.286625.69510@d55g2000hsg.googlegroups.com...
>
> Ray, nice to hear from you. Yes, I have considered BRAMs as lookup
> tables.
> In fact, we noticed that Synplify does something pretty cool: it packs
> two multipliers
> in a single BRAM18, using one port for each multiplier. Of course this
> is possible since
> they share the same table.
> According to the documentation, one can use a BRAM36 as two BRAM18s,
> however
> PlanAhead refuses to place a pblock with two BRAM18s on any area with
> just one BRAM36.
> This could be either a PlanAhead bug or simply that the BRAM36 still
> has just two ports...
From p 125 of ug190.pdf (v3.1 Virtex-5 User Guide, 9/11/2007)
Two RAMB18s can be placed in the same RAMB36 location by using the BEL
UPPER/LOWER constraint:
inst "my_ramb18" LOC = RAMB36_X0Y0 | BEL = UPPER
inst "my_ramb18" LOC = RAMB36_X0Y0 | BEL = LOWER
which is echoed in Ansew Record 25115
http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=25115
though I think the note's author forgot to write UPPER for the last line.
Darned cut & paste!
Whether PlanAhead supports these constraints natively isn't obvious. Ask
the hotline or your FAE!
- John_H
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