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> Most Modern FPGAs have block RAM that can be used for look-ups. Use > these as larger LUTs to get partial counts, and then sum up the > partials. If you can afford a multiplied clock, you can time multiplex > segments of your input vector into a smaller number of RAMs followed by > accumulators. Thank you, Ray. Let me just add that a dual-ported RAM can then be used as two separate look-up tables, by addressing the two ports independently, using common data. This is obvious once you think about it, and it cuts the number of BRAMs in half... Peter AlfkeArticle: 124801
"Ray Andraka" <ray@andraka.com> wrote in message news:sEbNi.9606$Bq3.5856@newsfe18.lga... > Grumps wrote: >> [posted to comp.arch.fpga + comp.lang.vhdl] >> Hi All >> I've had a quote from a 3rd party to develop a floating point FFT core >> for us (1Mpt). Probably for a Xilinx Virtex5 SXT. >> Obviously I'd like to get some more quotes, but would like to know if you >> have any recommendations? >> Thanks. > > I've got a floating point FFT engine for V4 that I am porting to V5. It > is the fastest floating point FFT for FPGAs available anywhere (up to 1.2 > GS for the 32-2K point FFT). It can be adapted for 1M points and will > still beat anything out there for speed/density. There is info on my > website http://www.andraka.com regarding my IP, including a paper > discussing it. Interesting reading. You have mail!Article: 124802
I'm not even sure if this might be a stupid question. I have a Xilinx app note on daisy-chaining FPGA configurations, but can Xilinx CPLDs be placed on the chain as well?Article: 124803
On 4 Okt., 12:38, Steven Derrien <sderrienREM...@irisa.fr> wrote: > I am currently working on a circuit which has to perform Hamming > distance computation between large bit vectors (>500 bits). > > I was surprised not to find much information on how to implement this > type of operation *efficiently* on FPGA technology. > > So far I have been investigating two approaches (combining tables and > counter for the bitcouting part). I observed that the choice of table > size (3 or 4 address bits) had a significant impact (20%) on the area > cost of the operator. There was a lengthy discussion about bitcounting in the FPGA forum on mikrocontroller.net: http://www.mikrocontroller.net/topic/34231#new http://www.mikrocontroller.net/topic/34250#newArticle: 124804
<pomerado@hotmail.com> wrote in message news:1191534471.228883.255710@r29g2000hsg.googlegroups.com... > I'm not even sure if this might be a stupid question. I have a Xilinx > app note on daisy-chaining FPGA configurations, but can Xilinx CPLDs > be placed on the chain as well? CPLDs aren't typically configured like FPGAs. When the FPGA is changed, there's usually an update to the image either in a programming ROM or in system flash. In the same way when a CPLD is changed, the ROM in the CPLD is updated. These updates are typically a different process than the configuration chaining you're reading about. JTAG chains can configure *and* update and are designed to be daisy-chained. On programming cable can perform CPLD updates, FPGA updates if you're using the programming ROM, and on-the-fly CPLD configurations for testing new FPGA code with a volatile configuration.Article: 124805
I would like to use one hot state machine in verilog. I am using Xilinx V5 FPGA and XST synthesis tool. May i know the verilog syntex to do one hot? Thanks. CPArticle: 124806
<cpandya@yahoo.com> wrote in message news:1191538493.180180.182420@w3g2000hsg.googlegroups.com... >I would like to use one hot state machine in verilog. I am using > Xilinx V5 FPGA and XST synthesis tool. May i know the verilog syntex > to do one hot? > > Thanks. > > CP Repeat 3 times: "Google is gooood." http://toolbox.xilinx.com/docsan/xilinx4/data/docs/xst/hdlcode15.htmlArticle: 124807
On Oct 4, 6:12 pm, "John_H" <newsgr...@johnhandwork.com> wrote: > <cpan...@yahoo.com> wrote in message > > news:1191538493.180180.182420@w3g2000hsg.googlegroups.com... > > >I would like to use one hot state machine in verilog. I am using > > Xilinx V5 FPGA and XST synthesis tool. May i know the verilog syntex > > to do one hot? > > > Thanks. > > > CP > > Repeat 3 times: "Google is gooood." > > http://toolbox.xilinx.com/docsan/xilinx4/data/docs/xst/hdlcode15.html I am still unable to see the xst directive that telss the the xst synthesis tool that the state machine is one-hot. Is there such a thing? Google is good.Article: 124808
On Oct 5, 1:30 am, cpan...@yahoo.com wrote:
> On Oct 4, 6:12 pm, "John_H" <newsgr...@johnhandwork.com> wrote:
>
> > <cpan...@yahoo.com> wrote in message
>
> >news:1191538493.180180.182420@w3g2000hsg.googlegroups.com...
>
> > >I would like to use one hot state machine in verilog. I am using
> > > Xilinx V5 FPGA and XST synthesis tool. May i know the verilog syntex
> > > to do one hot?
>
> > > Thanks.
>
> > > CP
>
> > Repeat 3 times: "Google is gooood."
>
> >http://toolbox.xilinx.com/docsan/xilinx4/data/docs/xst/hdlcode15.html
>
> I am still unable to see the xst directive that telss the the xst
> synthesis tool that the state machine is one-hot. Is there such a
> thing?
>
> Google is good.
Find "XST User Guide" (in PDF) on xilinx.com. You will find plenty of
informations about XST. The same goes for "Constraints Guide" (also
PDF).
>From the doc:
(for VHDL)
attribute fsm_encoding of {entity_name|signal_name}: {entity|signal}
is
"{auto|one-hot|compact|gray|sequential|johnson|speed1|user}";
(for Verilog)
// synthesis attribute fsm_encoding [of] {module_name|signal_name}
[is] {auto|one-hot|compact|gray|sequential|johnson|speed1|user};
Cheers
Article: 124809I do believe the xilinx tools default to 1-hot implementation if left unspecified.Article: 124810
On 4 Okt., 23:58, Andreas Schwarz <use...@andreas-s.net> wrote: > On 4 Okt., 12:38, Steven Derrien <sderrienREM...@irisa.fr> wrote: > > > I am currently working on a circuit which has to perform Hamming > > distance computation between large bit vectors (>500 bits). > > > I was surprised not to find much information on how to implement this > > type of operation *efficiently* on FPGA technology. You find the background in theoretical text books on parallel computing. Prefix sum is a fundamental sub problem and a lot has been written about the implementation of sums and prefix sums on various architecturs including networks of operators. The results translate directly to FPGAs. (Counting bits reduces to summing numbers, albeit small numbers). Kolja SulimmaArticle: 124811
Hi Ray, That's indeed what I did, except that BRAM are somewhat overkill for the purpose. So far, the best approach I came up with was to store in a LUT the bitcount of a 3 bit wide vector (after xoring the 2 operand for Hamming), and use an adder tree ot obtain the Hamming distance value. Using larger tables (for vectors of 4 and more bits) ends up in a signifcant area penalty (~20%). Steven Ray Andraka a écrit : > Steven Derrien wrote: > >> Hi, >> >> I am currently working on a circuit which has to perform Hamming >> distance computation between large bit vectors (>500 bits). >> >> I was surprised not to find much information on how to implement this >> type of operation *efficiently* on FPGA technology. >> >> So far I have been investigating two approaches (combining tables and >> counter for the bitcouting part). I observed that the choice of table >> size (3 or 4 address bits) had a significant impact (20%) on the area >> cost of the operator. >> >> I feel that there are many subtle trade-offs in such implementations, >> and I was wondering if anybody had been looking at this problem (most >> of the articles I stumbled accross dealt with the correcting code >> issue, rather than focusing on the Hamming distance realization in >> itself). >> >> Thanks in advances for the input. >> >> Regards, >> >> Steven >> > > Most Modern FPGAs have block RAM that can be used for look-ups. Use > these as larger LUTs to get partial counts, and then sum up the > partials. If you can afford a multiplied clock, you can time multiplex > segments of your input vector into a smaller number of RAMs followed by > accumulators.Article: 124812
Thanks to all of you for responding and providing me with the information. I especially liked the mix of information from both research (Kolja and Hicks) as compared to the commercial information others provided. I would get through this information over this weekend. Thanks again, O.O.Article: 124813
Hi all! Next problem with Tcl. 1. I've got something like that in the script: >>puts [clock format [clock seconds] -format "\[%H:%M:%S\]"] >> >>puts "Generation Programming File\n"; >>set start_time [clock seconds]; >>process run "Generate Programming File"; >>set stop_time [clock seconds]; >>puts "File Generation Time: [expr $stop_time - $start_time]s"; >> >>puts [clock format [clock seconds] -format "\[%H:%M:%S\]"] 2. And I get this answer: >>[10:33:26] >> >>Generation Programming File >> >>ERROR:TclTasksC:process_070 - process run : Before running : incorrect num tasks 1 - expected 0 >>false It happens not every time. Sometimes it works. I use Tcl in ISE Window, not from system command line. It seems like tasks colision. Have you got any idea, how to walkaround that? Greetings, Jerzy GburArticle: 124814
On Fri, 05 Oct 2007 08:51:28 -0000, "jerzy.gbur@gmail.com" <jerzy.gbur@gmail.com> wrote: >It happens not every time. Sometimes it works. >I use Tcl in ISE Window, not from system command line. >It seems like tasks colision. >Have you got any idea, how to walkaround that? Try running in batch mode: > isim -batch on EvanArticle: 124815
On Oct 4, 6:10 am, "Pete Fraser" <pfra...@covad.net> wrote: > "cms" <Michael.Tsvet...@gmail.com> wrote in message > > news:1191497591.671967.88400@y42g2000hsy.googlegroups.com... > > > > > No, it works now. Periodically somebody ddos-attacked hosting and site > > goes down. But I hope it's temporary problem. > > I've tried about 20 times over the last 24 hours > (since you first posted on comp.compression). > > No luck. Works from CA.Article: 124816
On Oct 4, 10:30 am, "cpope" <cep...@nc.rr.com> wrote: > I have a design that was built with XPS 8.2.03. I want to lock down > everything in the design except one custom OPB peripheral I created. I want > other users to be able to modify that peripheral (from user_logic.vhd down) > and recompile the design with only the ISE software. > > If I use "export to ISE" are they still able to modify user_logic.vhd and > below? > Do they still need an XPS install to build? > Does ISE allow them to initialize the BRAMs with my bootloader .elf? > > Maybe somebody in this group has already done this? I want users to be able > to implement some custom hardware on my product but I don't want them > messing with the CPU and other peripherals and I'm trying to avoid the > expense of forcing them to buy XPS since they don't really need it. > > Thanks, > Clark I know you say you're using EDK 8.2, but if you have ISE 9.1, you could use the partitioning feature to create a partition around everything but that peripheral. That way they could modify just the peripheral and only it would need to be re-synthesized, map/par'd etc.Article: 124817
On Oct 5, 12:38 am, Jeff Cunningham <j...@sover.net> wrote: > I do believe the xilinx tools default to 1-hot implementation if left > unspecified. This is in fact true. It's also very annoying if you don't realize this and scratch your head for days wondering why a simple state machine with a 3-bit binary encoding and 8 states can lock up...Article: 124818
I own an original Xilinx/Digilent Spartan-3 Starter Kit (200K device) at $99 and since some months ago also a Xilinx/Digilent Microblaze Starter Kit (1600E device) at $295 and am very satified with both of them but of course it depends on what type of work you are willing to put in and how big projects you are aiming for. For staying in the cheap but quite capable beginner to intermediate class I would recommend the original Xilinx/Digilent Spartan-3 Starter Kit BUT with the 1000K-circuit option. For a mere $50 more you get 5 times the logic so that's great. But this board only uses 1MB 100Mhz SRAM so it is not really suitable for Video-stuff of any resolution or actions like Filtering. Its not suitable for Operating system-labbin either 1MB is just too small for other than the most simplest system like the TRS-80, C64 or similar retro-stuff. No Ethernet and no USB. It uses the Parallell-cable for download Like an earlier post said its 2*20 0.1" connectors is just great, easy and cheap to play with. I've connected everything from speakers, external VGA-screens to Joysticks and SD-Card connectors this way! For some more power and ALOT of logic I think the $295 1600E-based Starter-3E Kit is probably unbeatable for a non-student hobbyist. It just fits about every core you can think of and mostly give headroom for MORE. On the downside the external connector it uses a Hirose 100- pin FX2 connector that don't come cheap from a hobby-side view, like $25 for just a single connector if I remember correctly. One of the demos that come with the board is a ucLinux dist with FTP, Telnet- support! But for you to be able to make changes to its "hardware"-part in a resonably simple way you need the real license for the Microblaze- core and its tools and that will cost you $$. Otherwise if you like Altera I think that their DE-2 Development-card seems just great for doing Multimedia stuff. Hope this helps! Best Regards Magnus Wedmark vasile skrev: > > What do I want to do with them? > > Educate myself on FPGA. Hence I like to use the following: > > 1) Standard JTAG interfaces from Xilinx. I would like to be able to > > copy > > some of the existing schematics from the protoboard to my designs > > and work with it from standard JTAG. For example: > > - proprietary USB-JTAG interface on the nexys boards is a no no. > > > That's easy if you are satisfied with the standard Xilinx LPT jtag > cable. > The jtag connector is onboard. The schematic is here: > http://www.xilinx.com/support/programr/jtag_cable.pdf > The user guide is here: > http://www.xilinx.com/bvdocs/publications/ds097.pdf > Device family support and miscelanous: > http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-PC4 > > Vasile > > > > > 2) A speedy memory interface. > > 3) A large space for multiple cores.... > > > > Essentially the board must have most of the capabilities for the > > following work: > > > > 1) Plenty of i/o and adequate memory speed. example logic analyzer > > 2) Enough stuff for video and audio work. > > 3) DSP work..... > > > > So far this is the kind of work I am aiming for on the board. So the > > first project > > on the board as exercise would be NTSC output :) > > > > Regards, > > John- Hide quoted text - > > > > - Show quoted text -Article: 124819
On Sun, 30 Sep 2007 06:24:52 -0000, Antti <Antti.Lukats@googlemail.com> wrote: >On 30 Sep., 03:24, Ray Andraka <r...@andraka.com> wrote: >> johnp wrote: >> >> > I'd be happy if Xilinx would simply provide a free running, loosely >> > spec'd clock in the FPGAs >> > that a designer could use for non-critical design. They could spec it >> > as "it runs at some >> > frequency between 5 and 30 MHz and will drift with temperature/ >> > voltage, you can't set it, >> > you can only use it." If they would let you use the Master Mode >> > programming clock inside >> > the design, I'd be happy. I don't care about the frequency, I just >> > want a free running clock. >> >> > No crystal pads, no clock divider, just a ring oscillator within a >> > reasonable frequency range. >> >> > John Providenza >> >> Virtex4 actually has this. It isn't well documented, but it is there. >> Xilinx uses it for the NBTI fix in V4 devices. It does have an internal >> purpose, I think it was for one of the configuration download modes. >> >> I don't recall off-hand the magic incantation to use it, I'd have to >> find it in my design files. I think you have to make a hard macro in >> FPGA editor to get at it.- Zitierten Text ausblenden - >> >> - Zitierten Text anzeigen - > >yes PMV primitive can be used as free running clock, but its tricky to >use it as it xilinx undocumented feature > >Antti 1-0 for Lattice then: MachXO (biggest 2 devices) has an on-board osc, and ECP2, and ECP2M and XP2. Fairly easy to use even. LucArticle: 124820
On Oct 4, 2:58 pm, Andreas Schwarz <use...@andreas-s.net> wrote: >> > There was a lengthy discussion about bitcounting in the FPGA forum on > mikrocontroller.net:http://www.mikrocontroller.net/topic/34231#newhttp://www.mikrocontroller.net/topic/34250#new For the English-only readers: There is nothing of value in that German discussion, just repetitive trivialities. You don't miss anything if you cannot read it. Peter AlfkeArticle: 124821
"spartan3wiz" <magnus.wedmark@gmail.com> wrote in message news:1191594443.303849.241260@19g2000hsx.googlegroups.com... <snip> > .... On the downside the external connector it uses a Hirose 100- > pin FX2 connector that don't come cheap from a hobby-side view, like > $25 for just a single connector if I remember correctly. ... <snip> I picked up a couple connectors from Digikey 1 year ago this Tuesday at $6.79 each. They still show up at the same price: http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=H4324-ND The Hirose connector form factor may be "inconvenient" for perf-board hobbyists, but we're getting beyond the age of simple perf-board circuits. - John_HArticle: 124822
Hi cms, Good work ! If you have your VHDL code open, please give me a copy. Thank you. WengArticle: 124823
On Fri, 05 Oct 2007 07:27:23 -0700, spartan3wiz <magnus.wedmark@gmail.com> wrote: >I own an original Xilinx/Digilent Spartan-3 Starter Kit (200K device) >at $99 and since some months ago also a Xilinx/Digilent Microblaze >Starter Kit (1600E device) at $295 and am very satified with both of >them but of course it depends on what type of work you are willing to >put in and how big projects you are aiming for. > >For staying in the cheap but quite capable beginner to intermediate >class I would recommend the original Xilinx/Digilent Spartan-3 Starter >Kit BUT with the 1000K-circuit option. For a mere $50 more you get 5 >times the logic so that's great. But this board only uses 1MB 100Mhz >SRAM so it is not really suitable for Video-stuff of any resolution or >actions like Filtering. Its not suitable for Operating system-labbin >either 1MB is just too small for other than the most simplest system >like the TRS-80, C64 or similar retro-stuff. No Ethernet and no USB. >It uses the Parallell-cable for download >Like an earlier post said its 2*20 0.1" connectors is just great, easy >and cheap to play with. I've connected everything from speakers, >external VGA-screens to Joysticks and SD-Card connectors this way! > >For some more power and ALOT of logic I think the $295 1600E-based >Starter-3E Kit is probably unbeatable for a non-student hobbyist. It >just fits about every core you can think of and mostly give headroom >for MORE. On the downside the external connector it uses a Hirose 100- >pin FX2 connector that don't come cheap from a hobby-side view, like >$25 for just a single connector if I remember correctly. One of the >demos that come with the board is a ucLinux dist with FTP, Telnet- >support! But for you to be able to make changes to its "hardware"-part >in a resonably simple way you need the real license for the Microblaze- >core and its tools and that will cost you $$. > >Otherwise if you like Altera I think that their DE-2 Development-card >seems just great for doing Multimedia stuff. > >Hope this helps! > >Best Regards >Magnus Wedmark > > Yeah this is a good feedback that I need:) Thanks, John ChungArticle: 124824
Hi, I had the same problem. Maybe your project files are network drive. If so, this error occurs. You should use local drive to put the files. But you can solve this problem if you use ver9.2.3. Hope this helps. On 9 21 , 11:36, gilbert1219...@gmail.com wrote: > I have a doc. named "Partial Reconfiguration Design with PlanAhead > 9.2" and use PR_V5_DVI.zip for example. > > While following the step to Implementing the Static Logic and > Implementing the PR Modules, there be a problem. > > After PAR completed the static Launch run and continue to Launch run > for PR Modules, I got a error message said:"Static run needs to > complete before any config runs are launched. Please reset this config > run and complete the static run. Upon completion you can safely re- > launch this config run." > > But the static run is already complete. Even I reset the PR Modules > form the original source of PR_V5_DVI.zip, there stilled the same > error. > > By the way, I follow the PR_install.pdf re-install all the software > again in the order but nothing change. > > It still doesn't work. > > Could any environment setting problem casue this error or put the > projecet file in wrong location? Did I miss some step or what? Could > you help me fix up this problem? > > Thanks.
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