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On May 14, 10:44 pm, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > xcr3064xl wrote: > > Which one is the fuse file? > > After 'generate programming file' run, you should have a DesignName.JED > file. > > If that does not change (and it is not in your list) I only listed a couple (but not all) files that differed. (quote: "Here are _some_ differences:") The complete list is at the bottom of this post: The first directory (with the -commented suffix) has the assignments commented out, the other (with the drive0 suffix) has <= '0' assigned to pins. As you see both .jed and .rpt files are included in the listing (=they differ). The .rpt file in the -commented directory (i.e. the directory where the assignments are commented out) contains the following warnings: Cpld936: The ouput buffer 'p14_OBUF' is missing an input and will be deleted. This, again, makes sense because nothing is driving the pin. The warnings are gone when I add the assignment (e.g P14 <= '0') diff -q -r 1diode-run1-commented/ 1diode-run2-drive0 Files 1diode-run1-commented/1diode.dhp and 1diode-run2- drive0/1diode.dhp differ Files 1diode-run1-commented/_impact.cmd and 1diode-run2-drive0/ _impact.cmd differ Files 1diode-run1-commented/_impact.log and 1diode-run2-drive0/ _impact.log differ Files 1diode-run1-commented/_ngo/netlist.lst and 1diode-run2-drive0/ _ngo/netlist.lst differ Files 1diode-run1-commented/__projnav/1diode_flowplus.gfl and 1diode- run2-drive0/__projnav/1diode_flowplus.gfl differ Files 1diode-run1-commented/__projnav/1diode.gfl and 1diode-run2- drive0/__projnav/1diode.gfl differ Files 1diode-run1-commented/__projnav.log and 1diode-run2-drive0/ __projnav.log differ Files 1diode-run1-commented/xc3064xl.chk and 1diode-run2-drive0/ xc3064xl.chk differ Files 1diode-run1-commented/xc3064xl.cmd_log and 1diode-run2-drive0/ xc3064xl.cmd_log differ Files 1diode-run1-commented/xc3064xl.cxt and 1diode-run2-drive0/ xc3064xl.cxt differ Files 1diode-run1-commented/xc3064xl.gyd and 1diode-run2-drive0/ xc3064xl.gyd differ Files 1diode-run1-commented/xc3064xl_html/fit/ascii.htm and 1diode- run2-drive0/xc3064xl_html/fit/ascii.htm differ Files 1diode-run1-commented/xc3064xl_html/fit/defeqns.htm and 1diode- run2-drive0/xc3064xl_html/fit/defeqns.htm differ Files 1diode-run1-commented/xc3064xl_html/fit/eqns.htm and 1diode-run2- drive0/xc3064xl_html/fit/eqns.htm differ Files 1diode-run1-commented/xc3064xl_html/fit/summary.htm and 1diode- run2-drive0/xc3064xl_html/fit/summary.htm differ Files 1diode-run1-commented/xc3064xl.jed and 1diode-run2-drive0/ xc3064xl.jed differ Files 1diode-run1-commented/xc3064xl.mfd and 1diode-run2-drive0/ xc3064xl.mfd differ Files 1diode-run1-commented/xc3064xl.ngc and 1diode-run2-drive0/ xc3064xl.ngc differ Files 1diode-run1-commented/xc3064xl.ngd and 1diode-run2-drive0/ xc3064xl.ngd differ Files 1diode-run1-commented/xc3064xl.ngr and 1diode-run2-drive0/ xc3064xl.ngr differ Files 1diode-run1-commented/xc3064xl.pad and 1diode-run2-drive0/ xc3064xl.pad differ Files 1diode-run1-commented/xc3064xl_pad.csv and 1diode-run2-drive0/ xc3064xl_pad.csv differ Files 1diode-run1-commented/xc3064xl.pnx and 1diode-run2-drive0/ xc3064xl.pnx differ Files 1diode-run1-commented/xc3064xl.rpt and 1diode-run2-drive0/ xc3064xl.rpt differ Files 1diode-run1-commented/xc3064xl.syr and 1diode-run2-drive0/ xc3064xl.syr differ Files 1diode-run1-commented/xc3064xl.vhd and 1diode-run2-drive0/ xc3064xl.vhd differ Files 1diode-run1-commented/xc3064xl.vm6 and 1diode-run2-drive0/ xc3064xl.vm6 differ Files 1diode-run1-commented/xc3064xl.xml and 1diode-run2-drive0/ xc3064xl.xml differ Files 1diode-run1-commented/xst/work/hdllib.ref and 1diode-run2-drive0/ xst/work/hdllib.ref differ Files 1diode-run1-commented/xst/work/hdpdeps.ref and 1diode-run2- drive0/xst/work/hdpdeps.ref differ Files 1diode-run1-commented/xst/work/sub00/vhpl00.vho and 1diode-run2- drive0/xst/work/sub00/vhpl00.vho differ Files 1diode-run1-commented/xst/work/sub00/vhpl01.vho and 1diode-run2- drive0/xst/work/sub00/vhpl01.vho differ K. > then > it seems the tools are 'droppnig the ball'. > > Does the fitter .RPT file change equations for the pin ? > > -jgArticle: 132151
On May 15, 2:57 am, taco <b...@joepie.org> wrote: > anybody ever used the SPI core for microblaze? I found as example only a > montevista spi driver which basically is doing all the bitbanging at a low > level and uses it's own fifos, i.e. not using the xspi routines described > in the xilinx_drivers reference. Are there any problems with the xilinx > routines? Anybody some examples of usage? > Taco Yes. I used it on a project last year to talk to a MxFE (Mixed signal front end) ASIC with a simple SPI interface. Not too tricky, but you do have to setup an interrupt handler. The example code is a pretty good start, and there is a dummy interrupt handler that you can copy/ modify that will do most of what you want. Unfortunately, I can't share the code as it is unpublished, but the core isn't too hard to work with. I don't believe the hardware supports FIFO's, though. One key thing is to make sure you setup the clock divider correctly. SPI generally tops out at 16MHz, and is even slower if you have multiple devices on a single master. If you have a substantially faster system clock, you may have pay attention to that.Article: 132152
On May 15, 11:01=A0am, ghel...@lycos.com wrote: > On May 14, 4:23 pm, ghel...@lycos.com wrote: > > > When starting an EDK project, there is an option to download XBD files > > from the board vendor. > > > After you have downloaded it (or written one), how do you get the EDK > > to use it? > > > I've tried adding it to the 'board' directory(even though the > > documentation explicitly says that it in named boards), and I have > > searched in vain for the command to change the library search path... > > > Thanks & regards, > > G. > > Update: > > I have found the method to change the library search path. =A0This > appears to be broken (EDK-9.1.2). > > I found the Xilinx forum. =A0There are a number of people asking similar > questions, but no answers are posted. > > This should be real easy. =A0It's very frustrating that it's not > working, and the documentation for how to use it assumes that you > already know how. > > G. G., Sounds like you have already referred to the Xilinx documentation. Just to be sure, the best source is the Platform Studio Reference Manual. Check out Chapter 9, XBD Load Path. http://www.xilinx.com/support/documentation/sw_manuals/edk10_psf_rm.pdf Avnet also provides some supplemental documentation related to the Avnet XBD files, which includes some screenshots for added clarity. Goto www.em.avnet.com/xbd. Inside the 9.1 archive is a document called Avnet_BSB_Tutorial_060710.pdf. It's a little old, but I think still relevant. BryanArticle: 132153
We need data... You have told us nothing about speed, length (long doesn't count), type/specs of cable, etc.......... I've transmitted 400mbps over 5m using 3M MDR cable assemblies, driven by an FPGA. I've received up to 300mbps, FPGA's on both ends, Xilinx (tx) and Altera (rx)--this is evidence that two foes can play nice together :) Rob Crhonos04@gmail.com wrote: > Hello, > > I've implemented a camera link deserializer interface based on a > virtex 4 FPGA (using ML402 development board). I'm using the LVDS 2.5 > V inputs of the board and a cable with one end open. > > The module works fine when i use a short cable. However, my > application needs to use a long cable (with a discontinuity) which > doesn't work so fine. The thing is that I guess there is a match > problem in the board reception side, because when i represent the eye > diagram of the incoming signals (once it's converted to LVTTL) and the > long cable is used, it's really bad. > > I know that it is possible to use this long cable because it works > with a generic frame grabber. > I've tried using the DCI (Digital Control impedance) of the FPGA, > LVDS_EXT standard... but i don't reach a solution... > > If someone could have some experience in this field... > > Thank very much in advace !Article: 132154
Austin, That is not entirely true. I've used both the Cyclone3 and the Stratix3 with VCCIO at 3.3V. In fact, this is the verbiage used in the S3 spec: Stratix III devices support a wide range of industry I/O standards. Table 7–1 shows the I/O standards Stratix III devices support as well as the typical applications. Stratix III devices support a VCCIO voltage level of 3.3, 3.0, 2.5, 1.8, 1.5, and 1.2 V. The issue with the 65nm is that one needs to pay CLOSE attention to over shoot and undershoot voltages. There are three ways to deal with this: 1. Proper termination 2. Clamping diodes 3. Or reduce the VCCIO bank voltage to 3.0V If you do your job correctly you can run these devices at 3.3V w/o any problems. Rob austin wrote: > Karel, > > Cyclone III does not have 3.3v, it only has "3.0 volt IO" -- a new > "standard" from Altera! (Stratix III is the same). > > Why? Because TSMC does not have a process that has the small fast core > transistors, and the larger 3.3v IO transistors. > > So, 3.3v is now going the way of 5.0v -- gone. Xilinx still has 3.3v IO > at 65nm in Virtex 5, but that is only because we have our own triple > oxide process "built to order" by two fabs, UMC and Toshiba. > > Good luck! > > AustinArticle: 132155
recoder wrote: > Dear All, > Are there any Open source Core generators available? I am looking > for FIR and FFT Core generators but also wonder if open source > generators for other functions exist. > Thanks in Advance Give opencores.org a try. I believe there is a FIR generator available. Cheers, GuenterArticle: 132156
We are using SPARTAN 3 E FPGA. I would like to know what is the difference between ISE 8.2i and ISE 9.2i with respect to the micro blaze core. We are able to access the FLASH and RTC via SPI in 8.2i whereas the same is not possible in 9.2i. So we would like to know what is the difference between 8.2i and 9.2i.Article: 132157
Dear all,
may anybody help me to do the task. My task it to transmit some
data over bluetooth from one FPGA to another using Bluetooth link
I have decided to use LwBT libraries which uses LwIP. but I do
not know how to change the HCI layer or any other according to
microblaze. I am using ML402 board with EDK 9.1.03.
Thanks
Article: 132158
Hi ,
My question is silly but i need answers !
=> what do we mean by saying " distributed RAM" inside FPGA ?
what's the difference between "bistributed RAM" and BRAM inside
FPGA ?
thank you
Article: 132159> So, 3.3v is now going the way of 5.0v -- gone. =A0Xilinx still has 3.3v IO= > at 65nm in Virtex 5, but that is only because we have our own triple > oxide process "built to order" by two fabs, UMC and Toshiba. You'd better talk to the guys that make the V5 datasheets, because the recommended operating conditions do not leave a lot of room for 3.3V I/ O (3.45V). With both the Cyclone III and Stratix III you are better of at 3.6V recommended maximum input voltage. With the absolute maximum rating the V5 does a better job. A whole 50 mV more than the Stratix III (4.05V vs 4V). Let's see how Xilinx will do with their Spartan 4 in terms of 3.3V I/O. Happy reading. Karl.Article: 132160
> I am drawing schematics for a new system that uses a Cyclone 3 FPGA. I > have some LVTTL (3V3) signals on which I would like to use a 50R > series termination. > The Cyclone 3 has two possible 50R series terminations: > - not calibrated > - calibrated > The handbook doesn't specify the standards that can be used with the > calibrated termination. Has anybody got this data? > The handbook mentions that the uncalibrated termination can be used > with 3.0V LVTTL, it doesn't mention 3.3V LVTTL, is this a typo -or- is > 3.3V LVTTL with on-chip termination not supported? To my knowledge the Cyclone III only features the additional I/O features at 3.0V or lower. 3.3V is supported but all clamping, terminating, rail pulling and slew rate compensating has to be done external of the device. A quick way to check what is and what is not possible is to make a small project within Quartus II with I/O assignments like you want them. Red messages will indicate that the device does not support it... The 3.3V outputs are limited in drive strength as well. Karl.Article: 132161
<bamboutcha9999@hotmail.com> wrote in message news:afb6208d-51ba-477c-b73d-b26da449b4f7@x35g2000hsb.googlegroups.com... > Hi , > > My question is silly but i need answers ! > > => what do we mean by saying " distributed RAM" inside FPGA ? > what's the difference between "bistributed RAM" and BRAM inside > FPGA ? > > thank you http://www.xilinx.com/support/documentation/user_guides/ug070.pdfArticle: 132162
Hi to all, Is there a way for measuring the length -in terms of time of course- between the blocks in an FPGA? I am trying to do this by using post- route simulations. I wonder if there is a much more efficient way. Up to now I only used Xilinx FPGAs but the information is also welcome for Altera's. Regards.Article: 132163
First of all, thank you for your answers. I answer some of your questions: - cam_clk = 40 MHz - Data rate = (about) 378 Mbps [30 fps; frame size 1024 x 1024; 12 bit digitalization] - My ucf and vhdl is the same that Brad's one (but without ISERDES) About the cable, is 5 meters in length. The problem is that there is an intermediate sub-D connector which is joining two 2.5 m cables, id est, the cable consists in a camera link connector - a sub-D female - a sub-D male - pins to FPGA board. I really know that this is not the most suitable for high frequency signals, but the thing is that this cable works when the receiver is a frame grabber or a board using the NI deserializer chip. Once the input signals are received by the FPGA, they're wrong, so...if there's a problem I guess it's a mismatch or something like that. Anyway I'm not an expert...if you have more ideas... Thank you, ChronosArticle: 132164
Hi, I need to interconnect two or four FPGAs on a PCB, and I am looking at the prospect of designing these boards myself. If any one has done this, I would be grateful if you could provide some pointers, especially links to websites that have this information. I would probably be using the Xilinx Virtex II I don=92t know how to start this =96 but I have a few questions. Is it possible for me to simulate the setup between FPGAs connected on a PCB board. Or is it possible for me to bread board the FPGA =96 I have not heard of this though. I have looked at the manual of the Virtex II, and there are a large numbers of pins =96 I have yet to figure out which pins I need to power at the minimum to get this to work. So I don=92t want to start laying out a PCB Board immediately. I would be requiring significant on board communication =96 but I don=92t think I need the Rocket IOs that are available with Virtex4 =96 the simple LVDS would do for me I guess. Is there a way for me to test this aspect before actually putting it on the PCB?? I have so far used FPGAs on the protyping board that comes with the Spartan Kit from Xilinx. I have also used an Emulation machine with a couple of FPGAs. In all of this I have never been concerned about the external connections between FPGAs, so I am new to all of this. Any help is welcome. Thanks a lot. O.O.Article: 132165
========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for entity <Top_Module> in library <work> (architecture <struct_1>). ERROR:Xst - Xst_HdlConst_Imp::GetArrayValueByIndex : index out of range. ERROR:Xst - Unexpected error found while building hierarchy. --> Total memory usage is 123236 kilobytes Number of errors : 2 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered)Article: 132166
Hi Enes load your placed and routed design into the fpga_editor. There you can select signal lines and determine the delays. Have a nice synthesis Eilert Enes Erdin schrieb: > Hi to all, > > Is there a way for measuring the length -in terms of time of course- > between the blocks in an FPGA? I am trying to do this by using post- > route simulations. I wonder if there is a much more efficient way. Up > to now I only used Xilinx FPGAs but the information is also welcome > for Altera's. > > Regards.Article: 132167
Hi Pablo; Problem No.1: You are not able to read and understand error messages. Problem No.2: You have not understood that errors are caused by what's written in the source code. Really now, how do you expect that anyone can help you with the error message when you do not provide the source code that caused the error? When the message says "Index out of range", well, then there must be some index in your sources out of the allowed numerical range. Have a nice synthesis Eilert Pablo schrieb: > ========================================================================= > * Design Hierarchy > Analysis * > ========================================================================= > Analyzing hierarchy for entity <Top_Module> in library <work> > (architecture <struct_1>). > ERROR:Xst - Xst_HdlConst_Imp::GetArrayValueByIndex : index out of > range. > ERROR:Xst - Unexpected error found while building hierarchy. > --> > > Total memory usage is 123236 kilobytes > > Number of errors : 2 ( 0 filtered) > Number of warnings : 0 ( 0 filtered) > Number of infos : 0 ( 0 filtered)Article: 132168
Hi, why would you want to use Virtex-II on a new board? They are more expensive than the newer parts. Check out the various Spartan-3 variants and Virtex-5LX. You need to supply power more or less to all power pins and you definitely should use a board with at least 4 layers. Kolja On 16 Mai, 11:29, "O. Olson" <olson_...@yahoo.it> wrote: > Hi, > > I need to interconnect two or four FPGAs on a PCB, and I am lookin= g > at the prospect of designing these boards myself. If any one has done > this, I would be grateful if you could provide some pointers, > especially links to websites that have this information. I would > probably be using the Xilinx Virtex II > > I don=92t know how to start this =96 but I have a few questions. I= s it > possible for me to simulate the setup between FPGAs connected on a PCB > board. Or is it possible for me to bread board the FPGA =96 I have not > heard of this though. I have looked at the manual of the Virtex II, > and there are a large numbers of pins =96 I have yet to figure out which > pins I need to power at the minimum to get this to work. So I don=92t > want to start laying out a PCB Board immediately. > > I would be requiring significant on board communication =96 but I = don=92t > think I need the Rocket IOs that are available with Virtex4 =96 the > simple LVDS would do for me I guess. Is there a way for me to test > this aspect before actually putting it on the PCB?? > > I have so far used FPGAs on the protyping board that comes with th= e > Spartan Kit from Xilinx. I have also used an Emulation machine with a > couple of FPGAs. In all of this I have never been concerned about the > external connections between FPGAs, so I am new to all of this. > > Any help is welcome.Article: 132169
Thanks for pointing this out that the Virtex II might be costlier than newer parts. I understand that powering up of the power pins should do =96 however there are so many pins and it is possible for me to make a mistake. Is there some tools that can verify this =96 or allow me to simulate this, so that I don=92t make obvious mistakes. I don=92t think that the developers of FPGA Boards do it without some kind of verification. I am new to this stuff so I might be missing something obvious here. Thanks again. O.O. On May 16, 5:16 am, Kolja Sulimma <ksuli...@googlemail.com> wrote: > Hi, > > why would you want to use Virtex-II on a new board? They are more > expensive than the newer parts. Check out the various Spartan-3 > variants and Virtex-5LX. > > You need to supply power more or less to all power pins and you > definitely should use a board with at least 4 layers. > > Kolja >Article: 132170
On 16 mayo, 12:28, backhus <n...@nirgends.xyz> wrote: > Hi Pablo; > Problem No.1: You are not able to read and understand error messages. > Problem No.2: You have not understood that errors are caused by what's > written in the source code. > > Really now, how do you expect that anyone can help you with the error > message when you do not provide the source code that caused the error? > > When the message says "Index out of range", well, then there must be > some index in your sources out of the allowed numerical range. > > Have a nice synthesis > Eilert what I don't understand is why ISE doesn't specify "the error signal/ constant". Usually, ise tells the "error line", but in this kind it doesn't specify anything about a source code (which contains 800 lines).Article: 132171
Actually we check it by eyes. You know, one designs others check! It is a matter of experience I think.Article: 132172
On Thu, 15 May 2008 05:02:07 -0700 (PDT), fazulu deen
<fazulu.vlsi@gmail.com> wrote:
>On May 15, 4:37 pm, Kolja Sulimma <ksuli...@googlemail.com> wrote:
>> througput and area are contradicting optimization goals, therefore you
>> can't minimize both at the same time. Usually you have a throughput
>> goal and then minimize the area under that throughput constraint.
>>
>> Circular buffering is not a meaningful in a hardware implementation.
>>
>> For those parameters you can roughly expect for a virtex 5:
>>
>> Parallel: 400 Msps with 128 multipliers.
>> Serial: 1,5Msps with a single multiplier.
>> There are intermediate forms and you can push parallelization further
>> to compute
>> more than one sample per clock.
>>
>> Note however: While the filter can run at those clock rates it might
>> be difficult to build a
>> complete system at these speeds, let alone do data IO.
>>
>> Kolja Sulimma
>>
>> On 15 Mai, 10:14, fazulu deen <fazulu.v...@gmail.com> wrote:
>>
>> > On May 15, 12:23 pm, Kolja Sulimma <ksuli...@googlemail.com> wrote:
>>
>> > > > Hai,
>>
>> > > > How to implement an FIR filter in FPGA...which approach is a
>> > > > good(linear convolution or circular convolution)which can be optimized
>> > > > area in FPGA...
>> > > > I am trying to follow the canonical structure of FIR filter..
>>
>> > > > regards,
>> > > > faz
>>
>> > hai,
>>
>> > FIR Filter specifications are 256-tap,16-bit input and coefficients
>> > width,linear phase filter..
>>
>> > which type will give high computational speed with minimum area??
>> > 1.Linear convolution
>> > 2.Circular buffering
>> > which is most advisable architecture??
>> > 1.canonical form
>> > 2.Transpose form
>>
>> > regards,
>> > faz
>
>hai,
>
>I got one more doubt in FIR filter implementation...Though the basic
>operation is MAC...It is different from normal convolution operation
>performed manually(with pencil and paper)...
>
>for ex x(n)={1,2,3}
> h(n)={2,1,4}
>Then y(n)=N1+N2-1=3+3-1=5
> y(n)={2,5,12,11,12}
>
>But in canonical form of FIR implementation with the same formula:
>
>y(n)={2,5,12} because shift of x(n) till number of taps(i.e.number of
>filter coefficients which is 3 here)
>
>why this difference??kindly explain..
Because you stopped the second computation too soon, so you only got the
first three samples out.
Try it with the sequence
x(n)=... 0, 0, 0, 1, 2, 3, 0, 0, 0,...
- Brian
Article: 132173On Fri, 16 May 2008 02:29:52 -0700 (PDT), "O. Olson" <olson_ord@yahoo.it> wrote: >Hi, > > I need to interconnect two or four FPGAs on a PCB, and I am looking >at the prospect of designing these boards myself. If any one has done >this, I would be grateful if you could provide some pointers, >especially links to websites that have this information. I would >probably be using the Xilinx Virtex II > > I don’t know how to start this – but I have a few questions. Is it >possible for me to simulate the setup between FPGAs connected on a PCB >board. Or is it possible for me to bread board the FPGA – I have not >heard of this though. I have looked at the manual of the Virtex II, >and there are a large numbers of pins – I have yet to figure out which >pins I need to power at the minimum to get this to work. So I don’t >want to start laying out a PCB Board immediately. Here is one approach to breadboarding with multiple FPGAs, which may allow you to prototype your system before going to your own PCB. http://www.enterpoint.co.uk/moelbryn/overcoat.html Since you are using the Spartan kit, this board http://www.enterpoint.co.uk/moelbryn/raggedstone1.html is probably the most suitable component for the above approach. They can also supply PC104 form-factor boards stackable the same way. http://www.enterpoint.co.uk/moelbryn/hollybush1.html - BrianArticle: 132174
On Fri, 16 May 2008 04:39:40 -0700 (PDT), Pablo <pbantunez@gmail.com> wrote: >On 16 mayo, 12:28, backhus <n...@nirgends.xyz> wrote: >> Hi Pablo; >> Problem No.1: You are not able to read and understand error messages. >> Problem No.2: You have not understood that errors are caused by what's >> written in the source code. >> >> Really now, how do you expect that anyone can help you with the error >> message when you do not provide the source code that caused the error? >> >> When the message says "Index out of range", well, then there must be >> some index in your sources out of the allowed numerical range. >> >> Have a nice synthesis >> Eilert > >what I don't understand is why ISE doesn't specify "the error signal/ >constant". Usually, ise tells the "error line", but in this kind it >doesn't specify anything about a source code (which contains 800 >lines). What I don't understand is how this design passed simulation tests without catching something as basic as an out of range index. But anyway, if you can't find an error in an 800-line source file, split it into two (or more) smaller source files, and find out which one contains the error. Repeat until error found. - Brian
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