Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi all, I'm trying to write a memory controller to make the use of DDR SDRAM possible. It's not going to be a high speed memory controller, but a basic one. The problem i encounter is with implementing the design (place and route stage). The error given says: **************************************************************************************************************************** Place:897 - The following IOBs have been locked (LOC constraint) to the I/O bank 3. They require a voltage reference supply from the VREF pin(s) within the same I/O bank to be available. The following VREF pins are currently locked and can't be used to supply the necessary reference IO Standard: Name = SSTL2_I, VREF = 1.25, VCCO = NR, TERM = NONE List of locked IOB's: SDR_CLK_FB List of occupied VREF Sites: VREF site IOB_X1Y136 is occupied by comp BA<0> **************************************************************************************************************************** I looked up my ucf file, board schematics and pin definitions. If i'm correct, the error is generated by the fact that: IO pins on bank 3 are of type SSTL2_I. Because pin 'SDR_CLK_FB' is a input of type SSTL2_I, which is not a standard type like LVTTL, the bank needs to use a Vref pin to be able to recognize the logic level (1 or 0) of input 'SDR_CLK_FB'. This is then becoming a problem beacause the Vref pin is already used as output signal 'BA0'. Therefor the compiler tells me that this input 'SDR_CLK_FB' on bank 3 cannot be used, in other words "locked to the I/O bank 3". As many of you know, BA0 and BA1 are 'Bank Select' signals used to select 1 of 4 memorybanks in the DDR SDRAM, and to access the 'Mode register (B1=0 and BA0=0) or the 'Extended Mode Register ((B1=0 and BA0=1)'. The 'SDR_CLK_FB' (SDRAM Clock Feedback) signal is used for clock deskew using Virtex-4 DCMs. What can i do to solve this problem? In advance thanks, MauriceArticle: 132176
On May 16, 6:13 am, Enes Erdin <eneser...@gmail.com> wrote: > Actually we check it by eyes. You know, one designs others check! It > is a matter of experience I think. Thanks for your response Enes. So do you guys ever breadboard your stuff =96 or it is direct on the PCB? Thanks again, O.O.Article: 132177
On 16 May=FDs, 06:01, "O. Olson" <olson_...@yahoo.it> wrote: > On May 16, 6:13 am, Enes Erdin <eneser...@gmail.com> wrote: > > > Actually we check it by eyes. You know, one designs others check! It > > is a matter of experience I think. > > Thanks for your response Enes. So do you guys ever breadboard your > stuff - or it is direct on the PCB? > Thanks again, > O.O. Hi, Although I am not so much experienced about these topics in my answer I am referring to -experienced- people who designed boards in the past. Also I must say that I have never been in a design which uses multiple FPGA's but we designed FPGA+Microcontroller boards. As I guess they are more or less the same thing. We directly produce the PCB and correct the errors in the next revisions. Besides power issues (misconnections) there are -I think- more important topics such as using the IO standards. Misconnections in the power pins can be corrected by examining the design multiple times. For example by grouping the power pins in the netlist you can easily route them without error. But if you do not specify your standards before PCB design you can get stuck easily. Only a small example, if you try to use _CC_ pins as output in LVDS -I am referring to Virtex4- you certainly get into trouble but they work perfectly if you do not use LVDS. Unfortuantely I don't know a software checking for these errors at a system level. I don't know whether you know or not these issues but I hope it helps.Article: 132178
On May 16, 7:47 am, Enes Erdin <eneser...@gmail.com> wrote: > On 16 May=FDs, 06:01, "O. Olson" <olson_...@yahoo.it> wrote: > > > On May 16, 6:13 am, Enes Erdin <eneser...@gmail.com> wrote: > > > > Actually we check it by eyes. You know, one designs others check! It > > > is a matter of experience I think. > > > Thanks for your response Enes. So do you guys ever breadboard your > > stuff - or it is direct on the PCB? > > Thanks again, > > O.O. > > Hi, > > Although I am not so much experienced about these topics in my answer > I am referring to -experienced- people who designed boards in the > past. Also I must say that I have never been in a design which uses > multiple FPGA's but we designed FPGA+Microcontroller boards. As I > guess they are more or less the same thing. > > We directly produce the PCB and correct the errors in the next > revisions. Besides power issues (misconnections) there are -I think- > more important topics such as using the IO standards. Misconnections > in the power pins can be corrected by examining the design multiple > times. For example by grouping the power pins in the netlist you can > easily route them without error. But if you do not specify your > standards before PCB design you can get stuck easily. Only a small > example, if you try to use _CC_ pins as output in LVDS -I am referring > to Virtex4- you certainly get into trouble but they work perfectly if > you do not use LVDS. > > Unfortuantely I don't know a software checking for these errors at a > system level. > > I don't know whether you know or not these issues but I hope it helps. Thanks Enes for your information. This is exactly my problem. I have designed PCB Boards with only microcontrollers and some memory chips =96 but this is the first time I am doing FPGAs. So I have Zero Experience. Also I am not aware of the standards =96 that=92s why I was hoping for some kind of tool, before I actually get to putting it on the PCB. I feel that this would be very difficult without a tool. Thanks again. O.O.Article: 132179
> Thanks Enes for your information. This is exactly my problem. I have > designed PCB Boards with only microcontrollers and some memory chips =96 > but this is the first time I am doing FPGAs. So I have Zero > Experience. Also I am not aware of the standards =96 that=92s why I was > hoping for some kind of tool, before I actually get to putting it on > the PCB. I feel that this would be very difficult without a tool. > > Thanks again. > O.O. I think it will be easier than you think :) First try to define your needs than make meetings with your colleagues. Or are you also the guy who writes codes for FPGA? If your design is not too complex it will be easier. Your needs are well-defined in data-sheets and also too many topics are discussed in this group about I/O things. I advise you to look at the pinout specifications first. Also look at the DC and switching characteristics too. As an experience of mine, in one of our designs we needed a 20 A rush-current for an FPGA. And things like this... -enesArticle: 132180
Karl, Thank you. You broke the code, didn't you? Remember, Xilinx specifies that at their absolute maximum ratings, the device is still OK, with no reliability issues. Altera also states that if their parts latch-up (and they do, just search for 'latch up' on their web site), that you, the customer have screwed up, and it is all your fault for "allowing" some overshoot or undershoot.... http://www.altera.com/literature/ds/dsoprq.pdf page 4 (also note how they latch up due to power supply sequencing, etc.) As a good example of how this lack of margin on IOs and latch up will KILL you: PCI at 3.3V REQUIRES reflective wave switching. That means the inputs have overshoot and undershoot BY DESIGN. AustinArticle: 132181
Hi all , I am devoloping software fro microblaze using XPS and I dont have enough resources for a watchdog timer. I want to reset the FPGA after n number of error conditions have occured in software. Whats the most reliable way to reboot the Xilinx Spartan 3 FPGA? Any help will e much appreciated. BR RateArticle: 132182
"Brian Drummond" <brian_drummond@btconnect.com> wrote in message news:n80r245qv80dkgd4tqgehe2ots8ikfgcd9@4ax.com... > On Fri, 16 May 2008 04:39:40 -0700 (PDT), Pablo <pbantunez@gmail.com> > wrote: > >>On 16 mayo, 12:28, backhus <n...@nirgends.xyz> wrote: >>> Hi Pablo; >>> Problem No.1: You are not able to read and understand error messages. >>> Problem No.2: You have not understood that errors are caused by what's >>> written in the source code. >>> >>> Really now, how do you expect that anyone can help you with the error >>> message when you do not provide the source code that caused the error? >>> >>> When the message says "Index out of range", well, then there must be >>> some index in your sources out of the allowed numerical range. >>> >>> Have a nice synthesis >>> Eilert >> >>what I don't understand is why ISE doesn't specify "the error signal/ >>constant". Usually, ise tells the "error line", but in this kind it >>doesn't specify anything about a source code (which contains 800 >>lines). > > What I don't understand is how this design passed simulation tests > without catching something as basic as an out of range index. > > But anyway, if you can't find an error in an 800-line source file, split > it into two (or more) smaller source files, and find out which one > contains the error. > > Repeat until error found. > > - Brian Is this a source error though? The error message quoted was: ERROR:Xst - Xst_HdlConst_Imp::GetArrayValueByIndex : index out of range. ERROR:Xst - Unexpected error found while building hierarchy. This implies that something failed in a function called "GetArrayValueByIndex". This, combined with the lack of a line number, suggests to me that this is an internal run-time error from XST, not a source error, that is being reported.Article: 132183
On May 16, 8:15 am, Enes Erdin <eneser...@gmail.com> wrote: > I think it will be easier than you think :) > > First try to define your needs than make meetings with your > colleagues. Or are you also the guy who writes codes for FPGA? If your > design is not too complex it will be easier. > > Your needs are well-defined in data-sheets and also too many topics > are discussed in this group about I/O things. > > I advise you to look at the pinout specifications first. Also look at > the DC and switching characteristics too. As an experience of mine, in > one of our designs we needed a 20 A rush-current for an FPGA. And > things like this... > > -enes Dear Enes, I am a student and looking into the possibility of taking this up for my thesis. So actually I don=92t have any colleagues. Yes, I would be also writing the code for the FPGAs myself =96 and I am going to try to keep the design simple. However as I am alone, and without much experience in the area, I would first like to get a feel of how complicated this would be. Is there anyway I get hold of the stuff you are referring to: for e.g. I did not expect there would be a 20 A rush-current on an PCB Board. Also I don=92t have much experience with LVDS =96 though I know what it is and have seen others use it. So is there some place I can dig for the concerns that you are brining up. Thanks again. O.O.Article: 132184
Rate, Why do you need to reset the FPGA after some number of software errors? Won't the software errors just re-occur? How does resetting (restarting) the FPGA affect the software? To start over, forgetting everything, the best way is to pull PROG (low). Tying an output of the same FPGA to the PROG line input is not something we can easily recommend, as unless we really have it tested, that is a race condition (as the first thing that happens when PROG is pulled low, is all IOs go tristate!). I believe this works for some parts...and perhaps Peter will chime in and let me know which one(s). AustinArticle: 132185
On Fri, 16 May 2008 14:36:07 GMT, "David Spencer" <davidmspencer@verizon.net> wrote: >Is this a source error though? The error message quoted was: > >ERROR:Xst - Xst_HdlConst_Imp::GetArrayValueByIndex : index out of >range. >ERROR:Xst - Unexpected error found while building hierarchy. > >This implies that something failed in a function called >"GetArrayValueByIndex". This, combined with the lack of a line number, >suggests to me that this is an internal run-time error from XST, not a >source error, that is being reported. > I think it's likely that there is a problem with the source ( maybe something not synthesizable which didn't get detected earlier) which is causing a late stage in the processing to give an error. I would think an industrial strength synthesizer would be able to give a better error message earlier.Article: 132186
O. Olson wrote: > Hi, > > I need to interconnect two or four FPGAs on a PCB, and I am looking > at the prospect of designing these boards myself. If any one has done > this, I would be grateful if you could provide some pointers, > especially links to websites that have this information. I would > probably be using the Xilinx Virtex II > > I don’t know how to start this – but I have a few questions. Is it > possible for me to simulate the setup between FPGAs connected on a PCB > board. Or is it possible for me to bread board the FPGA – I have not > heard of this though. I have looked at the manual of the Virtex II, > and there are a large numbers of pins – I have yet to figure out which > pins I need to power at the minimum to get this to work. So I don’t > want to start laying out a PCB Board immediately. > > I would be requiring significant on board communication – but I don’t > think I need the Rocket IOs that are available with Virtex4 – the > simple LVDS would do for me I guess. Is there a way for me to test > this aspect before actually putting it on the PCB?? > > I have so far used FPGAs on the protyping board that comes with the > Spartan Kit from Xilinx. I have also used an Emulation machine with a > couple of FPGAs. In all of this I have never been concerned about the > external connections between FPGAs, so I am new to all of this. > > Any help is welcome. > > Thanks a lot. > O.O. Just to step back a tick, are you sure that what you need is interconnected FPGAs? If the design you're talking about could be made to work with two Virtex IIs, then you can probably get it all into one larger Virtex-4 or 5 and save yourself a whole lot of grief. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 132187
hello , i v some questions about frame format in the bitstream of virtex 5 : * frame = 41 words = (41* 32) bits = 1312 bits , i would like to know the format of this frame ; i mean wich comes first clk config ?Bram config ? ... tell me about it * how can i set the beginning of the first frame to '1' ? (rbt file) * why serial debug is desabled for encrypted bitstream ? Thank you for help .Article: 132188
> Dear Enes, > > I am a student and looking into the possibility of taking this up = for > my thesis. So actually I don=92t have any colleagues. Yes, I would be > also writing the code for the FPGAs myself =96 and I am going to try to > keep the design simple.... Now everything changes. I am also an Msc. student and currently doing a VHDL work but, IMHO, doing something in a master (I don't know PhD) in both hardware and software -I am looking at VHDL like software- will be very tiring. If you try to observe some characteristics of the FPGA's I don't have any idea about it but for me buy a kit and continue your work on it. Of course these are my thoughts. And if we talk about LVDS it is not different from usual signals only two wires will be routed and you will tell the FPGA that these pins are LVDS signals, that is instead of a LVTTL or LVCMOS buffer you will use an LVDS buffer that's all. I hope you success -enesArticle: 132189
dajjou, Why? AustinArticle: 132190
On May 16, 10:34 am, Rob Gaddi <rga...@technologyhighland.com> wrote: > > Just to step back a tick, are you sure that what you need is > interconnected FPGAs? If the design you're talking about could be made > to work with two Virtex IIs, then you can probably get it all into one > larger Virtex-4 or 5 and save yourself a whole lot of grief. > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order Thank you for your reply Rob. I am a student. Actually I do not know what the design is going to be. We are trying to implement some sort of multiplexing/routing strategy to increase/facilitate the interconnections between designs on FPGAs. Thank you for your suggestion though. O.O.Article: 132191
On May 16, 2:29 am, "O. Olson" <olson_...@yahoo.it> wrote: > Hi, > > I need to interconnect two or four FPGAs on a PCB, and I am lookin= g > at the prospect of designing these boards myself. If any one has done > this, I would be grateful if you could provide some pointers, > especially links to websites that have this information. I would > probably be using the Xilinx Virtex II > > I don=92t know how to start this =96 but I have a few questions. I= s it > possible for me to simulate the setup between FPGAs connected on a PCB > board. Or is it possible for me to bread board the FPGA =96 I have not > heard of this though. I have looked at the manual of the Virtex II, > and there are a large numbers of pins =96 I have yet to figure out which > pins I need to power at the minimum to get this to work. So I don=92t > want to start laying out a PCB Board immediately. > > I would be requiring significant on board communication =96 but I = don=92t > think I need the Rocket IOs that are available with Virtex4 =96 the > simple LVDS would do for me I guess. Is there a way for me to test > this aspect before actually putting it on the PCB?? > > I have so far used FPGAs on the protyping board that comes with th= e > Spartan Kit from Xilinx. I have also used an Emulation machine with a > couple of FPGAs. In all of this I have never been concerned about the > external connections between FPGAs, so I am new to all of this. > > Any help is welcome. > > Thanks a lot. > O.O. BTDT. I built a board with 16 FPGAs on it years ago because there just wasn't one big enough to do the job. Last time I used the Xilinx 4000 series, I had to use 3 parts to fit all my logic. The hardest part is chip to chip communication. Even with a master (board) clock, you need to treat each chip as being in its own clock domain. And inter-chip communication is much slower than intra-chip. The current spike as they all come out of program mode can't be ignored either. (At least I was not able to ignore it). Programming all of the parts off of one configuration device seemed to cause them to exit program mode sequentially, distributing the spike a little. Good luck, G. If you program all of the devices off of oneArticle: 132192
On May 16, 8:07=A0am, austin <aus...@xilinx.com> wrote: > Rate, > > Why do you need to reset the FPGA after some number of software errors? > =A0Won't the software errors just re-occur? =A0How does resetting > (restarting) the FPGA affect the software? > > To start over, forgetting everything, the best way is to pull PROG > (low). =A0Tying an output of the same FPGA to the PROG line input is not > something we can easily recommend, as unless we really have it tested, > that is a race condition (as the first thing that happens when PROG is > pulled low, is all IOs go tristate!). > > I believe this works for some parts...and perhaps Peter will chime in > and let me know which one(s). > > Austin To re-configure, you must pull down PROG for a certain length of time,expressed in microseconds.If you use one FPGA output to do this, you face a dilemma: Once reconfiguration starts, every output is being 3-stated, which violated the min PRG=3DLow time requirement.In older parts, this self-triggering worked reliably "by design", since both reconfiguration and 3-stating were controlled by a common latch. Once set, there was no way to stop configuration. This nice design was changed in some of the Virtex and probably also in some of the Spartan parts, just because the rationale for the previous design methodology was forgotten (its impact had never been officially documented anyhow). I'll try to find out, once and for all, which parts are designed which way. In future parts we intend to re-institute the old design method, since it offers one unbeatable advantage... Peter AlfkeArticle: 132193
Hi, I have been running my designs on ISE 9.2i for a virtex-5 LX110t FPGA. The time taken by the tool to complete a full synthesis and implementation is a little over 3 hours on a Core2 Quad CPU running at 2.4 GHz with 2GB of RAM and Windows XP Pro 32-bit edition. I have tried using ISE 10.1 and have observed that the time taken to run the same design is less than 2 hrs. I have read the threads on Xilinx about using more memory, I will be upgrading my memory to 3 GB or more. I would like to get some recommendations for a system configuration in terms of the best suitable processor, memory and any other useful configuration to bring down the synthesis-map-par run- time. The other discussion threads that I went through were either old or did not point to an optimal configuration. Your inputs will be helpful and is highly appreciated. Thanks!Article: 132194
> About the cable, is 5 meters in length. The problem is that there is > an intermediate sub-D connector which is joining two 2.5 m cables I'm not sure you can daisy chain Camera Link Cables like this. Are you doing that for the frame grabber set up? There was something about the Camera Link spec that made me think that you can't connect them like other cables, besides the fact they don't have male/female connectors. Your signals maybe mirrored. > idest ? Brad Smallridge AiVisionArticle: 132195
In article <g0k5da$7nq14@cnn.xsj.xilinx.com>,
austin <austin@xilinx.com> wrote:
>Altera also states that if their parts latch-up (and they do, just
>search for 'latch up' on their web site), that you, the customer have
>screwed up, and it is all your fault for "allowing" some overshoot or
>undershoot....
>http://www.altera.com/literature/ds/dsoprq.pdf
>page 4 (also note how they latch up due to power supply sequencing, etc.)
Careful, this note is quite old (1999). Newer parts do not have power
sequencing requirements: read the hot socketing section of any recent Altera
chip device handbook.
On the other hand, the 65nm Cyclone-III/Stratix-III 3.3v issue still
remains. Basically if you want to use 3.3V PCI on Cyclone-III, use a 3.0V
power supply.
2.5V is increasingly becomming the new 3.3V (or 5.0V).
--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 132196Joseph, Good point (on sequencing). All I was really trying to point out is that with the shrinking geometries, IO is more often in commonly available foundry processes now using 180nm transistors instead of 250, or 350 nm (.25u or .35u). And unless the gate thickness is kept as it was in the .35u device, the transistors will just "punch through" (gate rupture, HCI, TDDB, etc.). AustinArticle: 132197
On May 16, 12:17=A0am, wicky <wicky.zh...@gmail.com> wrote: > Hi all, > > I need a SATA hard disk support through pci bus of my powerpc embedded > system. After search a lot here and google, i think there is 4 ways: > > 1: use a PCI to SATA controller, but i can't find the industrial > temperature class ASIC. > > 2: use a PATA to SATA controller, then design the PCI to IDE in an > FPGA, but the same question of temperature. > > 3: use the Virtex5 GTP and SATA ipcore, what an expensive sulution? > > 4: use the spartan3 FPGA with a SATA PHY, can I purchase the > industrial class PHY ASIC? > > Hope anyone can give me a hand, Thanks a lot. > > Best Regards, > > Wicky How about this problem? Many thanks. Best Regards, WickyArticle: 132198
On May 16, 3:09=A0pm, karthick <karthick...@gmail.com> wrote: > We are using SPARTAN 3 E FPGA. I would like to know what is the > difference between ISE 8.2i and ISE 9.2i with respect to the micro > blaze core. > We are able to access the FLASH and RTC via SPI in 8.2i whereas the > same is not possible in 9.2i. > So we would like to know what is the difference between 8.2i and 9.2i. The most diffirence is that the new version of MicroBlaze use the unify PLB46 bus and OPB bus is no longer available, thus your opb peripherials need to be updated to PLB46. Best Regards, WickyArticle: 132199
On Fri, 16 May 2008 05:54:20 -0700 (PDT), mspiegels@gmail.com wrote: >Hi all, >Because pin 'SDR_CLK_FB' is a >input of type SSTL2_I, which is not a standard type like LVTTL, the >bank needs to use a Vref pin to be able to recognize the logic level >(1 or 0) of input 'SDR_CLK_FB'. This is then becoming a problem >beacause the Vref pin is already used as output signal 'BA0'. >What can i do to solve this problem? If you can rewire the PCB, then avoid the conflicting pinout. If you can't, then ... note, the only pin LISTED as requiring SSTL2-I input type in this bank is your own clock feedback pin. So verify that it is only connected to a spare clock output (e.g. by reading the board schematics) and, if so, set it to another input standard, e.g. LVTTL or LVCMOS. - Brian
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z