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Uchenna, at least on the XSA100 you can change the clock to something other than 100MHz and then XTEST won't work until you change it back. Given the message about the bad CPLD, however, it is not likely to be the clock. -- JecelArticle: 132126
When starting an EDK project, there is an option to download XBD files from the board vendor. After you have downloaded it (or written one), how do you get the EDK to use it? I've tried adding it to the 'board' directory(even though the documentation explicitly says that it in named boards), and I have searched in vain for the command to change the library search path... Thanks & regards, G.Article: 132127
Hai, How to implement an FIR filter in FPGA...which approach is a good(linear convolution or circular convolution)which can be optimized area in FPGA... I am trying to follow the canonical structure of FIR filter.. regards, fazArticle: 132128
I respond as this newsgroup responds to all questions of this type (we need an FAQ): This highly depends on - throughput - FIR-length - word width - other constraints (linear phase filter?, many 0 coefficients?) Try to ask again. Kolja Sulimma On 15 Mai, 06:31, fazulu deen <fazulu.v...@gmail.com> wrote: > Hai, > > How to implement an FIR filter in FPGA...which approach is a > good(linear convolution or circular convolution)which can be optimized > area in FPGA... > I am trying to follow the canonical structure of FIR filter.. > > regards, > fazArticle: 132129
anybody ever used the SPI core for microblaze? I found as example only a montevista spi driver which basically is doing all the bitbanging at a low level and uses it's own fifos, i.e. not using the xspi routines described in the xilinx_drivers reference. Are there any problems with the xilinx routines? Anybody some examples of usage? TacoArticle: 132130
On May 15, 12:23=A0pm, Kolja Sulimma <ksuli...@googlemail.com> wrote: > I respond as this newsgroup responds to all questions of this type (we > need an FAQ): > > This highly depends on > - throughput > - FIR-length > - word width > - other constraints (linear phase filter?, many 0 coefficients?) > > Try to ask again. > > Kolja Sulimma > > On 15 Mai, 06:31, fazulu deen <fazulu.v...@gmail.com> wrote: > > > Hai, > > > How to implement an FIR filter in FPGA...which =A0approach is a > > good(linear convolution or circular convolution)which can be optimized > > area in FPGA... > > I am trying to follow the canonical structure of FIR filter.. > > > regards, > > faz hai, FIR Filter specifications are 256-tap,16-bit input and coefficients width,linear phase filter.. which type will give high computational speed with minimum area?? 1.Linear convolution 2.Circular buffering which is most advisable architecture?? 1.canonical form 2.Transpose form regards, fazArticle: 132131
Hi, I am drawing schematics for a new system that uses a Cyclone 3 FPGA. I have some LVTTL (3V3) signals on which I would like to use a 50R series termination. The Cyclone 3 has two possible 50R series terminations: - not calibrated - calibrated The handbook doesn't specify the standards that can be used with the calibrated termination. Has anybody got this data? The handbook mentions that the uncalibrated termination can be used with 3.0V LVTTL, it doesn't mention 3.3V LVTTL, is this a typo -or- is 3.3V LVTTL with on-chip termination not supported? thanks and best regards, Karel DArticle: 132132
On May 14, 6:36 pm, Dave <dhsch...@gmail.com> wrote: > On May 14, 11:47 am, Dave Pollum <vze24...@verizon.net> wrote: > > > > > On May 14, 7:09 am, Zorjak <Zor...@gmail.com> wrote: > > > > Hi!!! > > > > I started recently with the xilinx software and these days I am trying > > > to become more familiar with the modelsim and ise. I wanted to test > > > some basic counter simulation in modelsim so I used this simple code > > > > counter design file > > > > library ieee ; > > > use ieee.std_logic_1164.all; > > > use ieee.std_logic_unsigned.all; > > > > entity counter is > > > port( clk: in std_logic; > > > reset: in std_logic; > > > enable: in std_logic; > > > count: out std_logic_vector(3 downto 0) > > > ); > > > end counter; > > > > architecture behav of counter is > > > signal pre_count: std_logic_vector(3 downto 0); > > > begin > > > process(clk, enable, reset) > > > begin > > > if reset = '1' then > > > pre_count <= "0000"; > > > elsif (clk='1' and clk'event) then > > > if enable = '1' then > > > pre_count <= pre_count + "1"; > > > end if; > > > end if; > > > end process; > > > count <= pre_count; > > > end behav; > > > > testbench > > > > library ieee ; > > > use ieee.std_logic_1164.all; > > > use ieee.std_logic_unsigned.all; > > > use ieee.std_logic_textio.all; > > > use std.textio.all; > > > > entity counter_tb is > > > end; > > > > architecture counter_tb of counter_tb is > > > > component counter > > > port ( count : out std_logic_vector(3 downto 0); > > > clk : in std_logic; > > > enable: in std_logic; > > > reset : in std_logic); > > > end component ; > > > > signal clk : std_logic := '0'; > > > signal reset : std_logic := '0'; > > > signal enable : std_logic := '0'; > > > signal count : std_logic_vector(3 downto 0); > > > > begin > > > > dut : counter > > > port map ( > > > count => count, > > > clk => clk, > > > enable=> enable, > > > reset => reset ); > > > > clock : process > > > begin > > > clk<='0'; > > > wait for 5 ns; > > > clk<='1'; > > > wait for 5 ns; > > > end process clock; > > > > stimulus : process > > > begin > > > > wait for 5 ns; reset <= '1'; > > > wait for 4 ns; reset <= '0'; > > > wait for 4 ns; enable <= '1'; > > > wait; > > > end process stimulus; > > > > but my simulation doesn't give right results. (I am getting U state on > > > all inputs). I am trying to find my mistake for more than 4 hours so > > > please if someone could help me please do it. I have defined new > > > project, I have compiled files and when I start simulation this > > > results repeat over and over again. I fell that this is stupid little > > > mistake but I can't find it no matter what. > > > > Thanks for any kind of help > > > Zoran > > > Your clock process will only produce -1- clock cycle. You need the > > clock to be in a loop: > > > clock : process > > begin > > loop > > clk<='0'; > > wait for 5 ns; > > clk<='1'; > > wait for 5 ns; > > end loop; > > end process clock; > > > -Dave Pollum > > The clock process is Ok as is - there doesn't need to be a loop. Since > there's no 'wait' statement at the end of the process, execution will > go back to the top of the process on the next delta cycle. > > This stimulus process could use some work, though. Try defining the > reset and enable signals from the beginning, like this: > > stimulus : process > begin > reset <= '0'; > enable <= '0'; > wait for 5 ns; reset <= '1'; > wait for 4 ns; reset <= '0'; > wait for 4 ns; enable <= '1'; > wait; > end process stimulus; > > Otherwise, the reset and enable signals are 'U" until you drive them > in the testbench. This could cause U's and X's to propagate through > your DUT, and the feedback in the counter could make them last > forever. > > Hope this helps, > > Dave Thanks to everybody for the help. As I said I am beginner with modelsim so I was making mistake when I was starting my simulation. After I was starting simulation I was choosing both files (design and testbench) and I should chose only testbench file. So this was problem. At the end I tried to select only testbench file and it worked fine and there was no end of my happiness:):):) One more time, thanks to everyone ZoranArticle: 132133
"Jon Elson" <elson@wustl.edu> wrote in message news:482B33EB.6080206@wustl.edu... > > > John_H wrote: >> Aren't we? :-) > > I did mine in 2001, been happy with it since. But, it is proprietary, > and I don't intend to publish it. (sorry) > > Jon > Jon, I have discovered a truly marvellous encoder, which this newsgroup is too narrow to contain. Cheers, Syms. p.s. http://en.wikipedia.org/wiki/Fermat's_last_theorem#Fermat.27s_Last_Theorem_from_a_comment_in_a_marginArticle: 132134
througput and area are contradicting optimization goals, therefore you can't minimize both at the same time. Usually you have a throughput goal and then minimize the area under that throughput constraint. Circular buffering is not a meaningful in a hardware implementation. For those parameters you can roughly expect for a virtex 5: Parallel: 400 Msps with 128 multipliers. Serial: 1,5Msps with a single multiplier. There are intermediate forms and you can push parallelization further to compute more than one sample per clock. Note however: While the filter can run at those clock rates it might be difficult to build a complete system at these speeds, let alone do data IO. Kolja Sulimma On 15 Mai, 10:14, fazulu deen <fazulu.v...@gmail.com> wrote: > On May 15, 12:23 pm, Kolja Sulimma <ksuli...@googlemail.com> wrote: > > > > > > Hai, > > > > How to implement an FIR filter in FPGA...which approach is a > > > good(linear convolution or circular convolution)which can be optimized > > > area in FPGA... > > > I am trying to follow the canonical structure of FIR filter.. > > > > regards, > > > faz > > hai, > > FIR Filter specifications are 256-tap,16-bit input and coefficients > width,linear phase filter.. > > which type will give high computational speed with minimum area?? > 1.Linear convolution > 2.Circular buffering > which is most advisable architecture?? > 1.canonical form > 2.Transpose form > > regards, > fazArticle: 132135
Hello, I've implemented a camera link deserializer interface based on a virtex 4 FPGA (using ML402 development board). I'm using the LVDS 2.5 V inputs of the board and a cable with one end open. The module works fine when i use a short cable. However, my application needs to use a long cable (with a discontinuity) which doesn't work so fine. The thing is that I guess there is a match problem in the board reception side, because when i represent the eye diagram of the incoming signals (once it's converted to LVTTL) and the long cable is used, it's really bad. I know that it is possible to use this long cable because it works with a generic frame grabber. I've tried using the DCI (Digital Control impedance) of the FPGA, LVDS_EXT standard... but i don't reach a solution... If someone could have some experience in this field... Thank very much in advace !Article: 132136
On 15 May=FDs, 04:41, Crhono...@gmail.com wrote: > Hello, > > I've implemented a camera link deserializer interface based on a > virtex 4 FPGA (using ML402 development board). I'm using the LVDS 2.5 > V inputs of the board and a cable with one end open. > > The module works fine when i use a short cable. However, my > application needs to use a long cable (with a discontinuity) which > doesn't work so fine. The thing is that I guess there is a match > problem in the board reception side, because when i represent the eye > diagram of the incoming signals (once it's converted to LVTTL) and the > long cable is used, it's really bad. > > I know that it is possible to use this long cable because it works > with a generic frame grabber. > I've tried using the DCI (Digital Control impedance) of the FPGA, > LVDS_EXT standard... but i don't reach a solution... > > If someone could have some experience in this field... > > Thank very much in advace ! Hi, What is the length of your cable? Do you know the impedance of your cable? Mismatch can also accur because of the cable. As an example I have used LVDS signaling through a 3m. cable with 100 Mbps successfully.Article: 132137
On May 15, 4:37=A0pm, Kolja Sulimma <ksuli...@googlemail.com> wrote:
> througput and area are contradicting optimization goals, therefore you
> can't minimize both at the same time. Usually you have a throughput
> goal and then minimize the area under that throughput constraint.
>
> Circular buffering is not a meaningful in a hardware implementation.
>
> For those parameters you can roughly expect for a virtex 5:
>
> Parallel: 400 Msps with 128 multipliers.
> Serial: 1,5Msps with a single multiplier.
> There are intermediate forms and you can push parallelization further
> to compute
> more than one sample per clock.
>
> Note however: While the filter can run at those clock rates it might
> be difficult to build a
> complete system at these speeds, let alone do data IO.
>
> Kolja Sulimma
>
> On 15 Mai, 10:14, fazulu deen <fazulu.v...@gmail.com> wrote:
>
> > On May 15, 12:23 pm, Kolja Sulimma <ksuli...@googlemail.com> wrote:
>
> > > > Hai,
>
> > > > How to implement an FIR filter in FPGA...which =A0approach is a
> > > > good(linear convolution or circular convolution)which can be optimiz=
ed
> > > > area in FPGA...
> > > > I am trying to follow the canonical structure of FIR filter..
>
> > > > regards,
> > > > faz
>
> > hai,
>
> > FIR Filter specifications are 256-tap,16-bit input and coefficients
> > width,linear phase filter..
>
> > which type will give high computational speed with minimum area??
> > 1.Linear convolution
> > 2.Circular buffering
> > which is most advisable architecture??
> > 1.canonical form
> > 2.Transpose form
>
> > regards,
> > faz
hai,
I got one more doubt in FIR filter implementation...Though the basic
operation is MAC...It is different from normal convolution operation
performed manually(with pencil and paper)...
for ex x(n)=3D{1,2,3}
h(n)=3D{2,1,4}
Then y(n)=3DN1+N2-1=3D3+3-1=3D5
y(n)=3D{2,5,12,11,12}
But in canonical form of FIR implementation with the same formula:
y(n)=3D{2,5,12} because shift of x(n) till number of taps(i.e.number of
filter coefficients which is 3 here)
why this difference??kindly explain..
regards,
faz
Article: 132138Also I must say that I was also unsuccessful through a 5m. cable with a very bad one which includes several connectors and a long solid flat cable in it.Article: 132139
Hi, I have read several appnotes about serial interfaces in Xilinx FPGAs. Most of them use a DCM on the receiving side to phase shift and/or multiply the incoming clock. My problem is that I don't have any global clock pins available, only clock capable. So when I use a DCM, XST gives me an error that I am using a non-optimal IOB site for clock input. The error can be reduced to a warning be setting a constraint that allows the non-optimal clock input. What are the implications of using the non-optimal IOB for clock input? Would it be better to try to find a solution that does not include a DCM in the receiver?Article: 132140
Have you instantiated the differential input buffers (IBUFDS) with the diffterm generic set to true?Article: 132141
Hello,
During implementation I get the following fitter warning:
Warning: Following 1 pins must use external clamping diodes.
Info: Pin Nios2Processor:\b_uP_MemInt_I2C:i_Nios2Processor|
epcs_controller:the_epcs_controller|
tornado_epcs_controller_atom:the_tornado_epcs_controller_atom|
the_tornado_spiblock~ALTERA_DATA0 uses I/O standard 2.5 V at N7
My design uses an EPCS flash (powered @ 3V3) and it uses pin N7, which
is situated in a 3.3V bank.
This is confusing:
- The handbook uses a clamping diode to Vccio, in my case that is 3.3V
- Quartus tells me to add a clamping diode, it doesn't specify to
which voltage but I guess that it is the 2V5
- Is the input buffer for the data0 pin powered by Vccio (3V3) or by
Vcca (2V5) ?
Can you clarify this?
thanks and best regards,
Karel D
Article: 132142Karel, Cyclone III does not have 3.3v, it only has "3.0 volt IO" -- a new "standard" from Altera! (Stratix III is the same). Why? Because TSMC does not have a process that has the small fast core transistors, and the larger 3.3v IO transistors. So, 3.3v is now going the way of 5.0v -- gone. Xilinx still has 3.3v IO at 65nm in Virtex 5, but that is only because we have our own triple oxide process "built to order" by two fabs, UMC and Toshiba. Good luck! AustinArticle: 132143
Hi all, I need a SATA hard disk support through pci bus of my powerpc embedded system. After search a lot here and google, i think there is 4 ways: 1: use a PCI to SATA controller, but i can't find the industrial temperature class ASIC. 2: use a PATA to SATA controller, then design the PCI to IDE in an FPGA, but the same question of temperature. 3: use the Virtex5 GTP and SATA ipcore, what an expensive sulution? 4: use the spartan3 FPGA with a SATA PHY, can I purchase the industrial class PHY ASIC? Hope anyone can give me a hand, Thanks a lot. Best Regards, WickyArticle: 132144
On May 15, 7:41=A0pm, Crhono...@gmail.com wrote: > Hello, > > I've implemented a camera link deserializer interface based on a > virtex 4 FPGA (using ML402 development board). I'm using the LVDS 2.5 > V inputs of the board and a cable with one end open. > > The module works fine when i use a short cable. However, my > application needs to use a long cable (with a discontinuity) which > doesn't work so fine. The thing is that I guess there is a match > problem in the board reception side, because when i represent the eye > diagram of the incoming signals (once it's converted to LVTTL) and the > long cable is used, it's really bad. > > I know that it is possible to use this long cable because it works > with a generic frame grabber. > I've tried using the DCI (Digital Control impedance) of the FPGA, > LVDS_EXT standard... but i don't reach a solution... > > If someone could have some experience in this field... > > Thank very much in advace ! I think the length and the bps is the key factor, i am now doing the saming work, could you send me you codes for reference? thanks a lot. Best Regards, WickyArticle: 132145
On May 14, 4:23 pm, ghel...@lycos.com wrote: > When starting an EDK project, there is an option to download XBD files > from the board vendor. > > After you have downloaded it (or written one), how do you get the EDK > to use it? > > I've tried adding it to the 'board' directory(even though the > documentation explicitly says that it in named boards), and I have > searched in vain for the command to change the library search path... > > Thanks & regards, > G. Update: I have found the method to change the library search path. This appears to be broken (EDK-9.1.2). I found the Xilinx forum. There are a number of people asking similar questions, but no answers are posted. This should be real easy. It's very frustrating that it's not working, and the documentation for how to use it assumes that you already know how. G.Article: 132146
Hello, If you do not use a global clock input, then the worst case skews and delays are no longer guaranteed. If you use the phase shift in the DCM to find the center of the "eye" in order to sample the received data, this means a single fixed phase shift value may not work for all silicon. If you use the variable "find the center" design which sets the phase shift for each device after a training interval, then this will always find the best sampling point, and the added skew or delay of using a non-global input will not matter. AustinArticle: 132147
I have camera link working at 40MHz, a 2 meter cable,
VHDL code using the ISERDES Xilinx primitives, a ML402
with a daughter board of my own design that had matched
length traces.
I did not use Digital Control Impedance.
What do you mean "one end open"?
Setting up the ISERDES,the terminated IOBs, and your
DCMs are all critical:
from UCF file:
# CAMERA LINK 2 INPUT
NET "cam2_in<0>" LOC = "AC20" ; # X0NEG
NET "cam2_in<1>" LOC = "AB20" ; # X0POS
NET "cam2_in<2>" LOC = "AD21" ; # X1NEG
NET "cam2_in<3>" LOC = "AE21" ; # X1POS
NET "cam2_in<4>" LOC = "AD20" ; # X2NEG
NET "cam2_in<5>" LOC = "AE20" ; # X2POS
NET "cam2_in<6>" LOC = "AC19" ; # CLKNEG
NET "cam2_in<7>" LOC = "AD19" ; # CLKPOS
NET "cam2_in<8>" LOC = "AB18" ; # X3NEG
NET "cam2_in<9>" LOC = "AC18" ; # X3POS
from VHDL:
attribute DIFF_TERM : boolean;
attribute DIFF_TERM of cam2_x0_ibufd_inst:label is true;
attribute DIFF_TERM of cam2_x1_ibufd_inst:label is true;
attribute DIFF_TERM of cam2_x2_ibufd_inst:label is true;
attribute DIFF_TERM of cam2_x3_ibufd_inst:label is true;
attribute DIFF_TERM of cam2_xclk_ibufd_inst:label is true;
attribute DIFF_TERM of serial_from_cam2_IBUFDS:label is true;
cam2_xclk_ibufd_inst : IBUFDS
port map (
O => cam2_xclk,
I => cam2_in(7),
IB => cam2_in(6) );
cam2_x0_ibufd_inst : IBUFDS
port map (
O => cam2_x0,
I => cam2_in(1),
IB => cam2_in(0) );
cam2_x1_ibufd_inst : IBUFDS
port map (
O => cam2_x1,
I => cam2_in(3),
IB => cam2_in(2) );
cam2_x2_ibufd_inst : IBUFDS
port map (
O => cam2_x2,
I => cam2_in(5),
IB => cam2_in(4) );
cam2_x3_ibufd_inst : IBUFDS
port map (
O => cam2_x3,
I => cam2_in(9),
IB => cam2_in(8) );
iserdes_master : ISERDES
generic map (
BITSLIP_ENABLE => FALSE, -- TRUE FALSE
DATA_RATE => "SDR", -- DDR SDR
DATA_WIDTH => 7, -- DDR 4,6,8,10 SDR 2,3,4,5,6,7,8
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "MEMORY", -- model - "MEMORY" or "NETWORKING"
IOBDELAY => "NONE", -- delay chain
"NONE","IBUF","IFD","BOTH"
IOBDELAY_TYPE => "DEFAULT", -- tap delay "DEFAULT",
"FIXED","VARIABLE"
IOBDELAY_VALUE => 0, -- initial tap delay 0 to 63
NUM_CE => 1, -- clock enables 1,2
SERDES_MODE => "MASTER", -- "MASTER" or "SLAVE"
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0')
port map (
O => open,
Q1 => dout(0),
Q2 => dout(1),
Q3 => dout(2),
Q4 => dout(3),
Q5 => dout(4),
Q6 => dout(5),
SHIFTOUT1 => shift1,
SHIFTOUT2 => shift2,
BITSLIP => '0',
CE1 => '1',
CE2 => '1',
CLK => fclk,
CLKDIV => xclk,
D => din,
DLYCE => dlyce,
DLYINC => dlyinc,
DLYRST => dlyrst,
OCLK => oclk,
REV => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SR => reset );
iserdes_slave : ISERDES
generic map (
BITSLIP_ENABLE => FALSE, -- TRUE FALSE
DATA_RATE => "SDR", -- DDR SDR
DATA_WIDTH => 7, -- DDR 4,6,8,10 SDR 2,3,4,5,6,7,8
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "MEMORY", -- model - "MEMORY" or "NETWORKING"
IOBDELAY => "NONE", -- delay chain
"NONE","IBUF","IFD","BOTH"
IOBDELAY_TYPE => "DEFAULT", -- tap delay "DEFAULT",
"FIXED","VARIABLE"
IOBDELAY_VALUE => 0, -- initial tap delay 0 to 63
NUM_CE => 1, -- clock enables 1,2
SERDES_MODE => "SLAVE", -- "MASTER" or "SLAVE"
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0')
port map (
O => open,
Q1 => open,
Q2 => open,
Q3 => dout(6),
Q4 => dout(7),
Q5 => dout(8),
Q6 => dout(9),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
BITSLIP => '0',
CE1 => '1',
CE2 => '1',
CLK => fclk,
CLKDIV => xclk,
D => '0',
DLYCE => dlyce,
DLYINC => dlyinc,
DLYRST => dlyrst,
OCLK => oclk,
REV => '0',
SHIFTIN1 => shift1,
SHIFTIN2 => shift2,
SR => reset );
Brad Smallridge
AiVision
<Crhonos04@gmail.com> wrote in message
news:aaab7574-dcb3-49ce-a927-9ecb5926d1a0@34g2000hsf.googlegroups.com...
> Hello,
>
> I've implemented a camera link deserializer interface based on a
> virtex 4 FPGA (using ML402 development board). I'm using the LVDS 2.5
> V inputs of the board and a cable with one end open.
>
> The module works fine when i use a short cable. However, my
> application needs to use a long cable (with a discontinuity) which
> doesn't work so fine. The thing is that I guess there is a match
> problem in the board reception side, because when i represent the eye
> diagram of the incoming signals (once it's converted to LVTTL) and the
> long cable is used, it's really bad.
>
> I know that it is possible to use this long cable because it works
> with a generic frame grabber.
> I've tried using the DCI (Digital Control impedance) of the FPGA,
> LVDS_EXT standard... but i don't reach a solution...
>
> If someone could have some experience in this field...
>
> Thank very much in advace !
Article: 132148Dear All, Are there any Open source Core generators available? I am looking for FIR and FFT Core generators but also wonder if open source generators for other functions exist. Thanks in AdvanceArticle: 132149
Jeff Cunningham wrote: > Is it still true that BRAM arrays with different width ports cannot be > inferred? > > Also, are the BRAM parity bits usable with inference, i.e. can you infer > a 36 bit wide memory into a single BRAM? > > Coregen left a bad taste in my mouth last time I tried to use it for > BRAM. Instead I find directly instantiating BRAM instances with use of > the VHDL generate statement to be fairly powerful and flexible. > > -Jeff I believe so. I made my own dual port ram component that looks at the data and address port widths on both ports to figure out the construction of the composite memory. It is limited in depth to the BRAM depths (up to 16K), as it doesn't use any multiplexers. It also accepts initial ram values as an array of integers and takes care of splitting those up among parallelled BRAMs as needed. It took a while to develop and test the component, but since I do as many designs as I do, it has more than paid for itself in time saved on subsequent designs.
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