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On Jul 8, 9:46 am, Nemesis <gnemesis2...@gmail.com> wrote: > I'm using the DCM instantiation reported below, on a Virtex4fx60 > target. > I have two different boards (ICS-8550) the differ only for the > ruggedization level, the boards are almost the same and so should be > the FPGAs, maybe only the stepping level is different. > > But on one board is working and on another one is not working. > > I'm providing a 300ms long reset signal as requested on the V4 user > guide but the DCM doesn't get locked. > > The input is a 100MHz clock and the sys_clock_dcm signal is valid, but > I don't get the divided, multiplied and FX clocks, and the lock signal > is down. > > The same bitstream is working on > > SYSTEM_DCM: DCM > generic map ( > CLKFX_DIVIDE => 8, > CLKFX_MULTIPLY => 2 > ) > port map ( > CLKIN => adc1_clk_in, > CLKFB => sys_clock_dcmfb, > DSSEN => '0', > PSINCDEC => '0', > PSEN => '0', > PSCLK => '0', > RST => my_dcm_reset, > CLK0 => sys_clock_dcm, > CLKDV => sys_clock_x05_i, > CLK2X => sys_clock_x2_i, > CLKFX => sys_clock_fx_i, > LOCKED => sys_lock > ); > > sys_clock_dcm_bufg: BUFG port map( I => sys_clock_dcm, O => > sys_clock_dcmfb); With a sample size of just two boards, it's possible that your clock source is not within the required jitter specs to achieve lock. What is the source? Possibly an oscillator with a PLL to produce the required frequency?Article: 133676
"Gabor" <gabor@alacron.com> wrote in message news:e1dcc819-76e0-4f8b-8e0a-7ee345bacdbb@8g2000hse.googlegroups.com... > On Jul 8, 9:46 am, Nemesis <gnemesis2...@gmail.com> wrote: >> I have two different boards (ICS-8550) the differ only for the >> ruggedization level, the boards are almost the same and so should be >> the FPGAs, maybe only the stepping level is different. >> >> But on one board is working and on another one is not working. >> > > With a sample size of just two boards, it's possible that your clock > source is not within the required jitter specs to achieve lock. What > is the source? Possibly an oscillator with a PLL to produce the > required frequency? Or maybe cascaded DCMs?Article: 133677
On Jul 8, 11:12 am, "shivashankara" <shankaran.si...@gmail.com> wrote: > Hi All, > I am migrating from Spartan 3e to Cyclone III. We bought only cyclone III > starter board. We don't have any USB blaster download cable. I devloped > the my current design. Now i want to download into FPGA using USB cable. > What are the steps to follow? > > regards, > S Shankaran "We don't have any USB blaster download cable." - "I want to download into FPGA using USB cable." Unless I'm missing something here, step one would be to "Get a USB download cable."Article: 133678
On Jul 8, 9:41 pm, kumara...@gmail.com wrote: > On Jul 5, 2:36 am, meralonu...@gmail.com wrote: > > > Xilinx ISE 9.2 and 10.1 (Webpack) > > > signal cntr: integer range 0 to 3; > > ... > > if(clk'event and clk='1') then cntr<=cntr+1; end if; > > inferres 2 FFs as I see from the RL schematics. > > But when I try to simulate, the simulator does not recognize any upper > > limit. That is, it counts limitlessly. > > I am a beginner. What is the problem? > > Thanks. > > Hi, > > ISE Simulator has simulation run time value range check turned off by > default, hence you do not see your out of range value being detected > and reported as error. > > If you are using ISE 9.2, please do following to turn the value range > check on: > > 1) Right click on "Simulate Behavioral Model" and select > "Properties.." > 2) On the Properties dialog set the "Propert display level" to > Advanced > 3) You will see a Property named "Value Range Check". Select the box > against this property to turn the value range check on. > > If you are a command line user, type fuse -help and you will see that > there is a switch called -rangecheck that turns on the value range > check. Use this switch and you would see value range check being > performed during simulation. > > Generaly speaking, ISE 10.1 verison of ISE simulator is hugely > improved in quality and speed over ISE 9.2 version of the simulator; > However, I have to admit that 10.1 ISim does have run time value > rangecheck broken. We are going to fix the broken value range check in > 10.1 Service pack 3. > > Thank you for using ISim (SE Simulator) and providing this feedback! > Kumar (ISE Simulator team) One of the differences I have noticed between the ISE simulator and the Active-HDL simulator is that ISE seems to compile to machine runnable code and Active-HDL does not. Active-HDL compiles much faster, typically around a second for my current project, while ISE can take many 10's of seconds. I would assume this is done because it makes for faster simulation? So I guess there is a break point where running for a shorter time is faster on the Active-HDL simulator and for a longer time is faster on the ISE simulator. Do you have any idea of where that break point is? Is there an option for not compiling to executable code when running short simulations? RickArticle: 133679
"vlsi_learner" <bajajk@gmail.com> wrote in message news:e923ab5c-6a1d-4431-9630-8375a0da42b5@d77g2000hsb.googlegroups.com... > Hi, > > I am using altera FPGA. > > How can I put the output of my logic into the FPGA internal > memories(assuming I have unused memories available)? Probably best to use a dual port RAM - something like a lpm_ram_dp will do nicely. Using the megawizard decide on the width and depth required. Set up a scanner (mux/counter combo) with each of your internal nodes that you want to store located on the input of the mux. Wizz round (scan) the mux inputs with your counter, at the same time using the counter output as the address to your RAM. Output of mux is data input to RAM. Also generate an appropriate clock/WR for the RAM. Bring the other side of the DPR address and DATA to the FPGA I/O and weld up the WR line low (you only want to READ). Now, assuming you internal scanned nodes have defined bit and address positions, and you have an appropriate scan sample rate going, you can access any node via the I/O address data lines. Now why couldn't you think of that? IckyArticle: 133680
Ive seen posts on this error in VHDL a few times around here, but I am
still unsure how to get rid of this error so my nets don't get
removed. Here is the code that is causing the error:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity BLINK is
PORT( SA: IN STD_LOGIC_VECTOR (19 downto 0); --Offending
input vector
pin2: OUT STD_LOGIC := '0';
clk: IN STD_LOGIC);
end BLINK;
architecture FLASH of BLINK is
CONSTANT count: INTEGER:=8330000;
SIGNAL t: INTEGER:= 0;
SIGNAL sig: STD_LOGIC:='0';
SIGNAL state: STD_LOGIC;
CONSTANT address: STD_LOGIC_VECTOR (19 downto 0) := X"002E8";
SIGNAL BASEADDRESS: STD_LOGIC_VECTOR (19 downto 0);
SIGNAL ADD: STD_LOGIC_VECTOR (2 downto 0);
begin
PROCESS (clk, SA) --SA is placed in
sensitivity list
begin
BASEADDRESS<=SA AND "11111111111111111000"; --SA is
used to derive a value for a signal
ADD<=SA (2 downto
0); --SA
is used to derive a value for a signal
IF(BASEADDRESS=address) THEN
.
.
.
I get the error that SA_0 through SA_19 has no load. As you can see, I
use the SA vector. I have even tried placing it in the sensitivity
list, but I still get the 'has no load' error and the net continues to
get removed after synthesis. How do I go about either giving this
vector a dummy load or ignoring the warnings and keeping the net in my
design?
Thanks in advance.
Article: 133681On Jul 9, 9:44 am, Matt <metal...@gmail.com> wrote: > Ive seen posts on this error in VHDL a few times around here, but I am > still unsure how to get rid of this error so my nets don't get > removed. Here is the code that is causing the error: > > library ieee; > use ieee.std_logic_1164.all; > use ieee.std_logic_arith.all; > use ieee.std_logic_unsigned.all; > > entity BLINK is > > PORT( SA: IN STD_LOGIC_VECTOR (19 downto 0); --Offending > input vector > pin2: OUT STD_LOGIC := '0'; > clk: IN STD_LOGIC); > > end BLINK; > > architecture FLASH of BLINK is > > CONSTANT count: INTEGER:=8330000; > SIGNAL t: INTEGER:= 0; > SIGNAL sig: STD_LOGIC:='0'; > SIGNAL state: STD_LOGIC; > CONSTANT address: STD_LOGIC_VECTOR (19 downto 0) := X"002E8"; > SIGNAL BASEADDRESS: STD_LOGIC_VECTOR (19 downto 0); > SIGNAL ADD: STD_LOGIC_VECTOR (2 downto 0); > > begin > > PROCESS (clk, SA) --SA is placed in > sensitivity list > begin > > BASEADDRESS<=SA AND "11111111111111111000"; --SA is > used to derive a value for a signal > ADD<=SA (2 downto > 0); --SA > is used to derive a value for a signal > > IF(BASEADDRESS=address) THEN > > . > . > . > > I get the error that SA_0 through SA_19 has no load. As you can see, I > use the SA vector. I have even tried placing it in the sensitivity > list, but I still get the 'has no load' error and the net continues to > get removed after synthesis. How do I go about either giving this > vector a dummy load or ignoring the warnings and keeping the net in my > design? > > Thanks in advance. The signals BASEADDRESS and ADD are not used, so any assignment to them is being optimized away. Then you are left with input signals that do nothing, and that's where the warning message is coming from. Connect those signals to something, and the logic won't be optimized away. As is is, you have one output, and it is forced to '0', so I would be surprized if there was _any_ logic left.Article: 133682
On Jul 9, 9:14=A0am, rickman <gnu...@gmail.com> wrote: > On Jul 8, 9:41 pm, kumara...@gmail.com wrote: > > > > > > > On Jul 5, 2:36 am, meralonu...@gmail.com wrote: > > > > Xilinx ISE 9.2 and 10.1 =A0(Webpack) > > > > signal cntr: integer range 0 to 3; > > > ... > > > if(clk'event and clk=3D'1') then cntr<=3Dcntr+1; end if; > > > inferres 2 FFs as I see from the RL schematics. > > > But when I try to simulate, the simulator does not recognize any uppe= r > > > limit. That is, it counts limitlessly. > > > I am a beginner. What is the problem? > > > Thanks. > > > Hi, > > > ISE Simulator has simulation run time value range check turned off by > > default, hence you do not see your out of range value being detected > > and reported as error. > > > If you are using ISE 9.2, please do following to turn the value range > > check on: > > > 1) Right click on "Simulate Behavioral Model" and select > > "Properties.." > > 2) On the Properties dialog set the "Propert display level" to > > Advanced > > 3) You will see a Property named "Value Range Check". Select the box > > against this property to turn the value range check on. > > > If you are a command line user, type fuse -help and you will see that > > there is a switch called -rangecheck that turns on the value range > > check. Use this switch and you would see value range check being > > performed during simulation. > > > Generaly speaking, ISE 10.1 verison of ISE simulator is hugely > > improved in quality and speed over ISE 9.2 version of the simulator; > > However, I have to admit that 10.1 ISim does have run time value > > rangecheck broken. We are going to fix the broken value range check in > > 10.1 Service pack 3. > > > Thank you for using ISim (SE Simulator) and providing this feedback! > > Kumar (ISE Simulator team) > > One of the differences I have noticed between the ISE simulator and > the Active-HDL simulator is that ISE seems to compile to machine > runnable code and Active-HDL does not. =A0Active-HDL compiles much > faster, typically around a second for my current project, while ISE > can take many 10's of seconds. =A0I would assume this is done because it > makes for faster simulation? =A0So I guess there is a break point where > running for a shorter time is faster on the Active-HDL simulator and > for a longer time is faster on the ISE simulator. =A0Do you have any > idea of where that break point is? =A0Is there an option for not > compiling to executable code when running short simulations? > > Rick- Hide quoted text - > > - Show quoted text - Hi Rick, Thank you for sharing your observation on compilation time of ISim with us! It is true that ISim compiler creates native machine runnable code as opposed to creating a pseudo byte code or interpretable intermediate representation. The native machine runnable code does help simulaiton go faster on a bit of extra cost to compilation. On the other hand, I can see that creating pseudo byte code instead of runnable machine code can make compilation go faster at cost of making simulation launch a bit slower -- cost to convert the pseudo byte code to machine code will need to be shifted to simulaiton launch time. ISim does not have option to create pseudo byte code as such. But, we are continually looking at speeding up compilation and simulation. For example, ISE 10.1 ISim compiler is 5X faster that ISE 9.2 ISim compiler as measured by a suite of around 75 behavioral/timing tests. We used to generate complex C++ code out of HDL in ISE 9.2 version which made our compilation slow. In ISE 10.1 we started generating simple assmebly like C from HDL and that has reduced compilation time by 5X. Thank you again! KumarArticle: 133683
On this wiki page on Viterbi Decoder : http://en.wikipedia.org/wiki/Viterbi_decoder In the TBU section, it reads "Note that the implementation shown on the image requires double frequency. There are some tricks that eliminate this requirement." Just wondering what the tricks are?Article: 133684
On Jul 9, 1:03 pm, LittleAlex <alex.lo...@email.com> wrote: > On Jul 9, 9:44 am, Matt <metal...@gmail.com> wrote: > > > > > Ive seen posts on this error in VHDL a few times around here, but I am > > still unsure how to get rid of this error so my nets don't get > > removed. Here is the code that is causing the error: > > > library ieee; > > use ieee.std_logic_1164.all; > > use ieee.std_logic_arith.all; > > use ieee.std_logic_unsigned.all; > > > entity BLINK is > > > PORT( SA: IN STD_LOGIC_VECTOR (19 downto 0); --Offending > > input vector > > pin2: OUT STD_LOGIC := '0'; > > clk: IN STD_LOGIC); > > > end BLINK; > > > architecture FLASH of BLINK is > > > CONSTANT count: INTEGER:=8330000; > > SIGNAL t: INTEGER:= 0; > > SIGNAL sig: STD_LOGIC:='0'; > > SIGNAL state: STD_LOGIC; > > CONSTANT address: STD_LOGIC_VECTOR (19 downto 0) := X"002E8"; > > SIGNAL BASEADDRESS: STD_LOGIC_VECTOR (19 downto 0); > > SIGNAL ADD: STD_LOGIC_VECTOR (2 downto 0); > > > begin > > > PROCESS (clk, SA) --SA is placed in > > sensitivity list > > begin > > > BASEADDRESS<=SA AND "11111111111111111000"; --SA is > > used to derive a value for a signal > > ADD<=SA (2 downto > > 0); --SA > > is used to derive a value for a signal > > > IF(BASEADDRESS=address) THEN > > > . > > . > > . > > > I get the error that SA_0 through SA_19 has no load. As you can see, I > > use the SA vector. I have even tried placing it in the sensitivity > > list, but I still get the 'has no load' error and the net continues to > > get removed after synthesis. How do I go about either giving this > > vector a dummy load or ignoring the warnings and keeping the net in my > > design? > > > Thanks in advance. > > The signals BASEADDRESS and ADD are not used, so any assignment to > them is being optimized away. Then you are left with input signals > that do nothing, and that's where the warning message is coming from. > Connect those signals to something, and the logic won't be optimized > away. > > As is is, you have one output, and it is forced to '0', so I would be > surprized if there was _any_ logic left. Isn't BASEADDRESS being used in the IF statement? IF(BASEADDRESS=address) THEN also, ADD is used in a similar switch case later in the code, I removed it just to keep it short. Thanks, MattArticle: 133685
> having difficulty determining how to detect the size of the > instruction register for each device. Can someone point me to some > code? AFAIK this problem can't be solved. Thats why every JTAG programm I know need this information frm the user or BSDL file. Regards FalkArticle: 133686
> I have the code which successfully goes out and determines the number > of devices in the scan chain, but am having difficulty determining > how to detect the size of the instruction register for each device. > Can someone point me to some code? Once you know the number of devices in the chain, you could retrieve their IDCODEs and get the instruction register length for each device from a look-up table or database. The UrJTAG software (http://urjtag.org/) applies this mechanism to identify the elements of the scan chain automatically. ArnimArticle: 133687
"Arnim" <clv.5.minral@spamgourmet.com> wrote in message news:g5394o$2cj$1@svr7.m-online.net... > > I have the code which successfully goes out and determines the number > > of devices in the scan chain, but am having difficulty determining > > how to detect the size of the instruction register for each device. > > Can someone point me to some code? > > Once you know the number of devices in the chain, you could retrieve > their IDCODEs and get the instruction register length for each device > from a look-up table or database. > The UrJTAG software (http://urjtag.org/) applies this mechanism to > identify the elements of the scan chain automatically. > > Arnim Hi, Knowing the number of devices in a JTAG chain is simple: after a reset (TRSTN = 0 or 5x TMS = 1) all devices with the IDCODE instruction must reset to this command, the others must reset to the BYPASS instruction. The IDCODE is always 32 bits with bit[0] = 1 and BYPASS register always captures a 0. Finding the total length of the IR registers is do-able, but rather difficult for individual registers: the IR register should capture 01 (or is it 10) als it's 2 lsbs. Using the above technique to get the IDCODEs and then going on woith the BSDL files is the best approach. Regards, Alvin.Article: 133688
> ERROR:iMPACT:583 - '1': The idcode read from the device does not match > the > =A0 =A0idcode in the bsdl File. > INFO:iMPACT:1578 - '1': =A0Device IDCODE : > 00000011100001000100000100100110 > > INFO:iMPACT:1579 - '1': Expected IDCODE: > 00000001110000100010000010010011 > Elapsed time =3D =A0 =A0 =A00 sec. -------------------------------------------------- Looks like the Device idcode is shifted by one bit. Perhaps noise on the jtag lines that maybe susceptible to speed setting of the download GUI vs batch mode. Are you using the flying leads. Sometimes they do not work very well. GLArticle: 133689
LittleAlex wrote: > On Jul 8, 11:12 am, "shivashankara" <shankaran.si...@gmail.com> wrote: >> Hi All, >> I am migrating from Spartan 3e to Cyclone III. We bought only cyclone III >> starter board. We don't have any USB blaster download cable. I devloped >> the my current design. Now i want to download into FPGA using USB cable. >> What are the steps to follow? >> >> regards, >> S Shankaran > > "We don't have any USB blaster download cable." - "I want to download > into FPGA using USB cable." > > Unless I'm missing something here, step one would be to "Get a USB > download cable." Well, actually if (and only if) he does have a "Cyclone III Starter FPGA Kit" (and just did not name it that way) the onboard usb-client port together with the onboard clpd have USB Blaster functionality. Nevertheless he can buy a USB-Blaster or even build such a JTAG cable himself (at least for the serial (line printer) port there are numerous examples on the internet. Nevertheless I'd suggest using the solution one gets for free. Regards, LorenzArticle: 133690
You could post your whole code, that would help. Usually you only have clk in the sensitivity list for synchronous operation unless you are doing an asynchonous reset or something more exotic. I think LittleAlex is right that something is being optimised away. You could try pin2<=sa(19) and sa(18); to see if those warnings go away on those two inputs. Brad Smallridge AiVisionArticle: 133691
Looks like the data line is open drain with a 1.5K pullup resistor. To send a high, one has to tristate the output. To send a '0', one drives the signal to '0' SCLK probably is supposed to run at 100KHz Looks like there is ack about every 8 bits. Might want to look at an I2C specification to see how a similar/same bus operates.Article: 133692
On Jul 9, 10:49 am, Matt <metal...@gmail.com> wrote: > On Jul 9, 1:03 pm, LittleAlex <alex.lo...@email.com> wrote: > > > > > On Jul 9, 9:44 am, Matt <metal...@gmail.com> wrote: > > > > Ive seen posts on this error in VHDL a few times around here, but I am > > > still unsure how to get rid of this error so my nets don't get > > > removed. Here is the code that is causing the error: > > > > library ieee; > > > use ieee.std_logic_1164.all; > > > use ieee.std_logic_arith.all; > > > use ieee.std_logic_unsigned.all; > > > > entity BLINK is > > > > PORT( SA: IN STD_LOGIC_VECTOR (19 downto 0); --Offending > > > input vector > > > pin2: OUT STD_LOGIC := '0'; > > > clk: IN STD_LOGIC); > > > > end BLINK; > > > > architecture FLASH of BLINK is > > > > CONSTANT count: INTEGER:=8330000; > > > SIGNAL t: INTEGER:= 0; > > > SIGNAL sig: STD_LOGIC:='0'; > > > SIGNAL state: STD_LOGIC; > > > CONSTANT address: STD_LOGIC_VECTOR (19 downto 0) := X"002E8"; > > > SIGNAL BASEADDRESS: STD_LOGIC_VECTOR (19 downto 0); > > > SIGNAL ADD: STD_LOGIC_VECTOR (2 downto 0); > > > > begin > > > > PROCESS (clk, SA) --SA is placed in > > > sensitivity list > > > begin > > > > BASEADDRESS<=SA AND "11111111111111111000"; --SA is > > > used to derive a value for a signal > > > ADD<=SA (2 downto > > > 0); --SA > > > is used to derive a value for a signal > > > > IF(BASEADDRESS=address) THEN > > > > . > > > . > > > . > > > > I get the error that SA_0 through SA_19 has no load. As you can see, I > > > use the SA vector. I have even tried placing it in the sensitivity > > > list, but I still get the 'has no load' error and the net continues to > > > get removed after synthesis. How do I go about either giving this > > > vector a dummy load or ignoring the warnings and keeping the net in my > > > design? > > > > Thanks in advance. > > > The signals BASEADDRESS and ADD are not used, so any assignment to > > them is being optimized away. Then you are left with input signals > > that do nothing, and that's where the warning message is coming from. > > Connect those signals to something, and the logic won't be optimized > > away. > > > As is is, you have one output, and it is forced to '0', so I would be > > surprized if there was _any_ logic left. > > Isn't BASEADDRESS being used in the IF statement? > > IF(BASEADDRESS=address) THEN > > also, ADD is used in a similar switch case later in the code, I > removed it just to keep it short. > > Thanks, > Matt BASEADDRESS is used in the IF statement, but it doesn't actually "do" anything. If it's equal to something, ADD gets set, but ADD isn't used for anything, so that assignment is a "don't care", so the comparison doesn't matter, so ...Article: 133693
Hi everyone, I'm supposed to implement a serializer where the parallel data and clock arrive from outside the chip and I have an 8x internal clock which is frequency locked to the incoming clock but the phase relationship between internal fast clock and external slow clock is unknown (but they are frequency locked ie the phase difference between the edges is not changing). Another constraint is that I have to do this with minimum latency so I can't use a synchronous fifo to gearshift. And unfortunately I don't have a PLL or DLL to create a zero-delay clock either. So what I am doing is an oversampling phase lock. I have a counter running at the fast clock and I sample the incoming clock with the fast clock 3 times and try to find the positive edge using the last two samples and I record the count when I see the edge and go back in the count value to sample the data as early as possible. If I account for the uncertainty of sampling this works OK. The issue is that if I am sampling at close to transition of incoming clock, the phase I will detect will change one tap occasionally (even maybe frequently; I'm assuming I'm not hitting a meta-stable case here). To prevent this I'm considering adding a small delay line myself (I have cells which have relatively large delay independent of PVT) and if I detect the phase changing, adding/subtracting one delay element to get stable sampling. Does this sound like a workable solution just for finding the phase of the clock? For data I'll implement the same delay line and change the sampling location similarly. Any suggestions are welcome.Article: 133694
Thanks! Newman wrote: > Looks like the data line is open drain with a 1.5K pullup resistor. > To send a high, one has to tristate the output. To send a '0', one > drives the signal to '0' > SCLK probably is supposed to run at 100KHz > Looks like there is ack about every 8 bits. > Might want to look at an I2C specification to see how a similar/same > bus operates. >Article: 133695
You don't need to find out the IR length. What your trying to do is called "blind interrogation" in the JTAG spec. As you clock into Test logic Reset all devices enter manufacturers ID mode if it is implemented and bypass if it isn't. A device will shift out a 1 on the first edge of the clock if it is shifting out its ID and will shift out a 0 if it is in bypass. It is then straightforward to work out what devices are in your chain. High end JTAG test software that does interconnect testing (which is what JTAG was originally for) does not trust the information given in the bsdl files untill they check the manufacturers ID and then the IR & DR lengths on pretty much every test they carry out. ColinArticle: 133696
Icky Thwacket wrote: > Probably best to use a dual port RAM - something like a lpm_ram_dp will do > nicely. Using the megawizard decide on the width and depth required. Set up > a scanner (mux/counter combo) with each of your internal nodes that you want > to store located on the input of the mux. Wizz round (scan) the mux inputs > with your counter, at the same time using the counter output as the address > to your RAM. Output of mux is data input to RAM. Also generate an > appropriate clock/WR for the RAM. Bring the other side of the DPR address > and DATA to the FPGA I/O and weld up the WR line low (you only want to > READ). Now, assuming you internal scanned nodes have defined bit and address > positions, and you have an appropriate scan sample rate going, you can > access any node via the I/O address data lines. This sounds really complicated. He asked for putting the output into the memory, only. Looks like he don't want to read it back :-) > Now why couldn't you think of that? Looks like such things are common to people with gmail accounts. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 133697
On Jul 9, 5:55 am, kclo4 <alexis.ga...@gmail.com> wrote: > On Jul 8, 10:27 pm, natarajan.jaya...@gmail.com wrote: > > > Hey, > > > I need to send some data to the Altera Stratix II FPGA board from the > > matlab workspace and then do some FFT, FIR process on that and then > > return the data from the FPGA back into the matlab workspace. How do > > I do that? Kindly let me know if there is some tutorial which is > > Altera specific on this which can tell me how to do it step by step. > > > Thanks and Regards, > > Jayaram > > What is your board?? What are your bandwidth need? Personally I used a > RS232 it is easy to implement on both FPGA and matlab but it's slow so > I use it only for debugging. I am using EP2S180F1020C4 Stratix II. I do not need very high speed as such. Could you please highlight me on something about your implementation. A tutorial would be really helpful. Thanks JayaramArticle: 133698
"Frank Buss" <fb@frank-buss.de> wrote in message news:lwpnm8xptojr$.5dpw9umuf1k2$.dlg@40tude.net... > > He asked for putting the output into the > memory, only. Looks like he don't want to read it back :-) > In which case he needs one of these:- http://academics.vmi.edu/ee_js/Research/IC_Datasheets/digital_cmos/Write%20Only%20Memory.pdfArticle: 133699
On Jul 5, 4:43=A0pm, "Kappa" <78kappa78(at)virgilio(dot)it> wrote: > I have built a QPSK modulator, but I have some doubts about the generatio= n > of SymbolRate variable. > > The SymbolRate range should from 1 to 45 Msymb/s. I intend to use an > external AD9850 DDS, which generates the clock from 1 MHz to 45 MHz for > clockout the Symbol. > > The Symbols (I and Q) is interpolated by x2 or x4. > > How can multiply internally this clock (1 to 45 MHz) by x2 or x4 ? I > remember that the clock is variable. > > It's possible ? > > Thansk. > > Kappa hello i am doing Mtech in VLSI. I am in 3rd sem . i have to implement QPSk in VHDL if your have qpsk modulator in vhdl then pls foreward me
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