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jjlindula@hotmail.com wrote:
> Hello, I use Altera's Quartus II software for my FPGA development and
> in the software package they have the following Advisors: Timing,
> Power, Resource Optimization, Increment Compilation. I usually open
> the Timing Advisor and make the suggested changes that are easy to
> make. Usually these are the configuration settings and are easy to
> change. The other suggestions in the Timing Advisor are a little more
> involved and I don't do.
Yes, the timing adviser is a good double check.
If I have a top level synchronization plan
I should be able to sort out the expected
warnings about synchronizers from design
rule violations.
-- Mike Treseler
Article: 120401Symon, Gaslamp? Nope, although right around the block, on Front Street is our vacation residence. Right now I am at the Hyatt, on the bay, up the street from the convention center. Great show, all those booths with Xilinx products. Wow. Seems like any booth I go to, they are selling, supporting, using, or in some other way, merchandising Xilinx. A little disappointed at how there is so little competition. How are we going to keep our edge? John Daane this AM announced that they will have a 45 nm product in 2008... Perhaps they will skip 65nm altogether? "Fast follower"? I am shocked. Their 65nm S3 is announced to be released in August, 2007. Perhaps everyone should wait until 2008, and get their 45nm? Of course, TSMC is making a huge splash at DAC with their 65/45nm tools, process, and IP. Too bad it is the "cell phone low power" processes they are pushing. In talking to ASIC designers (lots of those at this little show), they are frantic about the poor models, lack of process control, huge variations, and inability to design for low power. With the "low power process." Too bad if you want a high performance process at 65 (or 45nm). At $2M a mask set, "guess and check" gets pretty expensive! I also learned the ASIC emulation business is estimated to be $30M to $40M a year (FPGA Journal story today), so compare that with last year's sales for Xilinx (1.8 billion $), and you see just how IMPORTANT those ASIC simulation sockets are. Don't get me wrong, we love that business, because it is the largest parts (xc5vlx330), and we have no competition for more than one year now ... so we "own" the entire market (no competition). But owning the "high ground" is not much money when you look at it compared to the overall sales numbers. But, I digress. We have seen where the various parasitic inductances, and the capacitance combine to create spots where there is no effective bypassing at all. Hence the need for more than one value to "break it up." More later, I have asked one of my SI gurus to put something together to illustrate the (potential) problem. AustinArticle: 120402
On Wed, 06 Jun 2007 03:07:41 -0700, sanju <sanju4buddy@gmail.com> wrote: >is anybody here who can guide me about asynchronous CAD tools. is any >such CAD tool available. which asynchronous design methodology is used >nowadays.plz help me. Have you looked at Handshake Solutions? www.handshakesolutions.com I'm sure there are other such tools around too. However, I'm not aware of *any* asynchronous design tools that are truly mainstream. For FPGAs, the structure of the devices and the behaviour of their place-and-route tools effectively makes asynchronous design intractable for ordinary mortals. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 120403
sanju, Somebody is using asynchronous design? Wow. I thought it died (yet again) awhile ago now. I think when the famous asynchronous ARM chip was built synchronously and was better in every possible way (size: smaller, power: less, etc.), that it effectively killed asynchronous design (again). I have yet to see a single case where asynchronous design has any advantages. In the small (phase detectors, D flip flop, clock switches, FIFO, and so on), asynchronous design must be used (somewhere). But it is usually done by one expert (and only that one expert is allowed to do any asynchronous design). Much more popular is "Globally asynchronous, locally synchronous" or GALS approach to design, where groups of synchronous logics communicate with others using asynchronous handshake protocols. No need for any new tools. AustinArticle: 120404
glen herrmannsfeldt wrote: > I have been told that another reason is that it is too hard for > engineers to learn and understand both C and verilog. This I also > don't believe, but maybe that is just me. Huh? It is a pretty bad engineer who can only think in one language. Always try to use the right tool for the job! Terje -- - <Terje.Mathisen@hda.hydro.com> "almost all programming can be viewed as an exercise in caching"Article: 120405
On Jun 6, 6:07 am, sanju <sanju4bu...@gmail.com> wrote: > is anybody here who can guide me about asynchronous CAD tools. is any > such CAD tool available. which asynchronous design methodology is used > nowadays.plz help me. There is a chapter called Level-Mode Sequential Circuits in Introduction to Switching Theory & Logical Design Frederick J. Hill Gerald R. Peterson Third Edition Copyright 1968, 1974, 1981 John Wiley & Sons, Inc. Perhaps a Google Search will pick up related, newer references. -Newman, a synchronous guy ... not asynchronousArticle: 120406
I have two FPGA development boards, using different power source. when I connected their IO pins, should I connect the GND of board too? I hesitate to do that because I am not sure if these two GNDs are sharing a common GND. If they do not have a common GND, will it generate a current between GNDs when I connect them and damage the boards? Any other things I should take care of when I connect two FPGA board together? ThanksArticle: 120407
On Jun 6, 3:09 pm, jasonL <junsong.l...@gmail.com> wrote: > I have two FPGA development boards, using different power source. when > I connected their IO pins, should I connect the GND of board too? > > I hesitate to do that because I am not sure if these two GNDs are > sharing a common GND. If they do not have a common GND, will it > generate a current between GNDs when I connect them and damage the > boards? > > Any other things I should take care of when I connect two FPGA board > together? > > Thanks If the two grounds are different, and you don't connect the grounds together, you'll damage the FPGAs. Even if they are at the same potential, and you don't connect the grounds together, interface signals between them will likely not work. Connect the grounds. AndyArticle: 120408
jasonL, if you do not connect the two grounds, then you will almost certqainly damage the two devices, or, nothing will happen (as they have no common reference). If the two grounds can not be connected without causing a current to flow, there is something seriously wrong with you building wiring! It could kill you, in fact. Connect the two grounds together with a DVM in between, or current scale. There should be 0 AC current,and 0 DC current flowing between the boards (before any signals are switching). If this is not the case, consult an electrician (as electronics engineer is not needed, but someone who understands how wall sockets are wired, is required). AustinArticle: 120409
On 28 mai, 00:35, Ken Ryan <newsr...@leesburg-geeks.org> wrote: > Thanks, you encouraged me to try that tack again. :-) > > I commented out the bogus sleep() definition, and I had to drop > a "#define LWIP_TIMEVAL_PRIVATE 0" to keep lwip away from struct > timeval. > > Next, to figure out why the Xilinx gdb quit giving me symbols... > (yes I have -g -O0 in both the app and libraries...) > > ken Thank you guys for sharing your experiences. I had the same problem and commented out this line in sleep.h. //void sleep(unsigned int seconds); Is it the line you were talking about? I'm not sure where to do the fix however... Doing any modification to the EDK source tree is not portable accross computers. Doing the modification in the ppc405_0 folder will be lost during the next library rebuild. Is there a better way? Another question while I'm at it, did you fix the problem about debug symbols? It indeed seems broken in EDK v9.1, even after 2 service packs. Thanks. PatrickArticle: 120410
On Jun 6, 7:35 am, austin <aus...@xilinx.com> wrote: > "Chopped liver?" I wonder where that came from? This is proof that East Coast Jewish facetiousness just doesn't come across correctly on Usenet. Proper pronunciation: Borscht belt comedian. "What am I, chopped liver?" is a gentle nudge meaning, "please don't ignore me!" (or less gently, depending on tone-of-voice, "Thanks for ignoring me ...") In this context, an issue was raised in public but answered off-line. Hence, the nudge. -aArticle: 120411
"Andy Peters" <google@latke.net> wrote in message news:1181163696.659767.295660@n15g2000prd.googlegroups.com... > On Jun 6, 7:35 am, austin <aus...@xilinx.com> wrote: > >> "Chopped liver?" I wonder where that came from? > > This is proof that East Coast Jewish facetiousness just doesn't come > across correctly on Usenet. Proper pronunciation: Borscht belt > comedian. > > I was as confused as Austin for a while, but it turns out Jewish folk help us gentiles by posting on Wikipedia! :-) http://en.wikipedia.org/wiki/Chopped_liver Cheers, Syms.Article: 120412
"jasonL" <junsong.liao@gmail.com> wrote in message news:1181160552.039333.85840@a26g2000pre.googlegroups.com... >I have two FPGA development boards, using different power source. when > I connected their IO pins, should I connect the GND of board too? > > I hesitate to do that because I am not sure if these two GNDs are > sharing a common GND. If they do not have a common GND, will it > generate a current between GNDs when I connect them and damage the > boards? > > Any other things I should take care of when I connect two FPGA board > together? > > Thanks Your two boards are powered by power supplies. Those supplies should be isolated. If the two grounds were connected together, the only imperfection in the ground should be due to imperfections in the isolation creating very little (if any) current flow. If they're isolated, the voltage between the two might be measered by a DVM to be a very bad number! But if you attached a 10k resistor between the two grounds, you would find the voltage difference to be negligible. For single ended electrical signals there must be a common ground reference for the transmitter and receiver. When a signal transitions, current flows in both the wire that's transitioning and the ground that provides the current return path. If the loop for the signal current and return current is large, ugly things will happen (crosstalk, electromagnetic interference, general signal integrity issues). For differential signals, the signal current has no (intended) return current through the ground plane. The differential signal should balance the currents so the switching point isn't affected by grounding issues. The differential receiver *does* still need to have the signal in its acceptable common mode range. To this end, it's better to have the common ground between the two boards powered by isolated power supplies. There are cases when the grounds cannot be the same. For these circumstances, simple electrical connections won't do. Isolation through transformers or opto-isolators are required to get the communication going. If you're working with development boards, the supplies should be isolated. Check the voltage with a 10k resistor between them if you're worried. If you see a little AC voltage, consider what the current flow is and whether you're comfortable with those (sub)milliamps running between boards. It's not rocket science, but there's nothing more unnerving than seeing sparks fly and losing a $1k investment. You're good to be cautious but the situation is probably fine. - John_HArticle: 120413
Symon wrote: > "austin" <austin@xilinx.com> wrote in message > news:f46gmp$ra02@cnn.xilinx.com... > >> He used all one value for Vcco bypass, 0402 1.0uF, and I am working on >>showing him that there can be anti-resonant peaks (right around 200 MHz), >>where the use of all one value is a bad choice. >> > > Hi Austin, > Anti-resonant peaks? Right around 200MHz? With a 1uF cap? Wow, I'm sure > looking forward to you posting what your advice is. You sure you've not been > spending too much time in the Gaslamp Quarter? ;-) > Cheers, Syms. This is an older document, but has some very good Graphs of Decoupling networks : Atmel's "EMC Improvement Guidelines" : http://www.atmel.com/dyn/resources/prod_documents/doc4279.pdf I've also seen more recent papers, pushing the "wider aspect ratio" caps, and the pass-thru decouplers, that give T networks, and some of those include PCB Plane impedance plots. Q: what is the package capacitance / impedance of the present FPGA packages alone (no decoupling), and of the FPGA mounted on a typical planed PCB (no caps) ? -jgArticle: 120414
On Jun 5, 9:47 pm, Ace <yasi...@gmail.com> wrote: > Hello, > > I recently bought a board that has a firewire port that uses PCI32 as > a communication to the TI Link layer chip. I was told that I could > easily communicate with the board by FPGA using Xilinx IPcore. I > followed the steps on "Getting Started User Guide" i.e. inserting the > device id, vendor id values and etc, getting the .ngc file and then > get the .bit file and used iMPACT. However, after several attempts, my > linux machine still could not detect the board. > > Does anyone has any suggestion on this? > > Cheers! It has been many years since I used the Xilinx PCI core, but... There was a short errata sheet that required VERY careful reading to make the core work. Two of the things I remember were the reset pin being in the wrong place and one clock being run through a BUF rather than a BUFG. And you do know that the FPGA -must- be initialized before the ROM BIOS does the power-on bus scan, right? HTHArticle: 120415
On Jun 6, 7:24 am, EdA <ed.art...@gmail.com> wrote: > Try this link:http://www.sutherland-hdl.com/pli_book_examples.html > > "David Roberts, of Cadence Design Systems, has provided a great > example using sockets to communicate between a PLI application and an > independently running C program. David has provided this example with > no restrictions on usage, under the GNU freeware license agreement." > > Allegedly it works on Linux and Windows. Yeah, and it's pretty simple. I did something like that a few years back - I'd built a soft-core processor (at that point only in verilog simulation), and wanted to write a debug monitor that could run on it. So I grafted in some registers to make a little "dummy uart" device that some pli code would monitor, and proxy the data to/from a local tcp socket. Then I connected to that socket with hyperterminal and "used" my simulated computer.Article: 120416
"Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message news:46672a96$1@clear.net.nz... > Symon wrote: >> "austin" <austin@xilinx.com> wrote in message >> news:f46gmp$ra02@cnn.xilinx.com... >> >>> He used all one value for Vcco bypass, 0402 1.0uF, and I am working on >>> showing him that there can be anti-resonant peaks (right around 200 >>> MHz), where the use of all one value is a bad choice. >>> >> >> Hi Austin, >> Anti-resonant peaks? Right around 200MHz? With a 1uF cap? Wow, I'm sure >> looking forward to you posting what your advice is. You sure you've not >> been spending too much time in the Gaslamp Quarter? ;-) >> Cheers, Syms. > > This is an older document, but has some very good Graphs of Decoupling > networks : > > Atmel's "EMC Improvement Guidelines" : > http://www.atmel.com/dyn/resources/prod_documents/doc4279.pdf > > I've also seen more recent papers, pushing the "wider aspect ratio" > caps, and the pass-thru decouplers, that give T networks, and > some of those include PCB Plane impedance plots. > > Q: what is the package capacitance / impedance of the present FPGA > packages alone (no decoupling), and of the FPGA mounted on a typical > planed PCB (no caps) ? > > -jg > Hi Jim, Thanks for the link, you're dead right. Also, on Murata's website, they give away some cool tools for their bypass caps which show their impedances. I'm interested how to get a resonance at 200MHz with a 1uF cap. Just to check, 200Mhz = 2*10E8, right? W=1/sqrt(1/LC) Hmmmm. As for your question, dunno, but I'm pretty sure, Xilinx have put ceramic bypass caps inside the package. It won't work otherwise. Cheers, Syms. p.s. http://www.murata.com/designlib/mcsil/index.htmlArticle: 120417
austin wrote: > Somebody is using asynchronous design? > > Wow. I thought it died (yet again) awhile ago now. I've read an article about it in 1999 [1] and it sounds interesting, but I don't know, if it is still used. If you use well known technics, like dual-rail signalling [2,3] or the Muller C gate [3], looks like you don't need to be an "expert". One advantage which isn't obvious and I remember from article [1] was, that the power consumption is lower, because you don't have to distribute a global clock signal all over the chip, but you need only locally coupled components. [1] http://www.heise.de/kiosk/archiv/ct/1999/17/176 [2] http://brej.org/papers/s2a.pdf [3] http://www.eetimes.com/editorial/2000/coverstory0005.html -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 120418
Whoops, W=sqrt(1/LC)Article: 120419
"austin" <austin@xilinx.com> wrote in message news:f46shv$ra22@cnn.xilinx.com... > > > But, I digress. > > We have seen where the various parasitic inductances, and the capacitance > combine to create spots where there is no effective bypassing at all. > Hence the need for more than one value to "break it up." > > More later, I have asked one of my SI gurus to put something together to > illustrate the (potential) problem. > OK, that'll be very interesting. I look forward to your guru's post. Many thanks, Symon.Article: 120420
It seems that bufio has the lowest clock skew in order to clock the oserdes. OSERDES in my configuration requires two clocks 1x clk and 2x clock. I would like to know how many OSERDES can I drive using one BUFIO. I would like to bring in limited number of clocks inside the part and avoid using bufg has it has 270 ps of clock skew as opposed to 50 ps of clock skew for bufio. Thanks.Article: 120421
Hi, I'd like to get some help from experienced people because I'm really running low on ideas here.. I'm a beginner in FPGA/LwIP and I can't seem to make it work using Xilinx EDK 8.2i. I've been creating a project using BSB including onewire, uart, emac and the external memory and using PPC. Once I am in the project manager, I did all of the required modifications to boot up on the bram and execute the code from the external memory, set up the -llwip4, checked the lwip 2.00a and set up the MAC address. Once i compile, it works fine, initializing a server code I took as an example and printfs display everything is fine but it is impossible to connect to the card or even ping it. Could someone give me a hint about what I m doing wrong? Thank you, Antoine.Article: 120422
Anyone, When I try to boot linux on a Xlinx ML403 board I get the following out put: loaded at: 00400000 004FA1A0 board data at: 00000000 0000007C relocated to: 0040405C 004040D8 zimage at: 00404FE5 004F7A9B avail ram: 004FB000 7C9E2378 Linux/PPC load: console=ttyS0,9600 ip=on root=/dev/xsysace2 rw Uncompressing Linux...done. Now booting the kernel Does the 'board data at' arguments look ok. Any help would be appriated!!!Article: 120423
Thanks to all of you. Your reply help me a lot. I am sure what to do now.Article: 120424
On Wed, 06 Jun 2007 07:35:13 -0700, austin <austin@xilinx.com> wrote:
>The extra pins to ground isn't go to do anything for him (use of IOs as
>ground), as he is already in an excellent package in V4, and we are
>looking at his bypassing solution. He used all one value for Vcco
>bypass, 0402 1.0uF, and I am working on showing him that there can be
>anti-resonant peaks (right around 200 MHz), where the use of all one
>value is a bad choice.
Using a different mix of caps will only produce different resonances.
I recently had some time to wait for while (1) { XST; translate; map; place & route }
and used it to play with capacitors.
6.8 Mb pdf of capacitors on a stripline: pictures and impedance plots, still bound to grow.
<http://www.hoffmann-hochfrequenz.de/downloads/experiments_with_decoupling_capacitors.pdf>
(hi, Peter, see you at the Berlin XFest!)
regards, Gerhard
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