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John Larkin wrote: > > Please post the schematic of a zero-ripple switcher. > > John Sorry, but that feature is only available on the 0 volt model. -- Service to my country? Been there, Done that, and I've got my DD214 to prove it. Member of DAV #85. Michael A. Terrell Central FloridaArticle: 115676
Michael A. Terrell wrote: > John Larkin wrote: > >>Please post the schematic of a zero-ripple switcher. >> >>John > > > > Sorry, but that feature is only available on the 0 volt model. > Indeed there are the topologies of the switchers with exactly zero or almost zero ripple, assuming the ideal symmetry of everything. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.comArticle: 115677
Adding a -L unisims_ver to the vsim command worked. PS Xilinx documentation is not the best. I never could get the library compilation wizard in the EDK to work. I had to doit manually. Then the online steps for simulating with ModelSim were not accurate.Article: 115678
John Larkin wrote:
>
... snip ...
>
> Please post the schematic of a zero-ripple switcher.
All it takes is an infinite capacity capacitor. The turn-on time
and inrush current may be high. However it avoids the need for a
UPS. Once they get the breakdown voltage up and get them into
production we can have all the electric cars we want, and dispense
with all batteries.
--
<http://www.cs.auckland.ac.nz/~pgut001/pubs/vista_cost.txt>
<http://www.securityfocus.com/columnists/423>
"A man who is right every time is not likely to do very much."
-- Francis Crick, co-discover of DNA
"There is nothing more amazing than stupidity in action."
-- Thomas Matthews
Article: 115679On Fri, 16 Feb 2007 18:25:11 GMT, Vladimir Vassilevsky <antispam_bogus@hotmail.com> wrote: > > >Michael A. Terrell wrote: >> John Larkin wrote: >> >>>Please post the schematic of a zero-ripple switcher. >>> >>>John >> >> >> >> Sorry, but that feature is only available on the 0 volt model. >> > >Indeed there are the topologies of the switchers with exactly zero or >almost zero ripple, assuming the ideal symmetry of everything. > Like a polyphase switcher with *big* inductors? But I don't want "almost zero ripple", I want the real thing. JohnArticle: 115680
John Larkin wrote: >>>>Please post the schematic of a zero-ripple switcher. >>>Sorry, but that feature is only available on the 0 volt model. >>> >>Indeed there are the topologies of the switchers with exactly zero or >>almost zero ripple, assuming the ideal symmetry of everything. >> > > > Like a polyphase switcher with *big* inductors? > But I don't want "almost zero ripple", I want the real thing. Zero ripple is a real thing. Imagine the two identical bucks operating 50/50 duty with 180 degree phase shift on the common load. Ideally, there will be no ripple at the load at all. There are numerous patents on the variations of this idea, allowing to adjust the duty, different topologies and such. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.comArticle: 115681
On Fri, 16 Feb 2007 14:18:55 -0500, CBFalconer <cbfalconer@yahoo.com> wrote: >John Larkin wrote: >> >... snip ... >> >> Please post the schematic of a zero-ripple switcher. > >All it takes is an infinite capacity capacitor. The turn-on time >and inrush current may be high. However it avoids the need for a >UPS. Once they get the breakdown voltage up and get them into >production we can have all the electric cars we want, and dispense >with all batteries. Right. You'd buy them charged, guaranted to run for 200K miles. JohnArticle: 115682
Lots of good posting on this question and I get asked it alot. The way I like to put is that picking your FPGA vendor is like liking a religion. They all offer similar things, but you should pick one and be good at it. No jumping back and forth. If your design department is really large, you can have both camps that each specialize in either Altera or Xilinx. Its the dillution of knowledge that kills you. The ability to master the tools and parts is what allows a designer to get the most out of these chips. If you have some large volume production then perhaps its worth wasting the money of entertaining other brand solutions to get the price break, but for most types of things that people seem to use FPGAs for it just isn't worth it. I've personally thrown my hat into the Xilinx ring and all new designs are Xilinx in my organization. On Feb 14, 9:59 am, "jetq88" <jetq5...@gmail.com> wrote: > Our design department basically split in the middle with half products > were designed with Altera parts and half products were designed with > Xilinx parts, when talking about choosing one main FPGA source, > everyone voiced different opinions. I'm about to have a new design to > process digital video signal which requires large external memory, > either DIMM DDR/DDR2 SDRAM or component DDR/DDR2 SDRAM. > First i go for Xilinx ISE9.1 webpack, quite large program, go to > CoreGen, can't find place to generate memory controller, goto Xilinx > and check MIG tool, nowhere to download MIG tool for ISE9.1. guess I > have to use old tool, then import to ISE9.1 and tweak it by myself. > downloaded Altera quartus6.1 webpack, go to megawizard, choose memory > controller, then DDR SDRAM, right there, only thing I need is to > customize it, looks like it's simpler so far, since I just get > started, no sure the road ahead yet, but from the beginning, look like > xilinx road is bumpy. > I know if I get reference design of either one, It should get the job > done, I want to listen to others out there, specially those who have > experience on both, what are your thoughts about both companies in > term of chip performance, development tool and supports, I'd like > choose a company with overall better preformance, stick with it and > forget the other oneArticle: 115683
John Larkin wrote: > On Fri, 16 Feb 2007 14:18:55 -0500, CBFalconer <cbfalconer@yahoo.com> > wrote: >>John Larkin wrote: >> >>... snip ... >> >>All it takes is an infinite capacity capacitor. The turn-on time >>and inrush current may be high. However it avoids the need for a >>UPS. Once they get the breakdown voltage up and get them into >>production we can have all the electric cars we want, and dispense >>with all batteries. > This is interesting: http://www.engr.wisc.edu/groups/green/ultra.html Regards, MichaelArticle: 115684
When I started to write this, I wanted to ask how to model a
bidirectional wire with transport delays but I've come up with a
solution that works for my SDRAM sim so I'll post it here. I've done a
fairly exhaustive search, and have found many instances of others posing
this question, but no other definitive answers. Mr. Bromley, in a
recent post, showed me how to model transport (not inertial) delays on
unidirectional lines. I was initially able to, using two "wires" at the
endpoints and a "reg" in the middle, simulate a tranport delay that
worked in either direction, but the problem I kept encountering was
this: the signal got "reflected" at the receiving end of the path and
retransmitted, bouncing back and forth forever like a photon in a
mirrored box.
The Verilog "tran" primitive is not useful because it never incurs a
delay across its two I/Os.
I finally found a way to prevent the reflections that has the limitation
described below. To model a bidirectional wire, just instantiate the
module below, and the 'a' and 'b' ports correspond to the values at each
end of a bidirectional wire with delay. The delay values are reals so
that they can be changed during the sim; therefore you must 'force' them
using the method described below. The delays can model PCB copper
delays only, or, for RTL sims, can incorporate input/output pad delays,
in which case the delays may be different in each direction. Here is
the model:
/*****************************************************************
* module triwire: bidirectional wire bus model with delay
*
* This module models the two ends of a bidirectional bus with
* transport (not inertial) delays in each direction. The
* bus has a width of WIDTH and the delays are as follows:
* a->b has a delay of Ta_b (in `timescale units)
* b->a has a delay of Tb_a (in `timescale units)
* The two delays will typically be the same. This model
* overcomes the problem of "echoes" at the receiving end of the
* wire by ensuring that data is only transmitted down the wire
* when the received data is Z. That means that there may be
* collisions resulting in X at the local end, but X's are not
* transmitted to the other end, which is a limitation of the
* model. Another compromise made in the interest of simulation
* speed is that the bus is not treated as individual wires, so
* a Z on any single wire may prevent data from being transmitted
* on other wires.
*
* The delays are reals so that they may vary throughout the
* course of a simulation. To change the delay, use the Verilog
* force command. Here is an example instantiation template:
*
real Ta_b=1, Tb_a=1;
always@(Ta_b) force triwire.Ta_b = Ta_b;
always@(Tb_a) force triwire.Tb_a = Tb_a;
triwire #(.WIDTH(WIDTH)) triwire (.a(a),.b(b));
* Kevin Neilson, Xilinx, 2007
*****************************************************************/
module triwire #(parameter WIDTH=8) (inout [WIDTH-1:0] a, b);
real Ta_b=1, Tb_a=1;
reg [WIDTH-1:0] a_dly = 'bz, b_dly = 'bz;
always@(a) a_dly <= #(Ta_b) b_dly==={WIDTH{1'bz}} ? a : 'bz;
always@(b) b_dly <= #(Tb_a) a_dly==={WIDTH{1'bz}} ? b : 'bz;
assign b = a_dly, a = b_dly;
endmodule
Article: 115685On Feb 16, 4:14 am, Metin <meti...@gmx.de> wrote: > Hi there, > > I've heard that some Lattice FPGAs support M-LVDS signalling. > > Did anyone has any experience with lattice M-LVDS? Are they true M-LVDS driver/receivers? What are the deviations from the TIA/EIA-899 specification? Finally are They current-mode drivers? > > Thanks. The only support I've seen for M-LVDS from Lattice uses external resistors to emulate the spec. Check out the ECP2/M family datasheet figure 3-5 and Technote 1102.Article: 115686
I wrote a simple VHDL code using divide function. In Quartus II, it
work fine. A LPM divider was synthesized. However, same code in ISE, a
error " Operator <DIVIDE> must have constant operands or first operand
must be power of 2" was given.
Does it mean XST is not able to synthesize combinational divider?
Thanks
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
ENTITY divider IS
PORT
( op1, op2: IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
result : OUT STD_LOGIC_vector (7 downto 0)
);
END divider;
architecture rtl of divider is
begin
result<=conv_std_logic_vector (conv_integer(op1)/conv_integer (op2),
8);
end rtl;
Article: 115687Hi, I'm very interested in starting to learn about fpgas. I tried finding if there was anything about it at local colleges, but it seems a little to specialised! I'm quite adept at software engineering (C++/ Java etc...), but I haven't done any assembly, or worked very close with any hardware in any sense (except for PC maintenance ;) I've tried to do some rough research so that I would have some idea before I asked questions, and it seems that there are two main languages used (programming fpgas seems more popular than schematics from what I've seen), Verilog and VHDL. From what I've seen from the two languages, I think I'd prefer Verilog, but I can't work out if to use Verilog 2005 and SystemVerilog? Is this again a matter of perference or are there advantages and disadvantages to each? It seems SystemVerilog has a few more features that aren't in Verilog, giving it an edge over Verilog. If this is the case then perhaps SystemVerilog is the best thing? But it's here where things just disappear for me! I'm struggling with where go to after this? I'm expecting a very steep learning curve, but perhaps some resource (maybe a very good book on the subject for complete newbies) giving some direction from here would be nice. Thanks! :)Article: 115688
Hi, I wonder if someone could suggest an efficient LUT based signed multiplication algorithm for Virtex FPGAs. I've implemented an unsigned multiplier using the "computed partial product multipiler" algorithm described at: http://www.andraka.com/multipli.htm Is there some modification that will allow this to perform signed multiplication? Looking around google hasn't turned up much except a possible suggestion that a booth multiplier might be the way to go. Is this the right approach, and if so, does anyone know of a reference regarding mapping it to LUTs? Thanks, Andy.Article: 115689
Most synthesizers only support factor of 2 division. The XST manual (page 479) states that arithmetic division is supported only for powers of 2 http://toolbox.xilinx.com/docsan/xilinx9/books/docs/xst/xst.pdf The FPGA hardware needed to implement dividers is pretty slow so I wouldn't recommend just trying to have your code produce an LPM divider without understanding the delays you're going to experience. Also, the input/output sizes and known numerator limits relative to the denominator can *significantly* reduce the amount of logic needed. Dividers should be pretty easy to implement and should be optimized to your data flow for best results. If you have a specific implementation, I can rework an excel spreadsheet to show you how the data would flow with a fixed structure. You'd need to send me directly what your input sizes are and your desired output size along with the range of the numerator relative to the denominator; full (0->2^n-1)/(1->2^m-1) is much worse than if the numerator is always less than the denominator (or some fixed factor thereof). Also, signed versus unsigned is important for both factors. The Egyptian Division algorithm implemented in the spreadsheet lends itself directly to binary making the implementation simpler than the equivalent grade-school long division. I developed a nice pipelined best-fit divider (in my opinion) for a specific need in an ASIC-to-FPGA project algorithm conversion. - John_H "jasonL" <junsong.liao@gmail.com> wrote in message news:1171662816.846028.323670@j27g2000cwj.googlegroups.com... >I wrote a simple VHDL code using divide function. In Quartus II, it > work fine. A LPM divider was synthesized. However, same code in ISE, a > error " Operator <DIVIDE> must have constant operands or first operand > must be power of 2" was given. > > Does it mean XST is not able to synthesize combinational divider? > Thanks > > > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.std_logic_arith.all; > use IEEE.std_logic_unsigned.all; > > ENTITY divider IS > PORT > ( op1, op2: IN STD_LOGIC_VECTOR( 7 DOWNTO 0 ); > result : OUT STD_LOGIC_vector (7 downto 0) > ); > END divider; > > architecture rtl of divider is > begin > result<=conv_std_logic_vector (conv_integer(op1)/conv_integer (op2), > 8); > end rtl; >Article: 115690
<evilkidder@googlemail.com> wrote in message news:1171665126.779786.202250@v45g2000cwv.googlegroups.com... > Hi, > > I wonder if someone could suggest an efficient LUT based signed > multiplication algorithm for Virtex FPGAs. > > I've implemented an unsigned multiplier using the "computed partial > product multipiler" algorithm described at: > > http://www.andraka.com/multipli.htm > > Is there some modification that will allow this to perform signed > multiplication? > > Looking around google hasn't turned up much except a possible > suggestion that a booth multiplier might be the way to go. Is this > the right approach, and if so, does anyone know of a reference > regarding mapping it to LUTs? > > Thanks, > > Andy. "Efficiency" is to some degree relative. Are you looking for best LUT-based speed? Best area? It is an UTTER shame not to use the embedded multipliers in modern FPGAs. What size (including sign) for each of the input values? You want full output width, yes? Integers, right?Article: 115691
Tim wrote: > Peter Alfke wrote: > >> Do you like Virtex-5 ? Then please vote for it... > > > What do I do if I think Virtex-5 is really cool but no normal user can > take delivery of one? > > Most awards (e.g. the Oscars) are for products which are in meaningful > production. Which doesn't seem to be the case for Virtex-5, and for > Virtex-4, if distributor stockholdings are anything to go by. I don't know what the pricing on the Virtex-5 is going to look like, but there's a Virtex II Pro XC2VP100 chip in the Digi-Key catalog for $8400. I'm sure there is somebody, somewhere, who needs to miniaturize some system for an exotic, incredibly space-constrained application that can use something like this, or maybe the NSA needs it to crack codes or something. But, I can't possibly imagine a commercial product or even a research project that could rationally select a part that expensive. I also shudder to think of the CPU time and memory it will take to compile the config for that thing! We just bought a used minivan for slightly more that that price, and expect to get a LOT more use out of it than an $8400 chip. JonArticle: 115692
A book: (one of very many, this one is used by UC Berkeley) R. H. Katz, Contemporary Logic Design, Addison Wesley Publishing Company, Reading, MA, 1993. A source of stuff that universities and colleges actually use so you may find their course materials on line and follow along) http://www.digilentinc.com Such as: (one of hundreds) http://www.ece.unm.edu/vhdl/documents/d2sb_RM.pdf AustinArticle: 115693
Peter Alfke wrote: >On Feb 15, 5:06 pm, Tim <t...@nooospam.roockyloogic.com> wrote: > > >>Peter Alfke wrote: >> >> >>>Do you like Virtex-5 ? Then please vote for it... >>> >>> >>What do I do if I think Virtex-5 is really cool but no normal user can >>take delivery of one? >> >>Most awards (e.g. the Oscars) are for products which are in meaningful >>production. Which doesn't seem to be the case for Virtex-5, and for >>Virtex-4, if distributor stockholdings are anything to go by. >> >> > >Put in an order for 1000 pieces of any Virtex-5 LX or LXT (except >perhaps for the biggest -330 parts) with the ES suffix (early silicon >=with errata sheet), and watch us ship from inventory. > > > Oh, so I need to order 1000 pieces to get a prototype built? JonArticle: 115694
And, I forgot to mention that the cost of the Digilent (Spartan series) pcb's is designed to be like the cost of a textbook (but re-usable), so every student can afford one, and take their pcb through more than just one class (logic design, processor architectures, interfacing, etc...) AustinArticle: 115695
Tim wrote: > Peter Alfke wrote: > >> >> Put in an order for 1000 pieces of any Virtex-5 LX or LXT (except >> perhaps for the biggest -330 parts) with the ES suffix (early silicon >> =with errata sheet), and watch us ship from inventory. > > > Not practical. There is no published pricing for these parts and > distribution refuses to give pricing without an order. > > To be blunt, Peter, you know that I have the highest regard for > Xilinx, but the way you conduct your sales business these days is very > disheartening. An unblinking concentration on the major accounts is > just fine, but for the great majority of users: > > - you cannot buy the Virtex-5 > - you cannot buy most of the Virtex-4 range > - you cannot buy the Spartan-3E > - you cannot buy the Spartan-3A > - the Xilinx online store gives a new meaning to "store" > > If you think I'm exaggerating, try the Avnet site: > > Virtex-5 parts: all out of stock, no pricing > Virtex-4 parts: out of 243 parts (mostly priced!) just 59 are available > Spartan-3A parts: "Part is not found as a stocked item" > Spartan-3E parts: prototype parts only and no higher volume pricing > This is a really disturbing trend. For a while I thought this was a temporary disturbance due to the RoHS debacle, but I think it is far more serious than that. I think the entire electronic industry in the US is in a death spiral. There are just a RAFT of parts that I can no longer get, that were stocked by several distributors just a year ago. (TI, and others, may be partially responsible for this by producing literally DOZENS of variants on ordinary parts. Some of the old CMOS 74HC parts are now available in 5, 6 even 7 different packages, 3 temp ranges, and dozens of varying electrical and speed ranges. So, a 74HC04 now expands to fill half a page of type that requires a microscope to read in the digi-key catalog. I have a small pile of the wrong size chips that I bought by mistake because I can't remember the package suffix, but that's my fault. Who can possibly stock all these variants? I can't count the times in the last year or two that I've bought 5 parts to make a prototype, designed and debugged the board, and then had a mad scramble to try to obtain a small production quantity of several of the parts. Once I had Analog Devices quote me 120 weeks to obtain a certain part! A frantic search turned up a TI pin-compatible replacement at 1/6th the price! But, it sure got my blood pressure up until I had determined the substitute would actually work properly. The distributors have warehouses full of non-RoHS compliant parts they need to get rid of before they can fill them back up with more stuff they won't be able to move. And, I have all these non-franchised distributors of questionable reliability constantly calling me trying to sell me something! I NEVER buy from them, but they KEEP calling. JonArticle: 115696
On Feb 16, 10:52 pm, "John_H" <newsgr...@johnhandwork.com> wrote: > <evilkid...@googlemail.com> wrote in message > > news:1171665126.779786.202250@v45g2000cwv.googlegroups.com... > > > > > Hi, > > > I wonder if someone could suggest an efficient LUT based signed > > multiplication algorithm for Virtex FPGAs. > > > I've implemented an unsigned multiplier using the "computed partial > > product multipiler" algorithm described at: > > >http://www.andraka.com/multipli.htm > > > Is there some modification that will allow this to perform signed > > multiplication? > > > Looking around google hasn't turned up much except a possible > > suggestion that a booth multiplier might be the way to go. Is this > > the right approach, and if so, does anyone know of a reference > > regarding mapping it to LUTs? > > > Thanks, > > > Andy. > > "Efficiency" is to some degree relative. Are you looking for best LUT-based > speed? Best area? I am attempting to write a simple synthesizer for a HDL I have been working on so I guess I am looking for algorithms at both ends of the scale. To start with a reasonable trade-off between the two so I can get the initial implementation of the ground will be fine. > It is an UTTER shame not to use the embedded multipliers > in modern FPGAs. I will be using them based on some as yet undecided criteria. From what I've read it should be relatively easy to support, expect perhaps differences in "DSP" slices between architectures. I've yet to look into if a V4 will implement a mult18x18 primitive for example or if you need to use a dsp48. > > What size (including sign) for each of the input values? Basically any size. I intend to provide specific implementations for very small sizes but to start with I'll live with a generic version. > You want full output width, yes? Yes. Again there will probably be some scope for optimisation in this regard later on, but for now my languages multiplier primitive is M*N - > M+N. > Integers, right? If you mean twos complement, then yes. Thanks, Andy.Article: 115697
bitsbytesandbugs@googlemail.com wrote: > Hi, > > I'm very interested in starting to learn about fpgas. I tried finding ... > But it's here where things just disappear for me! I'm struggling with > where go to after this? I'm expecting a very steep learning curve, but > perhaps some resource (maybe a very good book on the subject for > complete newbies) giving some direction from here would be nice. The following site shows how to use Verilog with lots of simple but instructive examples. Additionally there are references to short and efficient verilog and vhdl courses on the net: http://www.fpga4fun.com/ A very good short introduction to Verilog is (in my opinion): Introduction to Verilog, Peter M. Nyasulu www.doe.carleton.ca/~shams/97350/PetervrlK.pdf Using the two references above I was able to complete some small designs (4x7 Segment LED, PS/2 Keyboard reader, VGA with text-output) in a very short time (with ISE WebPack and a Spartan 3 evaluation board from Digilent/Xilinx) If you want to find more infos, look at my linkpage: http://www.aviduratas.de/links/projekte_fpga.html A very thorough self learning course for Verilog on the web is: http://vol.verilog.com/ It covers also the aspects of Verilog as a simulation language - I have just leafed through it a little, but it is provided as an add-on to the book of Patterson and Hennessy, "Computer Organization and Design", so it should be of high quality. Greetings Jürgen -- Jürgen Böhm www.aviduratas.de "At a time when so many scholars in the world are calculating, is it not desirable that some, who can, dream ?" R. ThomArticle: 115698
Colin Paul Gloster wrote: > I checked the price of a component (not an F.P.G.A. though) we needed > on a few websites in December 2006. One of them was Avnet's and > Avnet's website had the engineering (prototype, commercial quality) > model priced at $11122.80 whereas Avnet's website had the radiation > hardened space qualified (better quality) version priced much less at > $3738. I performed this search due to miscommunication: we had > actually already bought the radiation hardened version before December > for far less than $5000 (though I do not know for how much exactly, > nor from whom). Impressive. And six significant figures in the $11122.80 pricing! What sort of component? As I recall, the most expensive Xilinx FPGA is around $9800.Article: 115699
On Fri, 16 Feb 2007 18:17:02 GMT, "Michael A. Terrell" <mike.terrell@earthlink.net> Gave us: >John Larkin wrote: >> >> Please post the schematic of a zero-ripple switcher. >> >> John > > > Sorry, but that feature is only available on the 0 volt model. Are they fooly regulated?
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